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| author | Ingo Molnar <mingo@elte.hu> | 2009-03-13 05:54:43 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-13 05:54:43 +0100 |
| commit | 17d85bc7564571a1cce23ffdb2d2a33301876925 (patch) | |
| tree | 815bfc3a02e94303c7c834770bf2a17012c10bf8 /arch/mips/include/asm/prefetch.h | |
| parent | d95c3578120e5bc4784069439f00ccb1b5f87717 (diff) | |
| parent | 041b62374c7fedc11a8a1eeda2868612d3d1436c (diff) | |
Merge commit 'v2.6.29-rc8' into cpus4096
Diffstat (limited to 'arch/mips/include/asm/prefetch.h')
| -rw-r--r-- | arch/mips/include/asm/prefetch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb..a56594f360e 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h @@ -26,7 +26,7 @@ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in * current versions due to erratum G105. * - * VR7701 only implements the Load prefetch. + * VR5500 (including VR5701 and VR7701) only implement load prefetch. * * Finally MIPS32 and MIPS64 implement all of the following hints. */ |