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authorIngo Molnar <mingo@elte.hu>2008-10-12 11:32:17 +0200
committerIngo Molnar <mingo@elte.hu>2008-10-12 11:32:17 +0200
commit206855c321adee56db3946ca09a5887cddb9d598 (patch)
tree13a2729d4d0e37170552bd9ad3c6bba71ba0c55c /arch/mips/include/asm/tlb.h
parente8d3f455de4f42d4bab2f6f1aeb2cf3bd18eb508 (diff)
parentcb58ffc3889f0545628f138f849e759a331b8ddc (diff)
Merge branch 'x86/urgent' into core/signal
Conflicts: arch/x86/kernel/signal_64.c
Diffstat (limited to 'arch/mips/include/asm/tlb.h')
-rw-r--r--arch/mips/include/asm/tlb.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
new file mode 100644
index 00000000000..80d9dfcf1e8
--- /dev/null
+++ b/arch/mips/include/asm/tlb.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_TLB_H
+#define __ASM_TLB_H
+
+/*
+ * MIPS doesn't need any special per-pte or per-vma handling, except
+ * we need to flush cache for area to be unmapped.
+ */
+#define tlb_start_vma(tlb, vma) \
+ do { \
+ if (!tlb->fullmm) \
+ flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+ } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it fills up.
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* __ASM_TLB_H */