diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
| commit | 0d4a42f6bd298e826620585e766a154ab460617a (patch) | |
| tree | 406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/mips/include/uapi/asm/cachectl.h | |
| parent | d62b4892f3d9f7dd2002e5309be10719d6805b0f (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes,
which depend upon the new for_each_sg_page introduce in
commit a321e91b6d73ed011ffceed384c40d2785cf723b
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Feb 27 17:02:56 2013 -0800
lib/scatterlist: add simple page iterator
The merge itself is just two trivial conflicts:
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/mips/include/uapi/asm/cachectl.h')
| -rw-r--r-- | arch/mips/include/uapi/asm/cachectl.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/include/uapi/asm/cachectl.h b/arch/mips/include/uapi/asm/cachectl.h index f3ce721861d..23039090877 100644 --- a/arch/mips/include/uapi/asm/cachectl.h +++ b/arch/mips/include/uapi/asm/cachectl.h @@ -5,15 +5,15 @@ * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL /* * Options for cacheflush system call */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ /* * Caching modes for the cachectl(2) call |