Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (27 commits)
  MIPS: Alchemy: time.c build fix
  MIPS: RB532: Export rb532_gpio_set_func()
  MIPS: RB532: Update headers
  MIPS: RB532: Simplify dev3 init
  MIPS: RB532: Remove {get,set}_434_reg()
  MIPS: RB532: Move dev3 init code to devices.c
  MIPS: RB532: Fix set_latch_u5()
  MIPS: RB532: Fix init of rb532_dev3_ctl_res
  MIPS: RB532: Use driver_data instead of platform_data
  MIPS: RB532: Detect uart type, add platform device
  MIPS: RB532: remove useless CF GPIO initialisation
  MIPS: RB532: Auto disable GPIO alternate function
  MIPS: RB532: Add set_type() function to IRQ struct.
  MIPS: RC32434: Define io_map_base for PCI controller
  MIPS: RB532: Fix bit swapping in rb532_set_bit()
  MIPS: Use hardware watchpoints on all R1 and R2 CPUs.
  MIPS: Read watch registers with interrupts disabled.
  MIPS: Fix a typo in watchpoint register structure.
  MIPS: TXx9: Add support for TX4939 internal RTC
  MIPS: R2: Fix broken installation of cache error handler.
  ...

1 files changed, 21 insertions, 1 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6e99665ae86..c43f4b26a69 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -618,15 +618,35 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 	if (cpu_has_inclusive_pcaches) {
 		if (size >= scache_size)
 			r4k_blast_scache();
-		else
+		else {
+			unsigned long lsize = cpu_scache_line_size();
+			unsigned long almask = ~(lsize - 1);
+
+			/*
+			 * There is no clearly documented alignment requirement
+			 * for the cache instruction on MIPS processors and
+			 * some processors, among them the RM5200 and RM7000
+			 * QED processors will throw an address error for cache
+			 * hit ops with insufficient alignment.  Solved by
+			 * aligning the address to cache line size.
+			 */
+			cache_op(Hit_Writeback_Inv_SD, addr & almask);
+			cache_op(Hit_Writeback_Inv_SD,
+				 (addr + size - 1) & almask);
 			blast_inv_scache_range(addr, addr + size);
+		}
 		return;
 	}
 
 	if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 		r4k_blast_dcache();
 	} else {
+		unsigned long lsize = cpu_dcache_line_size();
+		unsigned long almask = ~(lsize - 1);
+
 		R4600_HIT_CACHEOP_WAR_IMPL;
+		cache_op(Hit_Writeback_Inv_D, addr & almask);
+		cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
 		blast_inv_dcache_range(addr, addr + size);
 	}