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authorOlof Johansson <olof@lixom.net>2013-08-11 15:33:54 -0700
committerOlof Johansson <olof@lixom.net>2013-08-11 15:33:54 -0700
commit4ddbed9618724d52a7a79c1e10ef5adb46fcccf7 (patch)
treeffe64efb333d7dcdb5b2cf43ffef97b25261702c /arch/mips/mm/page.c
parent16649596d701c0f4f767bbcad7da4d6343ba8a9e (diff)
parentfa8c5a811e0e7c3e1c49b2e58fcb4db549b5719a (diff)
Merge tag 'boards-3.12' of git://git.infradead.org/linux-mvebu into next/boards
From Jason Cooper: mvebu boards changes for v3.12 - convert kirkwood, dove, orion5x to DT init of mv643xx_eth - _lots_ of board code removal :) - convert kirkwood, dove and orion5x to DT init of clocksource and irqchip * tag 'boards-3.12' of git://git.infradead.org/linux-mvebu: ARM: plat-orion: add reg offset to DT irq driver stub ARM: kirkwood: remove obsolete SDIO clock gate workaround ARM: kirkwood: convert to DT irqchip and clocksource ARM: dove: convert to DT irqchip and clocksource ARM: orion5x: update intc device tree node to new reg layout ARM: kirkwood: move device tree nodes to DT irqchip and clocksource ARM: dove: move device tree nodes to DT irqchip and clocksource ARM: orion5x: remove legacy mv643xx_eth board setup ARM: kirkwood: remove legacy clk alias for mv643xx_eth ARM: kirkwood: remove redundant DT board files ARM: dove: remove legacy mv643xx_eth setup ARM: orion5x: add gigabit ethernet and mvmdio device tree nodes ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes ARM: dove: add gigabit ethernet and mvmdio device tree nodes + Linux 3.11-rc2 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/mips/mm/page.c')
-rw-r--r--arch/mips/mm/page.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 2c0bd580b9d..218c2109a55 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -66,29 +66,29 @@ UASM_L_LA(_copy_pref_both)
UASM_L_LA(_copy_pref_store)
/* We need one branch and therefore one relocation per target label. */
-static struct uasm_label __cpuinitdata labels[5];
-static struct uasm_reloc __cpuinitdata relocs[5];
+static struct uasm_label labels[5];
+static struct uasm_reloc relocs[5];
#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
-static int pref_bias_clear_store __cpuinitdata;
-static int pref_bias_copy_load __cpuinitdata;
-static int pref_bias_copy_store __cpuinitdata;
+static int pref_bias_clear_store;
+static int pref_bias_copy_load;
+static int pref_bias_copy_store;
-static u32 pref_src_mode __cpuinitdata;
-static u32 pref_dst_mode __cpuinitdata;
+static u32 pref_src_mode;
+static u32 pref_dst_mode;
-static int clear_word_size __cpuinitdata;
-static int copy_word_size __cpuinitdata;
+static int clear_word_size;
+static int copy_word_size;
-static int half_clear_loop_size __cpuinitdata;
-static int half_copy_loop_size __cpuinitdata;
+static int half_clear_loop_size;
+static int half_copy_loop_size;
-static int cache_line_size __cpuinitdata;
+static int cache_line_size;
#define cache_line_mask() (cache_line_size - 1)
-static inline void __cpuinit
+static inline void
pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
{
if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
@@ -108,7 +108,7 @@ pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
}
}
-static void __cpuinit set_prefetch_parameters(void)
+static void set_prefetch_parameters(void)
{
if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg)
clear_word_size = 8;
@@ -199,7 +199,7 @@ static void __cpuinit set_prefetch_parameters(void)
4 * copy_word_size));
}
-static void __cpuinit build_clear_store(u32 **buf, int off)
+static void build_clear_store(u32 **buf, int off)
{
if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
uasm_i_sd(buf, ZERO, off, A0);
@@ -208,7 +208,7 @@ static void __cpuinit build_clear_store(u32 **buf, int off)
}
}
-static inline void __cpuinit build_clear_pref(u32 **buf, int off)
+static inline void build_clear_pref(u32 **buf, int off)
{
if (off & cache_line_mask())
return;
@@ -240,7 +240,7 @@ extern u32 __clear_page_end;
extern u32 __copy_page_start;
extern u32 __copy_page_end;
-void __cpuinit build_clear_page(void)
+void build_clear_page(void)
{
int off;
u32 *buf = &__clear_page_start;
@@ -333,7 +333,7 @@ void __cpuinit build_clear_page(void)
pr_debug("\t.set pop\n");
}
-static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
+static void build_copy_load(u32 **buf, int reg, int off)
{
if (cpu_has_64bit_gp_regs) {
uasm_i_ld(buf, reg, off, A1);
@@ -342,7 +342,7 @@ static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
}
}
-static void __cpuinit build_copy_store(u32 **buf, int reg, int off)
+static void build_copy_store(u32 **buf, int reg, int off)
{
if (cpu_has_64bit_gp_regs) {
uasm_i_sd(buf, reg, off, A0);
@@ -387,7 +387,7 @@ static inline void build_copy_store_pref(u32 **buf, int off)
}
}
-void __cpuinit build_copy_page(void)
+void build_copy_page(void)
{
int off;
u32 *buf = &__copy_page_start;