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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-06-05 14:29:53 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-06-05 14:29:53 -0700 |
| commit | 5965087dc96167298ab83598f681d4d6f9d324fa (patch) | |
| tree | 97feb8d8a546261de23024d5b4ee5797b03f988a /arch/mips/mm/page.c | |
| parent | 698f7a4a12c15fef354b2a1ac14f90a0e71008d9 (diff) | |
| parent | cd9da13d6ef4f4b652a9a885d4a7c80e40fed229 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
Fix divide by zero error in build_clear_page() and build_copy_page()
[MIPS] Fix typo in header guard
[MIPS] Fix build error - Delete debugging crap that crept in with CMP
[MIPS] Add accessors for random register.
[MIPS] IP27: misc fixes
[MIPS] IP27: Fix clockevent setup
[MIPS] IP27: Fix bootmem memory setup
[MIPS] remove CONFIG_CPU_R4000 line from Makefile
[MIPS] Fix check for valid stack pointer during backtrace
[MIPS] Add missing braces to pte_mkyoung
[MIPS] R4700: Fix build_tlb_probe_entry
[MIPS] Alchemy: dbdma: add API to delete custom DDMA device ids.
[MIPS] Alchemy: export get_au1x00_speed for modules
Diffstat (limited to 'arch/mips/mm/page.c')
| -rw-r--r-- | arch/mips/mm/page.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index d827d614436..cab81f42eee 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -310,8 +310,8 @@ void __cpuinit build_clear_page(void) if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) uasm_i_lui(&buf, AT, 0xa000); - off = min(8, pref_bias_clear_store / cache_line_size) * - cache_line_size; + off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) + * cache_line_size : 0; while (off) { build_clear_pref(&buf, -off); off -= cache_line_size; @@ -454,12 +454,14 @@ void __cpuinit build_copy_page(void) if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) uasm_i_lui(&buf, AT, 0xa000); - off = min(8, pref_bias_copy_load / cache_line_size) * cache_line_size; + off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * + cache_line_size : 0; while (off) { build_copy_load_pref(&buf, -off); off -= cache_line_size; } - off = min(8, pref_bias_copy_store / cache_line_size) * cache_line_size; + off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * + cache_line_size : 0; while (off) { build_copy_store_pref(&buf, -off); off -= cache_line_size; |