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| author | James Morris <jmorris@namei.org> | 2011-04-19 21:32:41 +1000 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2011-04-19 21:32:41 +1000 |
| commit | d4ab4e6a23f805abb8fc3cc34525eec3788aeca1 (patch) | |
| tree | eefd82c155bc27469a85667d759cd90facf4a6e3 /arch/mips/mm/tlbex.c | |
| parent | c0fa797ae6cd02ff87c0bfe0d509368a3b45640e (diff) | |
| parent | 96fd2d57b8252e16dfacf8941f7a74a6119197f5 (diff) | |
Merge branch 'master'; commit 'v2.6.39-rc3' into next
Diffstat (limited to 'arch/mips/mm/tlbex.c')
| -rw-r--r-- | arch/mips/mm/tlbex.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 04f9e17db9d..5ef294fbb6e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -352,7 +352,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) /* * Write random or indexed TLB entry, and care about the hazards from - * the preceeding mtc0 and for the following eret. + * the preceding mtc0 and for the following eret. */ enum tlb_write_entry { tlb_random, tlb_indexed }; |