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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-29 11:13:10 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-29 11:13:10 -0700
commitb77d643ced576bdd1e918aebda869de74696cde9 (patch)
treebb5d708f4bbb48461923a28e63a8cf8bdd477dd7 /arch/mips/pci/pcie-octeon.c
parentb4020c1b198c0f0c0b0ff0cfdd824a26b93edd6f (diff)
parent64575f918f3279d8487cf670dbefa956ce16a526 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (46 commits) ftrace/MIPS: Enable C Version of recordmcount ftrace/MIPS: Add module support for C version of recordmcount ftrace/MIPS: Add MIPS64 support for C version of recordmcount MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes. MIPS: Allow UserLocal on MIPS_R1 processors MIPS: Honor L2 bypass bit MIPS: Add BMIPS CP0 register definitions MIPS: Add BMIPS processor types to Kconfig MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code MIPS: Add support for hardware performance events (mipsxx) MIPS: Perf-events: Add callchain support MIPS: add support for hardware performance events (skeleton) MIPS: add support for software performance events MIPS: define local_xchg from xchg_local to atomic_long_xchg MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant MIPS: AR7: Initialize GPIO earlier MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI USB: Add EHCI and OHCH glue for OCTEON II SOCs. MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic. MIPS: Octeon: Apply CN63XXP1 errata workarounds. ...
Diffstat (limited to 'arch/mips/pci/pcie-octeon.c')
-rw-r--r--arch/mips/pci/pcie-octeon.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 861361e0c9a..385f035b24e 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -75,6 +75,8 @@ union cvmx_pcie_address {
} mem;
};
+#include <dma-coherence.h>
+
/**
* Return the Core virtual base address for PCIe IO access. IOs are
* read/written as an offset from this address.
@@ -1391,6 +1393,9 @@ static int __init octeon_pcie_setup(void)
cvmx_pcie_get_io_size(1) - 1;
register_pci_controller(&octeon_pcie1_controller);
}
+
+ octeon_pci_dma_init();
+
return 0;
}