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authorJonas Gorski <jonas.gorski@gmail.com>2012-10-28 11:49:53 +0000
committerJohn Crispin <blogic@openwrt.org>2012-11-09 11:37:17 +0100
commitf2d1035e956052d29c83fe8f8da0d056af6d221a (patch)
tree1cb6769113f52ebf6e4457b6ec0adc38e7886e0b /arch/mips
parentb8ebbaff03798180c4d9661105670e03276afe83 (diff)
MIPS: BCM63XX: add and use a clock for PCIe
Add a PCIe clock and use that instead of directly touching the clock control register. While at it, fail if there is no such clock. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4452 Signed-off-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/bcm63xx/clk.c15
-rw-r--r--arch/mips/pci/pci-bcm63xx.c15
2 files changed, 25 insertions, 5 deletions
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index dff79ab6005..89a5fb07786 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -253,6 +253,19 @@ static struct clk clk_ipsec = {
};
/*
+ * PCIe clock
+ */
+
+static void pcie_set(struct clk *clk, int enable)
+{
+ bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+}
+
+static struct clk clk_pcie = {
+ .set = pcie_set,
+};
+
+/*
* Internal peripheral clock
*/
static struct clk clk_periph = {
@@ -313,6 +326,8 @@ struct clk *clk_get(struct device *dev, const char *id)
return &clk_pcm;
if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
return &clk_ipsec;
+ if (BCMCPU_IS_6328() && !strcmp(id, "pcie"))
+ return &clk_pcie;
return ERR_PTR(-ENOENT);
}
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 8a48139d219..fa8c320936f 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
+#include <linux/clk.h>
#include <asm/bootinfo.h>
#include "pci-bcm63xx.h"
@@ -119,11 +120,6 @@ static void __init bcm63xx_reset_pcie(void)
{
u32 val;
- /* enable clock */
- val = bcm_perf_readl(PERF_CKCTL_REG);
- val |= CKCTL_6328_PCIE_EN;
- bcm_perf_writel(val, PERF_CKCTL_REG);
-
/* enable SERDES */
val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
@@ -150,10 +146,19 @@ static void __init bcm63xx_reset_pcie(void)
mdelay(200);
}
+static struct clk *pcie_clk;
+
static int __init bcm63xx_register_pcie(void)
{
u32 val;
+ /* enable clock */
+ pcie_clk = clk_get(NULL, "pcie");
+ if (IS_ERR_OR_NULL(pcie_clk))
+ return -ENODEV;
+
+ clk_prepare_enable(pcie_clk);
+
bcm63xx_reset_pcie();
/* configure the PCIe bridge */