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authorShaohui Xie <b21989@freescale.com>2010-11-03 17:36:37 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-01-12 18:00:29 -0600
commitb5fb0cc7f1c90e3b00d40b64681efcbf8bcdeb9e (patch)
treed921754dbd842f07a23eefbd569fcc8d1c1bd182 /arch/powerpc/kernel/cpu_setup_fsl_booke.S
parent86985db66ea2fda174615be05112a7d1b13645c4 (diff)
powerpc/fsl_rio: Fix non-standard HID1 register access
Moved setting of RFXE bit so we get machine checks on RIO errors into cpu_setup so that the RIO code isn't core specific. Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Li Yang <leoli@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com> Cc: Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_fsl_booke.S')
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 894e64fa481..5c518ad3445 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -64,6 +64,12 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
+#ifdef CONFIG_RAPIDIO
+ /* Ensure that RFXE is set */
+ mfspr r3,SPRN_HID1
+ oris r3,r3,HID1_RFXE@h
+ mtspr SPRN_HID1,r3
+#endif
mtlr r4
blr
_GLOBAL(__setup_cpu_e500mc)