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authorTrent Piepho <tpiepho@freescale.com>2008-12-17 11:43:26 -0800
committerKumar Gala <galak@kernel.crashing.org>2009-01-07 15:33:05 -0600
commit565f37642c78754a85efe6c20a4a15e18ed21f07 (patch)
tree59d91974af64223e2891cddfe9ce2e58ada8109d /arch/powerpc/mm
parenta097a78c1e6e4030fcef3bcab6351b6001662335 (diff)
powerpc/fsl-pci: Set relaxed ordering on prefetchable ranges
Provides a small speedup when accessing pefetchable ranges. To indicate that a memory range is prefetchable, mark it in the dts file with 42000000 instead of 02000000. A powepc pci_controller is allowed three memory ranges, any of which may be prefetchable. However, the PCI-PCI bridge configuration space only has one field for "non-prefetchable memory behind bridge", which has a 32 bit address, and one field for "prefetchable memory behind bridge", which may have a 64 bit address. These are PCI bus addresses, not CPU physical addresses. So really you're only allowed one memory range of each type. And if you want the range at a PCI address above 32 bits you must make it prefetchable. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm')
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