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authorMichael Ellerman <michael@ellerman.id.au>2007-07-20 21:39:28 +0200
committerArnd Bergmann <arnd@klappe.arndb.de>2007-07-20 21:41:45 +0200
commitce21b3c9648ae55181787bf25ee00cf91dfd5c91 (patch)
tree9d2d22d9eab0a2621e29bc237fd1be7f3ea1f46c /arch/powerpc/platforms/cell/Makefile
parent8d2655e621bfc3c3f925016f881a36739d479f69 (diff)
[CELL] add support for MSI on Axon-based Cell systems
This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Diffstat (limited to 'arch/powerpc/platforms/cell/Makefile')
-rw-r--r--arch/powerpc/platforms/cell/Makefile2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index be059718bec..f88a7c76f29 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -25,3 +25,5 @@ obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \
$(spu-priv1-y) \
$(spu-manage-y) \
spufs/
+
+obj-$(CONFIG_PCI_MSI) += axon_msi.o