diff options
author | Vitaly Bordug <vbordug@ru.mvista.com> | 2006-09-21 22:31:26 +0400 |
---|---|---|
committer | Vitaly Bordug <vbordug@ru.mvista.com> | 2006-09-21 22:31:26 +0400 |
commit | 902f392d011d0a781ea4695c464345faa6664540 (patch) | |
tree | d47305185bba9e2c1d1cc5a7a87aeba7b3c64aa7 /arch/powerpc/platforms | |
parent | b0c110b4f19b226dcc9f7805759bf17f8ef4dca4 (diff) |
POWERPC: Add support for the mpc8560 eval board
This makes the 8560 evaluation board fully supported under arch/powerpc,
as the first board with CPM2 SoC peripherals. The brand new devicetree
nodes are introduced (intending to be a subset of the QuiccEngine-equipped
models, with dts sources placed into the kernel according to the new convention.
Assuming all the preceding stuff applied (PAL+fs_enet related+ CPM_UART
update), the both TSEC eth ,FCC Eths, and both SCC UARTs are
working. The relevant drivers are still capable to drive users in ppc,
which was verified with 8272ADS (SCC uart+FCC eth).
This is also verified on mpc8540 and actually make it work (PCI stuff
working as well)
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r-- | arch/powerpc/platforms/85xx/Kconfig | 21 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/Makefile | 1 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_ads.c | 109 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_ads.h | 61 |
4 files changed, 192 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index c3268d9877e..0584f3c7e88 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -11,6 +11,12 @@ config MPC8540_ADS help This option enables support for the MPC 8540 ADS board +config MPC8560_ADS + bool "Freescale MPC8560 ADS" + select DEFAULT_UIMAGE + help + This option enables support for the MPC 8560 ADS board + config MPC85xx_CDS bool "Freescale MPC85xx CDS" select DEFAULT_UIMAGE @@ -25,6 +31,11 @@ config MPC8540 select PPC_INDIRECT_PCI default y if MPC8540_ADS || MPC85xx_CDS +config MPC8560 + bool + select PPC_INDIRECT_PCI + default y if MPC8560_ADS + config PPC_INDIRECT_PCI_BE bool depends on PPC_85xx @@ -34,4 +45,14 @@ config MPIC bool default y +config CPM2 + bool + depends on MPC8560 + default y + help + The CPM2 (Communications Processor Module) is a coprocessor on + embedded CPUs made by Motorola. Selecting this option means that + you wish to build a kernel for a machine with a CPM2 coprocessor + on it. + endmenu diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 7615aa59c78..282f5d0d015 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -3,4 +3,5 @@ # obj-$(CONFIG_PPC_85xx) += misc.o pci.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o +obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index cae6b73357d..7ebfe74bde4 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c @@ -32,6 +32,12 @@ #include <sysdev/fsl_soc.h> #include "mpc85xx.h" +#ifdef CONFIG_CPM2 +#include <asm/cpm2.h> +#include <sysdev/cpm2_pic.h> +#include <asm/fs_pd.h> +#endif + #ifndef CONFIG_PCI unsigned long isa_io_base = 0; unsigned long isa_mem_base = 0; @@ -57,12 +63,29 @@ mpc85xx_pcibios_fixup(void) } #endif /* CONFIG_PCI */ +#ifdef CONFIG_CPM2 + +static void cpm2_cascade(unsigned int irq, struct irq_desc *desc, + struct pt_regs *regs) +{ + int cascade_irq; + + while ((cascade_irq = cpm2_get_irq(regs)) >= 0) { + generic_handle_irq(cascade_irq, regs); + } + desc->chip->eoi(irq); +} + +#endif /* CONFIG_CPM2 */ void __init mpc85xx_ads_pic_init(void) { struct mpic *mpic; struct resource r; struct device_node *np = NULL; +#ifdef CONFIG_CPM2 + int irq; +#endif np = of_find_node_by_type(np, "open-pic"); @@ -104,11 +127,92 @@ void __init mpc85xx_ads_pic_init(void) mpic_assign_isu(mpic, 14, r.start + 0x10100); mpic_init(mpic); + +#ifdef CONFIG_CPM2 + /* Setup CPM2 PIC */ + np = of_find_node_by_type(NULL, "cpm-pic"); + if (np == NULL) { + printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); + return; + } + irq = irq_of_parse_and_map(np, 0); + + cpm2_pic_init(np); + set_irq_chained_handler(irq, cpm2_cascade); +#endif } /* * Setup the architecture */ +#ifdef CONFIG_CPM2 +static void init_fcc_ioports(void) +{ + struct immap *immap; + struct io_port *io; + u32 tempval; + + immap = cpm2_immr; + + io = &immap->im_ioport; + /* FCC2/3 are on the ports B/C. */ + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB2_DIRB0; + tempval |= PB2_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB2_PSORB0; + tempval |= PB2_PSORB1; + out_be32(&io->iop_psorb, tempval); + + tempval = in_be32(&io->iop_pparb); + tempval |= (PB2_DIRB0 | PB2_DIRB1); + out_be32(&io->iop_pparb, tempval); + + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB3_DIRB0; + tempval |= PB3_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB3_PSORB0; + tempval |= PB3_PSORB1; + out_be32(&io->iop_psorb, tempval); + + tempval = in_be32(&io->iop_pparb); + tempval |= (PB3_DIRB0 | PB3_DIRB1); + out_be32(&io->iop_pparb, tempval); + + tempval = in_be32(&io->iop_pdirc); + tempval |= PC3_DIRC1; + out_be32(&io->iop_pdirc, tempval); + + tempval = in_be32(&io->iop_pparc); + tempval |= PC3_DIRC1; + out_be32(&io->iop_pparc, tempval); + + /* Port C has clocks...... */ + tempval = in_be32(&io->iop_psorc); + tempval &= ~(CLK_TRX); + out_be32(&io->iop_psorc, tempval); + + tempval = in_be32(&io->iop_pdirc); + tempval &= ~(CLK_TRX); + out_be32(&io->iop_pdirc, tempval); + tempval = in_be32(&io->iop_pparc); + tempval |= (CLK_TRX); + out_be32(&io->iop_pparc, tempval); + + /* Configure Serial Interface clock routing. + * First, clear all FCC bits to zero, + * then set the ones we want. + */ + immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK); + immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE; +} +#endif + static void __init mpc85xx_ads_setup_arch(void) { struct device_node *cpu; @@ -131,6 +235,11 @@ static void __init mpc85xx_ads_setup_arch(void) of_node_put(cpu); } +#ifdef CONFIG_CPM2 + cpm2_reset(); + init_fcc_ioports(); +#endif + #ifdef CONFIG_PCI for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) add_bridge(np); diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.h b/arch/powerpc/platforms/85xx/mpc85xx_ads.h new file mode 100644 index 00000000000..effcbf78f85 --- /dev/null +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.h @@ -0,0 +1,61 @@ +/* + * MPC85xx ADS board definitions + * + * Maintainer: Kumar Gala <galak@kernel.crashing.org> + * + * Copyright 2004 Freescale Semiconductor Inc. + * + * 2006 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __MACH_MPC85XXADS_H +#define __MACH_MPC85XXADS_H + +#include <linux/config.h> +#include <linux/initrd.h> +#include <sysdev/fsl_soc.h> + +#define BCSR_ADDR ((uint)0xf8000000) +#define BCSR_SIZE ((uint)(32 * 1024)) + +#ifdef CONFIG_CPM2 + +#define MPC85xx_CPM_OFFSET (0x80000) + +#define CPM_MAP_ADDR (get_immrbase() + MPC85xx_CPM_OFFSET) +#define CPM_IRQ_OFFSET 60 + +#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) +#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) +#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) +#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) +#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) +#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) + +/* FCC1 Clock Source Configuration. These can be + * redefined in the board specific file. + * Can only choose from CLK9-12 */ +#define F1_RXCLK 12 +#define F1_TXCLK 11 + +/* FCC2 Clock Source Configuration. These can be + * redefined in the board specific file. + * Can only choose from CLK13-16 */ +#define F2_RXCLK 13 +#define F2_TXCLK 14 + +/* FCC3 Clock Source Configuration. These can be + * redefined in the board specific file. + * Can only choose from CLK13-16 */ +#define F3_RXCLK 15 +#define F3_TXCLK 16 + +#endif /* CONFIG_CPM2 */ +#endif /* __MACH_MPC85XXADS_H */ |