diff options
| author | Dmitry Torokhov <dtor_core@ameritech.net> | 2006-04-02 00:08:05 -0500 |
|---|---|---|
| committer | Dmitry Torokhov <dtor_core@ameritech.net> | 2006-04-02 00:08:05 -0500 |
| commit | 95d465fd750897ab32462a6702fbfe1b122cbbc0 (patch) | |
| tree | 65c38b2f11c51bb6932e44dd6c92f15b0091abfe /arch/ppc/platforms | |
| parent | 642fde17dceceb56c7ba2762733ac688666ae657 (diff) | |
| parent | 683aa4012f53b2ada0f430487e05d37b0d94e90a (diff) | |
Manual merge with Linus.
Conflicts:
arch/powerpc/kernel/setup-common.c
drivers/input/keyboard/hil_kbd.c
drivers/input/mouse/hil_ptr.c
Diffstat (limited to 'arch/ppc/platforms')
125 files changed, 1747 insertions, 2091 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index d8837911bbc..174ddbc9758 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -57,6 +57,10 @@ config XILINX_ML300 help This option enables support for the Xilinx ML300 evaluation board. +config XILINX_ML403 + bool "Xilinx-ML403" + help + This option enables support for the Xilinx ML403 evaluation board. endchoice choice @@ -172,11 +176,6 @@ config IBM_OCP depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT default y -config XILINX_OCP - bool - depends on XILINX_ML300 - default y - config IBM_EMAC4 bool depends on 440GX || 440SP || 440SPE @@ -208,11 +207,21 @@ config 405GPR depends on SYCAMORE default y -config VIRTEX_II_PRO +config XILINX_VIRTEX_II_PRO bool depends on XILINX_ML300 default y +config XILINX_VIRTEX_4_FX + bool + depends on XILINX_ML403 + default y + +config XILINX_VIRTEX + bool + depends on XILINX_VIRTEX_II_PRO || XILINX_VIRTEX_4_FX + default y + config STB03xxx bool depends on REDWOOD_5 || REDWOOD_6 @@ -220,7 +229,7 @@ config STB03xxx config EMBEDDEDBOOT bool - depends on EP405 || XILINX_ML300 + depends on EP405 || XILINX_ML300 || XILINX_ML403 default y config IBM_OPENBIOS diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index c9bb6117095..a04a0d0a0f5 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_REDWOOD_6) += redwood6.o obj-$(CONFIG_SYCAMORE) += sycamore.o obj-$(CONFIG_WALNUT) += walnut.o obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o +obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o obj-$(CONFIG_405GP) += ibm405gp.o obj-$(CONFIG_REDWOOD_5) += ibmstb4.o @@ -26,4 +27,5 @@ obj-$(CONFIG_440SP) += ibm440sp.o obj-$(CONFIG_440SPE) += ppc440spe.o obj-$(CONFIG_405EP) += ibm405ep.o obj-$(CONFIG_405GPR) += ibm405gpr.o -obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o +obj-$(CONFIG_XILINX_VIRTEX) += virtex.o + diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c index 0ec53f04933..b940cfd646c 100644 --- a/arch/ppc/platforms/4xx/bamboo.c +++ b/arch/ppc/platforms/4xx/bamboo.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/bamboo.c - * * Bamboo board specific routines * * Wade Farnsworth <wfarnsworth@mvista.com> diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h index 5c019282649..31c0dd6a26c 100644 --- a/arch/ppc/platforms/4xx/bamboo.h +++ b/arch/ppc/platforms/4xx/bamboo.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/bamboo.h - * * Bamboo board definitions * * Wade Farnsworth <wfarnsworth@mvista.com> diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h index b5380cfaf5c..606aa9fa5ca 100644 --- a/arch/ppc/platforms/4xx/bubinga.h +++ b/arch/ppc/platforms/4xx/bubinga.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/bubinga.h - * * Bubinga board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c index ff966773a0b..6571e39fbe4 100644 --- a/arch/ppc/platforms/4xx/cpci405.c +++ b/arch/ppc/platforms/4xx/cpci405.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/cpci405.c - * * Board setup routines for the esd CPCI-405 cPCI Board. * * Author: Stefan Roese diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index 9a828b62341..b4ecb9c7985 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ebony.c - * * Ebony board specific routines * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h index b91ad4272df..27b2e77c7c8 100644 --- a/arch/ppc/platforms/4xx/ebony.h +++ b/arch/ppc/platforms/4xx/ebony.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ebony.h - * * Ebony board definitions * * Matt Porter <mporter@mvista.com> diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c index 26a07cdb30e..6efa91ff9c0 100644 --- a/arch/ppc/platforms/4xx/ep405.c +++ b/arch/ppc/platforms/4xx/ep405.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ep405.c - * * Embedded Planet 405GP board * http://www.embeddedplanet.com * diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h index ea3eb21338f..9814fc43172 100644 --- a/arch/ppc/platforms/4xx/ep405.h +++ b/arch/ppc/platforms/4xx/ep405.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ep405.h - * * Embedded Planet 405GP board * http://www.embeddedplanet.com * diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c index 093b28d27a4..55af769a6e7 100644 --- a/arch/ppc/platforms/4xx/ibm405ep.c +++ b/arch/ppc/platforms/4xx/ibm405ep.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ibm405ep.c - * * Support for IBM PPC 405EP processors. * * Author: SAW (IBM), derived from ibmnp405l.c. diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h index e051e3fe8c6..fe46640de15 100644 --- a/arch/ppc/platforms/4xx/ibm405ep.h +++ b/arch/ppc/platforms/4xx/ibm405ep.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405ep.h - * * IBM PPC 405EP processor defines. * * Author: SAW (IBM), derived from ibm405gp.h. diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h index b2b642e81af..eaf0ef57028 100644 --- a/arch/ppc/platforms/4xx/ibm405gp.h +++ b/arch/ppc/platforms/4xx/ibm405gp.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405gp.h - * * Author: Armin Kuster akuster@mvista.com * * 2001 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c index cd0d00d8e8e..49da61f6854 100644 --- a/arch/ppc/platforms/4xx/ibm405gpr.c +++ b/arch/ppc/platforms/4xx/ibm405gpr.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405gpr.c - * * Author: Armin Kuster <akuster@mvista.com> * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h index 45412fb4368..e90c5dde01d 100644 --- a/arch/ppc/platforms/4xx/ibm405gpr.h +++ b/arch/ppc/platforms/4xx/ibm405gpr.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm405gpr.h - * * Author: Armin Kuster <akuster@mvista.com> * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c index 65ac0b9c2d0..1fed6638c81 100644 --- a/arch/ppc/platforms/4xx/ibm440ep.c +++ b/arch/ppc/platforms/4xx/ibm440ep.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440ep.c - * * PPC440EP I/O descriptions * * Wade Farnsworth <wfarnsworth@mvista.com> diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h index 97c80b8e3e1..61717e8a799 100644 --- a/arch/ppc/platforms/4xx/ibm440ep.h +++ b/arch/ppc/platforms/4xx/ibm440ep.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440ep.h - * * PPC440EP definitions * * Wade Farnsworth <wfarnsworth@mvista.com> diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c index d926245e8b3..b67a72e5c6f 100644 --- a/arch/ppc/platforms/4xx/ibm440gp.c +++ b/arch/ppc/platforms/4xx/ibm440gp.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440gp.c - * * PPC440GP I/O descriptions * * Matt Porter <mporter@mvista.com> diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h index ae1efc03b29..7b2763b6024 100644 --- a/arch/ppc/platforms/4xx/ibm440gp.h +++ b/arch/ppc/platforms/4xx/ibm440gp.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440gp.h - * * PPC440GP definitions * * Roland Dreier <roland@digitalvampire.org> diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c index d24c09ee7b1..685abffcb6c 100644 --- a/arch/ppc/platforms/4xx/ibm440gx.c +++ b/arch/ppc/platforms/4xx/ibm440gx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440gx.c - * * PPC440GX I/O descriptions * * Matt Porter <mporter@mvista.com> diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h index 0b59d8dcd03..070a34efe1c 100644 --- a/arch/ppc/platforms/4xx/ibm440gx.h +++ b/arch/ppc/platforms/4xx/ibm440gx.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ibm440gx.h - * * PPC440GX definitions * * Matt Porter <mporter@mvista.com> diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c index 71a0117d359..de8f7ac5623 100644 --- a/arch/ppc/platforms/4xx/ibm440sp.c +++ b/arch/ppc/platforms/4xx/ibm440sp.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440sp.c - * * PPC440SP I/O descriptions * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h index c71e46a18b9..77e8bb22c52 100644 --- a/arch/ppc/platforms/4xx/ibm440sp.h +++ b/arch/ppc/platforms/4xx/ibm440sp.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440sp.h - * * PPC440SP definitions * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c index a477a78f490..f1dcb0ac15b 100644 --- a/arch/ppc/platforms/4xx/ibmnp405h.c +++ b/arch/ppc/platforms/4xx/ibmnp405h.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmnp405h.c - * * Author: Armin Kuster <akuster@mvista.com> * * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h index e2c2b06128c..2c683f6aaa6 100644 --- a/arch/ppc/platforms/4xx/ibmnp405h.h +++ b/arch/ppc/platforms/4xx/ibmnp405h.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmnp405h.h - * * Author: Armin Kuster <akuster@mvista.com> * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c index 7e33bb63544..799a2eccccc 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.c +++ b/arch/ppc/platforms/4xx/ibmstb4.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstb4.c - * * Author: Armin Kuster <akuster@mvista.com> * * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h index 9f21d4c88a3..9de42659735 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.h +++ b/arch/ppc/platforms/4xx/ibmstb4.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstb4.h - * * Author: Armin Kuster <akuster@mvista.com> * * 2001 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c index b895b9cca57..090ddcbecc5 100644 --- a/arch/ppc/platforms/4xx/ibmstbx25.c +++ b/arch/ppc/platforms/4xx/ibmstbx25.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstbx25.c - * * Author: Armin Kuster <akuster@mvista.com> * * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h index 9a2efc366e9..6884a49d348 100644 --- a/arch/ppc/platforms/4xx/ibmstbx25.h +++ b/arch/ppc/platforms/4xx/ibmstbx25.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibmstbx25.h - * * Author: Armin Kuster <akuster@mvista.com> * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c index 21d29132aeb..5c37de28e13 100644 --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/luan.c - * * Luan board specific routines * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h index bbe7d0766db..e0db6a810fe 100644 --- a/arch/ppc/platforms/4xx/luan.h +++ b/arch/ppc/platforms/4xx/luan.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/luan.h - * * Luan board definitions * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c index 4f355b6acab..f841972f1fa 100644 --- a/arch/ppc/platforms/4xx/ocotea.c +++ b/arch/ppc/platforms/4xx/ocotea.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ocotea.c - * * Ocotea board specific routines * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h index 33251153ac5..7c799a9ff82 100644 --- a/arch/ppc/platforms/4xx/ocotea.h +++ b/arch/ppc/platforms/4xx/ocotea.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ocotea.h - * * Ocotea board definitions * * Matt Porter <mporter@kernel.crashing.org> diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c index 6139a0b3393..1be5d1c8e26 100644 --- a/arch/ppc/platforms/4xx/ppc440spe.c +++ b/arch/ppc/platforms/4xx/ppc440spe.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ppc440spe.c - * * PPC440SPe I/O descriptions * * Roland Dreier <rolandd@cisco.com> diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h index 2216846973b..d3a620ddcde 100644 --- a/arch/ppc/platforms/4xx/ppc440spe.h +++ b/arch/ppc/platforms/4xx/ppc440spe.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/ibm440spe.h - * * PPC440SPe definitions * * Roland Dreier <rolandd@cisco.com> diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c index 611ac861804..53da2b4f7c2 100644 --- a/arch/ppc/platforms/4xx/redwood5.c +++ b/arch/ppc/platforms/4xx/redwood5.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood5.c - * * Support for the IBM redwood5 eval board file * * Author: Armin Kuster <akuster@mvista.com> diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h index 264e34fb3fb..49edd481897 100644 --- a/arch/ppc/platforms/4xx/redwood5.h +++ b/arch/ppc/platforms/4xx/redwood5.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood5.h - * * Macros, definitions, and data structures specific to the IBM PowerPC * STB03xxx "Redwood" evaluation board. * diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c index b1311669128..41b27d106fa 100644 --- a/arch/ppc/platforms/4xx/redwood6.c +++ b/arch/ppc/platforms/4xx/redwood6.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood6.c - * * Author: Armin Kuster <akuster@mvista.com> * * 2002 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h index 1814b9f5fc3..1edcbe5c51c 100644 --- a/arch/ppc/platforms/4xx/redwood6.h +++ b/arch/ppc/platforms/4xx/redwood6.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/redwood6.h - * * Macros, definitions, and data structures specific to the IBM PowerPC * STBx25xx "Redwood6" evaluation board. * diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c index 281b4a2ffb9..bab31eb3068 100644 --- a/arch/ppc/platforms/4xx/sycamore.c +++ b/arch/ppc/platforms/4xx/sycamore.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/sycamore.c - * * Architecture- / platform-specific boot-time initialization code for * IBM PowerPC 4xx based boards. * diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h index 1cd6c824fd6..dae01620227 100644 --- a/arch/ppc/platforms/4xx/sycamore.h +++ b/arch/ppc/platforms/4xx/sycamore.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/sycamore.h - * * Sycamore board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c b/arch/ppc/platforms/4xx/virtex-ii_pro.c deleted file mode 100644 index 097cc9d5aca..00000000000 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/ppc/platforms/4xx/virtex-ii_pro.c - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <asm/ocp.h> -#include "virtex-ii_pro.h" - -/* Have OCP take care of the serial ports. */ -struct ocp_def core_ocp[] = { -#ifdef XPAR_UARTNS550_0_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = XPAR_UARTNS550_0_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_1_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = XPAR_UARTNS550_1_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_2_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = XPAR_UARTNS550_2_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_3_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 3, - .paddr = XPAR_UARTNS550_3_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_4_BASEADDR -#error Edit this file to add more devices. -#endif /* 4 */ -#endif /* 3 */ -#endif /* 2 */ -#endif /* 1 */ -#endif /* 0 */ - { .vendor = OCP_VENDOR_INVALID - } -}; diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h deleted file mode 100644 index 9014c488733..00000000000 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/ppc/platforms/4xx/virtex-ii_pro.h - * - * Include file that defines the Xilinx Virtex-II Pro processor - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_VIRTEXIIPRO_H__ -#define __ASM_VIRTEXIIPRO_H__ - -#include <linux/config.h> -#include <asm/xparameters.h> - -/* serial defines */ - -#define RS_TABLE_SIZE 4 /* change this and add more devices below - if you have more then 4 16x50 UARTs */ - -#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16) - -/* The serial ports in the Virtex-II Pro have each I/O byte in the - * LSByte of a word. This means that iomem_reg_shift needs to be 2 to - * change the byte offsets into word offsets. In addition the base - * addresses need to have 3 added to them to get to the LSByte. - */ -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ - ASYNC_BOOT_AUTOCONF, \ - .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM}, - -#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define ML300_UART0 STD_UART_OP(0) -#else -#define ML300_UART0 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define ML300_UART1 STD_UART_OP(1) -#else -#define ML300_UART1 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define ML300_UART2 STD_UART_OP(2) -#else -#define ML300_UART2 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define ML300_UART3 STD_UART_OP(3) -#else -#define ML300_UART3 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID) -#error Edit this file to add more devices. -#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define NR_SER_PORTS 4 -#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define NR_SER_PORTS 3 -#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define NR_SER_PORTS 2 -#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define NR_SER_PORTS 1 -#else -#define NR_SER_PORTS 0 -#endif - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_PORT_DFNS \ - ML300_UART0 \ - ML300_UART1 \ - ML300_UART2 \ - ML300_UART3 -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_PORT_DFNS \ - ML300_UART1 \ - ML300_UART0 \ - ML300_UART2 \ - ML300_UART3 -#endif - -#define DCRN_CPMFR_BASE 0 - -#include <asm/ibm405.h> - -#endif /* __ASM_VIRTEXIIPRO_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/virtex.c b/arch/ppc/platforms/4xx/virtex.c new file mode 100644 index 00000000000..133a8314719 --- /dev/null +++ b/arch/ppc/platforms/4xx/virtex.c @@ -0,0 +1,56 @@ +/* + * Virtex-II Pro & Virtex-4 FX common infrastructure + * + * Maintainer: Grant Likely <grant.likely@secretlab.ca> + * + * Copyright 2005 Secret Lab Technologies Ltd. + * Copyright 2005 General Dynamics Canada Ltd. + * Copyright 2005 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/serial_8250.h> +#include <asm/ppc_sys.h> +#include <platforms/4xx/virtex.h> +#include <platforms/4xx/xparameters/xparameters.h> + +#define XPAR_UART(num) { \ + .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \ + .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ + .iotype = UPIO_MEM, \ + .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \ + .flags = UPF_BOOT_AUTOCONF, \ + .regshift = 2, \ + } + +struct plat_serial8250_port serial_platform_data[] = { +#ifdef XPAR_UARTNS550_0_BASEADDR + XPAR_UART(0), +#endif +#ifdef XPAR_UARTNS550_1_BASEADDR + XPAR_UART(1), +#endif +#ifdef XPAR_UARTNS550_2_BASEADDR + XPAR_UART(2), +#endif +#ifdef XPAR_UARTNS550_3_BASEADDR + XPAR_UART(3), +#endif + { }, /* terminated by empty record */ +}; + +struct platform_device ppc_sys_platform_devices[] = { + [VIRTEX_UART] = { + .name = "serial8250", + .id = 0, + .dev.platform_data = serial_platform_data, + }, +}; + diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h new file mode 100644 index 00000000000..c14325dfd7b --- /dev/null +++ b/arch/ppc/platforms/4xx/virtex.h @@ -0,0 +1,35 @@ +/* + * arch/ppc/platforms/4xx/virtex.h + * + * Include file that defines the Xilinx Virtex-II Pro processor + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_VIRTEX_H__ +#define __ASM_VIRTEX_H__ + +/* serial defines */ + +#include <asm/ibm405.h> + +/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */ +#if !defined(BASE_BAUD) + #define BASE_BAUD (0) /* dummy value; not used */ +#endif + +/* Device type enumeration for platform bus definitions */ +#ifndef __ASSEMBLY__ +enum ppc_sys_devices { + VIRTEX_UART, NUM_PPC_SYS_DEVS, +}; +#endif + +#endif /* __ASM_VIRTEX_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c index 74cb33182d9..6bd77902b9a 100644 --- a/arch/ppc/platforms/4xx/walnut.c +++ b/arch/ppc/platforms/4xx/walnut.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/walnut.c - * * Architecture- / platform-specific boot-time initialization code for * IBM PowerPC 4xx based boards. Adapted from original * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h index dcf2691698c..f13a577f0a4 100644 --- a/arch/ppc/platforms/4xx/walnut.h +++ b/arch/ppc/platforms/4xx/walnut.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/walnut.h - * * Walnut board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c index e90d97f64f7..d97a7f269f9 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.c +++ b/arch/ppc/platforms/4xx/xilinx_ml300.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/xilinx_ml300.c - * * Xilinx ML300 evaluation board initialization * * Author: MontaVista Software, Inc. @@ -17,12 +15,14 @@ #include <linux/tty.h> #include <linux/serial.h> #include <linux/serial_core.h> +#include <linux/serial_8250.h> #include <linux/serialP.h> #include <asm/io.h> #include <asm/machdep.h> -#include <asm/ocp.h> +#include <asm/ppc_sys.h> -#include <platforms/4xx/virtex-ii_pro.h> /* for NR_SER_PORTS */ +#include <syslib/gen550.h> +#include <platforms/4xx/xparameters/xparameters.h> /* * As an overview of how the following functions (platform_init, @@ -54,6 +54,22 @@ * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c */ +/* Board specifications structures */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + /* Only one entry, always assume the same design */ + .ppc_sys_name = "Xilinx ML300 Reference Design", + .mask = 0x00000000, + .value = 0x00000000, + .num_devices = 1, + .device_list = (enum ppc_sys_devices[]) + { + VIRTEX_UART, + }, + }, +}; + #if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) static volatile unsigned *powerdown_base = @@ -80,28 +96,39 @@ ml300_map_io(void) #endif } +/* Early serial support functions */ static void __init +ml300_early_serial_init(int num, struct plat_serial8250_port *pdata) +{ +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + struct uart_port serial_req; + + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.mapbase = pdata->mapbase; + serial_req.membase = pdata->membase; + serial_req.irq = pdata->irq; + serial_req.uartclk = pdata->uartclk; + serial_req.regshift = pdata->regshift; + serial_req.iotype = pdata->iotype; + serial_req.flags = pdata->flags; + gen550_init(num, &serial_req); +#endif +} + +void __init ml300_early_serial_map(void) { #ifdef CONFIG_SERIAL_8250 - struct serial_state old_ports[] = { SERIAL_PORT_DFNS }; - struct uart_port port; - int i; - - /* Setup ioremapped serial port access */ - for (i = 0; i < ARRAY_SIZE(old_ports); i++ ) { - memset(&port, 0, sizeof(port)); - port.membase = ioremap((phys_addr_t)(old_ports[i].iomem_base), 16); - port.irq = old_ports[i].irq; - port.uartclk = old_ports[i].baud_base * 16; - port.regshift = old_ports[i].iomem_reg_shift; - port.iotype = UPIO_MEM; - port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; - port.line = i; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port %d failed\n", i); - } + struct plat_serial8250_port *pdata; + int i = 0; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); + while(pdata && pdata->flags) + { + pdata->membase = ioremap(pdata->mapbase, 0x100); + ml300_early_serial_init(i, pdata); + pdata++; + i++; } #endif /* CONFIG_SERIAL_8250 */ } @@ -109,9 +136,8 @@ ml300_early_serial_map(void) void __init ml300_setup_arch(void) { - ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ - ml300_early_serial_map(); + ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ /* Identify the system */ printk(KERN_INFO "Xilinx Virtex-II Pro port\n"); @@ -131,6 +157,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, { ppc4xx_init(r3, r4, r5, r6, r7); + identify_ppc_sys_by_id(mfspr(SPRN_PVR)); + ppc_md.setup_arch = ml300_setup_arch; ppc_md.setup_io_mappings = ml300_map_io; ppc_md.init_IRQ = ml300_init_irq; diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h index f8c58841233..3d57332ba82 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.h +++ b/arch/ppc/platforms/4xx/xilinx_ml300.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/xilinx_ml300.h - * * Include file that defines the Xilinx ML300 evaluation board * * Author: MontaVista Software, Inc. @@ -16,7 +14,7 @@ #define __ASM_XILINX_ML300_H__ /* ML300 has a Xilinx Virtex-II Pro processor */ -#include <platforms/4xx/virtex-ii_pro.h> +#include <platforms/4xx/virtex.h> #ifndef __ASSEMBLY__ @@ -41,7 +39,7 @@ typedef struct board_info { #define PPC4xx_ONB_IO_VADDR 0u #define PPC4xx_ONB_IO_SIZE 0u -#define PPC4xx_MACHINE_NAME "Xilinx ML300" +#define PPC4xx_MACHINE_NAME "Xilinx ML300 Reference System" #endif /* __ASM_XILINX_ML300_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c new file mode 100644 index 00000000000..4c0c7e4c111 --- /dev/null +++ b/arch/ppc/platforms/4xx/xilinx_ml403.c @@ -0,0 +1,177 @@ +/* + * arch/ppc/platforms/4xx/xilinx_ml403.c + * + * Xilinx ML403 evaluation board initialization + * + * Author: Grant Likely <grant.likely@secretlab.ca> + * + * 2005 (c) Secret Lab Technologies Ltd. + * 2002-2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/serial_8250.h> +#include <linux/serialP.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/ppc_sys.h> + +#include <syslib/gen550.h> +#include <platforms/4xx/xparameters/xparameters.h> + +/* + * As an overview of how the following functions (platform_init, + * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the + * kernel startup procedure, here's a call tree: + * + * start_here arch/ppc/kernel/head_4xx.S + * early_init arch/ppc/kernel/setup.c + * machine_init arch/ppc/kernel/setup.c + * platform_init this file + * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c + * parse_bootinfo + * find_bootinfo + * "setup some default ppc_md pointers" + * MMU_init arch/ppc/mm/init.c + * *ppc_md.setup_io_mappings == ml403_map_io this file + * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c + * start_kernel init/main.c + * setup_arch arch/ppc/kernel/setup.c + * #if defined(CONFIG_KGDB) + * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc + * #endif + * *ppc_md.setup_arch == ml403_setup_arch this file + * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c + * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c + * init_IRQ arch/ppc/kernel/irq.c + * *ppc_md.init_IRQ == ml403_init_IRQ this file + * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c + * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c + */ + +/* Board specifications structures */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + /* Only one entry, always assume the same design */ + .ppc_sys_name = "Xilinx ML403 Reference Design", + .mask = 0x00000000, + .value = 0x00000000, + .num_devices = 1, + .device_list = (enum ppc_sys_devices[]) + { + VIRTEX_UART, + }, + }, +}; + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + +static volatile unsigned *powerdown_base = + (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR; + +static void +xilinx_power_off(void) +{ + local_irq_disable(); + out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE); + while (1) ; +} +#endif + +void __init +ml403_map_io(void) +{ + ppc4xx_map_io(); + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + powerdown_base = ioremap((unsigned long) powerdown_base, + XPAR_POWER_0_POWERDOWN_HIGHADDR - + XPAR_POWER_0_POWERDOWN_BASEADDR + 1); +#endif +} + +/* Early serial support functions */ +static void __init +ml403_early_serial_init(int num, struct plat_serial8250_port *pdata) +{ +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + struct uart_port serial_req; + + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.mapbase = pdata->mapbase; + serial_req.membase = pdata->membase; + serial_req.irq = pdata->irq; + serial_req.uartclk = pdata->uartclk; + serial_req.regshift = pdata->regshift; + serial_req.iotype = pdata->iotype; + serial_req.flags = pdata->flags; + gen550_init(num, &serial_req); +#endif +} + +void __init +ml403_early_serial_map(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct plat_serial8250_port *pdata; + int i = 0; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); + while(pdata && pdata->flags) + { + pdata->membase = ioremap(pdata->mapbase, 0x100); + ml403_early_serial_init(i, pdata); + pdata++; + i++; + } +#endif /* CONFIG_SERIAL_8250 */ +} + +void __init +ml403_setup_arch(void) +{ + ml403_early_serial_map(); + ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ + + /* Identify the system */ + printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n"); +} + +/* Called after board_setup_irq from ppc4xx_init_IRQ(). */ +void __init +ml403_init_irq(void) +{ + ppc4xx_init_IRQ(); +} + +void __init +platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + ppc4xx_init(r3, r4, r5, r6, r7); + + identify_ppc_sys_by_id(mfspr(SPRN_PVR)); + + ppc_md.setup_arch = ml403_setup_arch; + ppc_md.setup_io_mappings = ml403_map_io; + ppc_md.init_IRQ = ml403_init_irq; + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + ppc_md.power_off = xilinx_power_off; +#endif + +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = ml403_early_serial_map; +#endif +} + diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.h b/arch/ppc/platforms/4xx/xilinx_ml403.h new file mode 100644 index 00000000000..47359695990 --- /dev/null +++ b/arch/ppc/platforms/4xx/xilinx_ml403.h @@ -0,0 +1,49 @@ +/* + * arch/ppc/platforms/4xx/xilinx_ml403.h + * + * Include file that defines the Xilinx ML403 reference design + * + * Author: Grant Likely <grant.likely@secretlab.ca> + * + * 2005 (c) Secret Lab Technologies Ltd. + * 2002-2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_XILINX_ML403_H__ +#define __ASM_XILINX_ML403_H__ + +/* ML403 has a Xilinx Virtex-4 FPGA with a PPC405 hard core */ +#include <platforms/4xx/virtex.h> + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +typedef struct board_info { + unsigned int bi_memsize; /* DRAM installed, in bytes */ + unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ + unsigned int bi_intfreq; /* Processor speed, in Hz */ + unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ +} bd_t; + +/* Some 4xx parts use a different timebase frequency from the internal clock. +*/ +#define bi_tbfreq bi_intfreq + +#endif /* !__ASSEMBLY__ */ + +/* We don't need anything mapped. Size of zero will accomplish that. */ +#define PPC4xx_ONB_IO_PADDR 0u +#define PPC4xx_ONB_IO_VADDR 0u +#define PPC4xx_ONB_IO_SIZE 0u + +#define PPC4xx_MACHINE_NAME "Xilinx ML403 Reference Design" + +#endif /* __ASM_XILINX_ML403_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h new file mode 100644 index 00000000000..4cf21f25635 --- /dev/null +++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h @@ -0,0 +1,37 @@ +/* + * include/asm-ppc/xparameters.h + * + * This file includes the correct xparameters.h for the CONFIG'ed board plus + * fixups to translate board specific XPAR values to a common set of names + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms + * of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#include <linux/config.h> + +#if defined(CONFIG_XILINX_ML300) + #include "xparameters_ml300.h" +#elif defined(CONFIG_XILINX_ML403) + #include "xparameters_ml403.h" +#else + /* Add other board xparameter includes here before the #else */ + #error No xparameters_*.h file included +#endif + +#ifndef SERIAL_PORT_DFNS + /* zImage serial port definitions */ + #define RS_TABLE_SIZE 1 + #define SERIAL_PORT_DFNS { \ + .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \ + .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \ + .flags = ASYNC_BOOT_AUTOCONF, \ + .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + }, +#endif diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h new file mode 100644 index 00000000000..5cacdcb3964 --- /dev/null +++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h @@ -0,0 +1,243 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 +* DO NOT EDIT. +* +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + +#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000 +#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF + +/******************************************************************/ + +#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000 +#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF +#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000 +#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF +#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF +#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000 +#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF +#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000 +#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF + +/******************************************************************/ + +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 + +/******************************************************************/ + +#define XPAR_XUARTNS550_NUM_INSTANCES 1 +#define XPAR_XUARTNS550_CLOCK_HZ 100000000 +#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 +#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF +#define XPAR_OPB_UART16550_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XGPIO_NUM_INSTANCES 3 +#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000 +#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF +#define XPAR_OPB_GPIO_0_DEVICE_ID 0 +#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_0_IS_DUAL 1 +#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000 +#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF +#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1 +#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1 +#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000 +#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF +#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2 +#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0 + +/******************************************************************/ + +#define XPAR_XPS2_NUM_INSTANCES 2 +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) + +/******************************************************************/ + +#define XPAR_XIIC_NUM_INSTANCES 1 +#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 +#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF +#define XPAR_OPB_IIC_0_DEVICE_ID 0 +#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 +#define XPAR_OPB_IIC_0_GPO_WIDTH 1 + +/******************************************************************/ + +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10 +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_XINTC_USE_DCR 0 +#define XPAR_XINTC_NUM_INSTANCES 1 +#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0 +#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF +#define XPAR_OPB_INTC_0_DEVICE_ID 0 +#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 + +/******************************************************************/ + +#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0 +#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001 +#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0 +#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002 +#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1 +#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004 +#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2 +#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008 +#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010 +#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020 +#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5 +#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040 +#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6 +#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080 +#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7 +#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100 +#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 +#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200 +#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9 + +/******************************************************************/ + +#define XPAR_XTFT_NUM_INSTANCES 1 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 +#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XSYSACE_MEM_WIDTH 16 +#define XPAR_XSYSACE_NUM_INSTANCES 1 +#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 +#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF +#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 +#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16 + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ + + +/******************************************************************/ + +/* Linux Redefines */ + +/******************************************************************/ + +#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) +#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ +#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR +#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR +#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR +#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR +#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR +#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR +#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR + +/******************************************************************/ + +#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR + +/******************************************************************/ + +#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR +#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR +#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT +#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST +#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST +#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0 +#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0 +#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0 +#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1 +#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1 +#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1 +#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0 +#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0 +#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0 +#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1 +#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1 +#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1 +#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR +#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR +#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 +#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 +#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 +#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 +#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 +#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 + +/******************************************************************/ + +#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR +#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR +#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR +#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR +#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR +#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ +#define XPAR_DDR_0_SIZE 0x4000000 + +/******************************************************************/ + +#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 +#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF +#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 + +/******************************************************************/ + +#define XPAR_PCI_0_CLOCK_FREQ_HZ 0 + +/******************************************************************/ + diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c index b065b8babcd..f287dcdbffc 100644 --- a/arch/ppc/platforms/4xx/yucca.c +++ b/arch/ppc/platforms/4xx/yucca.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/yucca.c - * * Yucca board specific routines * * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter) diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h index 01a4afea151..7ae23012237 100644 --- a/arch/ppc/platforms/4xx/yucca.h +++ b/arch/ppc/platforms/4xx/yucca.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/4xx/yucca.h - * * Yucca board definitions * * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter) diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c index 1a659bbc186..11626dd9090 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.c +++ b/arch/ppc/platforms/83xx/mpc834x_sys.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/83xx/mpc834x_sys.c - * * MPC834x SYS board specific routines * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h index 2e514d316fb..6727bbdc36e 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.h +++ b/arch/ppc/platforms/83xx/mpc834x_sys.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/83xx/mpc834x_sys.h - * * MPC834X SYS common board definitions * * Maintainer: Kumar Gala <galak@kernel.crashing.org> @@ -25,7 +23,7 @@ #define VIRT_IMMRBAR ((uint)0xfe000000) #define BCSR_PHYS_ADDR ((uint)0xf8000000) -#define BCSR_SIZE ((uint)(128 * 1024)) +#define BCSR_SIZE ((uint)(32 * 1024)) #define BCSR_MISC_REG2_OFF 0x07 #define BCSR_MISC_REG2_PORESET 0x01 diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c index 408d64f18e1..9b014df516b 100644 --- a/arch/ppc/platforms/85xx/mpc8540_ads.c +++ b/arch/ppc/platforms/85xx/mpc8540_ads.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc8540_ads.c - * * MPC8540ADS board specific routines * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.h b/arch/ppc/platforms/85xx/mpc8540_ads.h index e48ca3a9739..0b5e7ff856f 100644 --- a/arch/ppc/platforms/85xx/mpc8540_ads.h +++ b/arch/ppc/platforms/85xx/mpc8540_ads.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc8540_ads.h - * * MPC8540ADS board definitions * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc8555_cds.h b/arch/ppc/platforms/85xx/mpc8555_cds.h index 1a8e6c67355..9754dbd5d18 100644 --- a/arch/ppc/platforms/85xx/mpc8555_cds.h +++ b/arch/ppc/platforms/85xx/mpc8555_cds.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/mpc8555_cds.h - * * MPC8555CDS board definitions * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c index 442c7ff195d..0cb2e86470e 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.c +++ b/arch/ppc/platforms/85xx/mpc8560_ads.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc8560_ads.c - * * MPC8560ADS board specific routines * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.h b/arch/ppc/platforms/85xx/mpc8560_ads.h index 143ae7eefa7..c2247c21fc5 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.h +++ b/arch/ppc/platforms/85xx/mpc8560_ads.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/mpc8560_ads.h - * * MPC8540ADS board definitions * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c index 17ce48fe350..8fd9d763f58 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_ads_common.c - * * MPC85xx ADS board common routines * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h index 198a6a02cde..de8d41aafe1 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_ads_common.h - * * MPC85XX ADS common board definitions * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index 1801ab392e2..c9e0aeeca3d 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platform/85xx/mpc85xx_cds_common.c - * * MPC85xx CDS board specific routines * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h index 5b588cfd0e4..62df54f61ae 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/mpc85xx_cds_common.h - * * MPC85xx CDS board definitions * * Maintainer: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c index 8a72221f816..b73778ecf82 100644 --- a/arch/ppc/platforms/85xx/sbc8560.c +++ b/arch/ppc/platforms/85xx/sbc8560.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/sbc8560.c - * * Wind River SBC8560 board specific routines * * Maintainer: Kumar Gala diff --git a/arch/ppc/platforms/85xx/sbc8560.h b/arch/ppc/platforms/85xx/sbc8560.h index 5e1b00c77da..44ffaa2d2c8 100644 --- a/arch/ppc/platforms/85xx/sbc8560.h +++ b/arch/ppc/platforms/85xx/sbc8560.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/sbc8560.h - * * Wind River SBC8560 board definitions * * Copyright 2003 Motorola Inc. diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c index c02f110219f..d3ff280510f 100644 --- a/arch/ppc/platforms/85xx/sbc85xx.c +++ b/arch/ppc/platforms/85xx/sbc85xx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platform/85xx/sbc85xx.c - * * WindRiver PowerQUICC III SBC85xx board common routines * * Copyright 2002, 2003 Motorola Inc. diff --git a/arch/ppc/platforms/85xx/sbc85xx.h b/arch/ppc/platforms/85xx/sbc85xx.h index 7af93c691a6..5dd8b6a98c9 100644 --- a/arch/ppc/platforms/85xx/sbc85xx.h +++ b/arch/ppc/platforms/85xx/sbc85xx.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/sbc85xx.h - * * WindRiver PowerQUICC III SBC85xx common board definitions * * Copyright 2003 Motorola Inc. diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c index 061bb7cf2d9..8d7baa9a397 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.c +++ b/arch/ppc/platforms/85xx/stx_gp3.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/stx_gp3.c - * * STx GP3 board specific routines * * Dan Malek <dan@embeddededge.com> diff --git a/arch/ppc/platforms/85xx/stx_gp3.h b/arch/ppc/platforms/85xx/stx_gp3.h index 2f25b519515..3f71f8f5937 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.h +++ b/arch/ppc/platforms/85xx/stx_gp3.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/stx8560_gp3.h - * * STx GP3 board definitions * * Dan Malek (dan@embeddededge.com) diff --git a/arch/ppc/platforms/85xx/tqm85xx.c b/arch/ppc/platforms/85xx/tqm85xx.c index a5e38ba6273..00af132262b 100644 --- a/arch/ppc/platforms/85xx/tqm85xx.c +++ b/arch/ppc/platforms/85xx/tqm85xx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/tqm85xx.c - * * TQM85xx (40/41/55/60) board specific routines * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/85xx/tqm85xx.h b/arch/ppc/platforms/85xx/tqm85xx.h index 3775eb363fd..612d80504f9 100644 --- a/arch/ppc/platforms/85xx/tqm85xx.h +++ b/arch/ppc/platforms/85xx/tqm85xx.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/85xx/tqm85xx.h - * * TQM85xx (40/41/55/60) board definitions * * Copyright (c) 2005 DENX Software Engineering diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile index 51430e294b3..90c62229442 100644 --- a/arch/ppc/platforms/Makefile +++ b/arch/ppc/platforms/Makefile @@ -2,18 +2,10 @@ # Makefile for the linux kernel. # -# Extra CFLAGS so we don't have to do relative includes -CFLAGS_chrp_setup.o += -Iarch/$(ARCH)/mm - obj-$(CONFIG_APUS) += apus_setup.o ifeq ($(CONFIG_APUS),y) obj-$(CONFIG_PCI) += apus_pci.o endif -obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \ - chrp_pegasos_eth.o -ifeq ($(CONFIG_PPC_CHRP),y) -obj-$(CONFIG_NVRAM) += chrp_nvram.o -endif obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o obj-$(CONFIG_PREP_RESIDUAL) += residual.o obj-$(CONFIG_PQ2ADS) += pq2ads.o @@ -37,7 +29,6 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o obj-$(CONFIG_SPRUCE) += spruce.o obj-$(CONFIG_LITE5200) += lite5200.o obj-$(CONFIG_EV64360) += ev64360.o - -ifeq ($(CONFIG_SMP),y) -obj-$(CONFIG_PPC_CHRP) += chrp_smp.o -endif +obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o +obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o +obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o diff --git a/arch/ppc/platforms/apus_setup.c b/arch/ppc/platforms/apus_setup.c index c42c50073da..fe0cdc04d43 100644 --- a/arch/ppc/platforms/apus_setup.c +++ b/arch/ppc/platforms/apus_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/apus_setup.c - * * Copyright (C) 1998, 1999 Jesper Skov * * Basically what is needed to replace functionality found in diff --git a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c index aefcc0e7be5..f324f757cae 100644 --- a/arch/ppc/platforms/chestnut.c +++ b/arch/ppc/platforms/chestnut.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chestnut.c - * * Board setup routines for IBM Chestnut * * Author: <source@mvista.com> diff --git a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h index 0400b2be40a..e00fd9f8bbd 100644 --- a/arch/ppc/platforms/chestnut.h +++ b/arch/ppc/platforms/chestnut.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/chestnut.h - * * Definitions for IBM 750FXGX Eval (Chestnut) * * Author: <source@mvista.com> diff --git a/arch/ppc/platforms/chrp_nvram.c b/arch/ppc/platforms/chrp_nvram.c deleted file mode 100644 index 465ba9b090e..00000000000 --- a/arch/ppc/platforms/chrp_nvram.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * c 2001 PPC 64 Team, IBM Corp - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * /dev/nvram driver for PPC - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <asm/uaccess.h> -#include <asm/prom.h> -#include <asm/machdep.h> - -static unsigned int nvram_size; -static unsigned char nvram_buf[4]; -static DEFINE_SPINLOCK(nvram_lock); - -static unsigned char chrp_nvram_read(int addr) -{ - unsigned long done, flags; - unsigned char ret; - - if (addr >= nvram_size) { - printk(KERN_DEBUG "%s: read addr %d > nvram_size %u\n", - current->comm, addr, nvram_size); - return 0xff; - } - spin_lock_irqsave(&nvram_lock, flags); - if ((call_rtas("nvram-fetch", 3, 2, &done, addr, __pa(nvram_buf), 1) != 0) || 1 != done) - ret = 0xff; - else - ret = nvram_buf[0]; - spin_unlock_irqrestore(&nvram_lock, flags); - - return ret; -} - -static void chrp_nvram_write(int addr, unsigned char val) -{ - unsigned long done, flags; - - if (addr >= nvram_size) { - printk(KERN_DEBUG "%s: write addr %d > nvram_size %u\n", - current->comm, addr, nvram_size); - return; - } - spin_lock_irqsave(&nvram_lock, flags); - nvram_buf[0] = val; - if ((call_rtas("nvram-store", 3, 2, &done, addr, __pa(nvram_buf), 1) != 0) || 1 != done) - printk(KERN_DEBUG "rtas IO error storing 0x%02x at %d", val, addr); - spin_unlock_irqrestore(&nvram_lock, flags); -} - -void __init chrp_nvram_init(void) -{ - struct device_node *nvram; - unsigned int *nbytes_p, proplen; - - nvram = of_find_node_by_type(NULL, "nvram"); - if (nvram == NULL) - return; - - nbytes_p = (unsigned int *)get_property(nvram, "#bytes", &proplen); - if (nbytes_p == NULL || proplen != sizeof(unsigned int)) - return; - - nvram_size = *nbytes_p; - - printk(KERN_INFO "CHRP nvram contains %u bytes\n", nvram_size); - of_node_put(nvram); - - ppc_md.nvram_read_val = chrp_nvram_read; - ppc_md.nvram_write_val = chrp_nvram_write; - - return; -} diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c deleted file mode 100644 index c7fe6182bb7..00000000000 --- a/arch/ppc/platforms/chrp_pci.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * CHRP pci routines. - */ - -#include <linux/config.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/string.h> -#include <linux/init.h> -#include <linux/ide.h> - -#include <asm/io.h> -#include <asm/pgtable.h> -#include <asm/irq.h> -#include <asm/hydra.h> -#include <asm/prom.h> -#include <asm/gg2.h> -#include <asm/machdep.h> -#include <asm/sections.h> -#include <asm/pci-bridge.h> -#include <asm/open_pic.h> - -/* LongTrail */ -void __iomem *gg2_pci_config_base; - -/* - * The VLSI Golden Gate II has only 512K of PCI configuration space, so we - * limit the bus number to 3 bits - */ - -int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, - int len, u32 *val) -{ - volatile void __iomem *cfg_data; - struct pci_controller *hose = bus->sysdata; - - if (bus->number > 7) - return PCIBIOS_DEVICE_NOT_FOUND; - /* - * Note: the caller has already checked that off is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); - switch (len) { - case 1: - *val = in_8(cfg_data); - break; - case 2: - *val = in_le16(cfg_data); - break; - default: - *val = in_le32(cfg_data); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, - int len, u32 val) -{ - volatile void __iomem *cfg_data; - struct pci_controller *hose = bus->sysdata; - - if (bus->number > 7) - return PCIBIOS_DEVICE_NOT_FOUND; - /* - * Note: the caller has already checked that off is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); - switch (len) { - case 1: - out_8(cfg_data, val); - break; - case 2: - out_le16(cfg_data, val); - break; - default: - out_le32(cfg_data, val); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops gg2_pci_ops = -{ - gg2_read_config, - gg2_write_config -}; - -/* - * Access functions for PCI config space using RTAS calls. - */ -int -rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - struct pci_controller *hose = bus->sysdata; - unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) - | (((bus->number - hose->first_busno) & 0xff) << 16) - | (hose->index << 24); - unsigned long ret = ~0UL; - int rval; - - rval = call_rtas("read-pci-config", 2, 2, &ret, addr, len); - *val = ret; - return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; -} - -int -rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - struct pci_controller *hose = bus->sysdata; - unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) - | (((bus->number - hose->first_busno) & 0xff) << 16) - | (hose->index << 24); - int rval; - - rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val); - return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops rtas_pci_ops = -{ - rtas_read_config, - rtas_write_config -}; - -volatile struct Hydra __iomem *Hydra = NULL; - -int __init -hydra_init(void) -{ - struct device_node *np; - - np = find_devices("mac-io"); - if (np == NULL || np->n_addrs == 0) - return 0; - Hydra = ioremap(np->addrs[0].address, np->addrs[0].size); - printk("Hydra Mac I/O at %x\n", np->addrs[0].address); - printk("Hydra Feature_Control was %x", - in_le32(&Hydra->Feature_Control)); - out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | - HYDRA_FC_SCSI_CELL_EN | - HYDRA_FC_SCCA_ENABLE | - HYDRA_FC_SCCB_ENABLE | - HYDRA_FC_ARB_BYPASS | - HYDRA_FC_MPIC_ENABLE | - HYDRA_FC_SLOW_SCC_PCLK | - HYDRA_FC_MPIC_IS_MASTER)); - printk(", now %x\n", in_le32(&Hydra->Feature_Control)); - return 1; -} - -void __init -chrp_pcibios_fixup(void) -{ - struct pci_dev *dev = NULL; - struct device_node *np; - - /* PCI interrupts are controlled by the OpenPIC */ - for_each_pci_dev(dev) { - np = pci_device_to_OF_node(dev); - if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0)) - dev->irq = np->intrs[0].line; - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } -} - -#define PRG_CL_RESET_VALID 0x00010000 - -static void __init -setup_python(struct pci_controller *hose, struct device_node *dev) -{ - u32 __iomem *reg; - u32 val; - unsigned long addr = dev->addrs[0].address; - - setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010); - - /* Clear the magic go-slow bit */ - reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40); - val = in_be32(®[12]); - if (val & PRG_CL_RESET_VALID) { - out_be32(®[12], val & ~PRG_CL_RESET_VALID); - in_be32(®[12]); - } - iounmap(reg); -} - -/* Marvell Discovery II based Pegasos 2 */ -static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) -{ - struct device_node *root = find_path_device("/"); - struct device_node *rtas; - - rtas = of_find_node_by_name (root, "rtas"); - if (rtas) { - hose->ops = &rtas_pci_ops; - } else { - printk ("RTAS supporting Pegasos OF not found, please upgrade" - " your firmware\n"); - } - pci_assign_all_buses = 1; -} - -void __init -chrp_find_bridges(void) -{ - struct device_node *dev; - int *bus_range; - int len, index = -1; - struct pci_controller *hose; - unsigned int *dma; - char *model, *machine; - int is_longtrail = 0, is_mot = 0, is_pegasos = 0; - struct device_node *root = find_path_device("/"); - - /* - * The PCI host bridge nodes on some machines don't have - * properties to adequately identify them, so we have to - * look at what sort of machine this is as well. - */ - machine = get_property(root, "model", NULL); - if (machine != NULL) { - is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; - is_mot = strncmp(machine, "MOT", 3) == 0; - if (strncmp(machine, "Pegasos2", 8) == 0) - is_pegasos = 2; - else if (strncmp(machine, "Pegasos", 7) == 0) - is_pegasos = 1; - } - for (dev = root->child; dev != NULL; dev = dev->sibling) { - if (dev->type == NULL || strcmp(dev->type, "pci") != 0) - continue; - ++index; - /* The GG2 bridge on the LongTrail doesn't have an address */ - if (dev->n_addrs < 1 && !is_longtrail) { - printk(KERN_WARNING "Can't use %s: no address\n", - dev->full_name); - continue; - } - bus_range = (int *) get_property(dev, "bus-range", &len); - if (bus_range == NULL || len < 2 * sizeof(int)) { - printk(KERN_WARNING "Can't get bus-range for %s\n", - dev->full_name); - continue; - } - if (bus_range[1] == bus_range[0]) - printk(KERN_INFO "PCI bus %d", bus_range[0]); - else - printk(KERN_INFO "PCI buses %d..%d", - bus_range[0], bus_range[1]); - printk(" controlled by %s", dev->type); - if (dev->n_addrs > 0) - printk(" at %x", dev->addrs[0].address); - printk("\n"); - - hose = pcibios_alloc_controller(); - if (!hose) { - printk("Can't allocate PCI controller structure for %s\n", - dev->full_name); - continue; - } - hose->arch_data = dev; - hose->first_busno = bus_range[0]; - hose->last_busno = bus_range[1]; - - model = get_property(dev, "model", NULL); - if (model == NULL) - model = "<none>"; - if (device_is_compatible(dev, "IBM,python")) { - setup_python(hose, dev); - } else if (is_mot - || strncmp(model, "Motorola, Grackle", 17) == 0) { - setup_indirect_pci(hose, 0xfec00000, 0xfee00000); - } else if (is_longtrail) { - void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); - hose->ops = &gg2_pci_ops; - hose->cfg_data = p; - gg2_pci_config_base = p; - } else if (is_pegasos == 1) { - setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); - } else if (is_pegasos == 2) { - setup_peg2(hose, dev); - } else { - printk("No methods for %s (model %s), using RTAS\n", - dev->full_name, model); - hose->ops = &rtas_pci_ops; - } - - pci_process_bridge_OF_ranges(hose, dev, index == 0); - - /* check the first bridge for a property that we can - use to set pci_dram_offset */ - dma = (unsigned int *) - get_property(dev, "ibm,dma-ranges", &len); - if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { - pci_dram_offset = dma[2] - dma[3]; - printk("pci_dram_offset = %lx\n", pci_dram_offset); - } - } - - /* Do not fixup interrupts from OF tree on pegasos */ - if (is_pegasos == 0) - ppc_md.pcibios_fixup = chrp_pcibios_fixup; -} diff --git a/arch/ppc/platforms/chrp_pegasos_eth.c b/arch/ppc/platforms/chrp_pegasos_eth.c deleted file mode 100644 index 108a6e26518..00000000000 --- a/arch/ppc/platforms/chrp_pegasos_eth.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * arch/ppc/platforms/chrp_pegasos_eth.c - * - * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de> - * Thanks to : - * Dale Farnsworth <dale@farnsworth.org> - * Mark A. Greer <mgreer@mvista.com> - * Nicolas DET <nd@bplan-gmbh.de> - * Benjamin Herrenschmidt <benh@kernel.crashing.org> - * And anyone else who helped me on this. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> -#include <linux/mv643xx.h> -#include <linux/pci.h> - -#define PEGASOS2_MARVELL_REGBASE (0xf1000000) -#define PEGASOS2_MARVELL_REGSIZE (0x00004000) -#define PEGASOS2_SRAM_BASE (0xf2000000) -#define PEGASOS2_SRAM_SIZE (256*1024) - -#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE) -#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) ) - - -#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) -#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4) - -#undef BE_VERBOSE - -static struct resource mv643xx_eth_shared_resources[] = { - [0] = { - .name = "ethernet shared base", - .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS, - .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + - MV643XX_ETH_SHARED_REGS_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv643xx_eth_shared_device = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources), - .resource = mv643xx_eth_shared_resources, -}; - -static struct resource mv643xx_eth0_resources[] = { - [0] = { - .name = "eth0 irq", - .start = 9, - .end = 9, - .flags = IORESOURCE_IRQ, - }, -}; - - -static struct mv643xx_eth_platform_data eth0_pd = { - .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0, - .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, - .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, - - .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE, - .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, - .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, -}; - -static struct platform_device eth0_device = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv643xx_eth0_resources), - .resource = mv643xx_eth0_resources, - .dev = { - .platform_data = ð0_pd, - }, -}; - -static struct resource mv643xx_eth1_resources[] = { - [0] = { - .name = "eth1 irq", - .start = 9, - .end = 9, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv643xx_eth_platform_data eth1_pd = { - .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1, - .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, - .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, - - .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE, - .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, - .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, -}; - -static struct platform_device eth1_device = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(mv643xx_eth1_resources), - .resource = mv643xx_eth1_resources, - .dev = { - .platform_data = ð1_pd, - }, -}; - -static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { - &mv643xx_eth_shared_device, - ð0_device, - ð1_device, -}; - -/***********/ -/***********/ -#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } -#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset) - -static void __iomem *mv643xx_reg_base; - -static int Enable_SRAM(void) -{ - u32 ALong; - - if (mv643xx_reg_base == NULL) - mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, - PEGASOS2_MARVELL_REGSIZE); - - if (mv643xx_reg_base == NULL) - return -ENOMEM; - -#ifdef BE_VERBOSE - printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", - (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base); -#endif - - MV_WRITE(MV64340_SRAM_CONFIG, 0); - - MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16); - - MV_READ(MV64340_BASE_ADDR_ENABLE, ALong); - ALong &= ~(1 << 19); - MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong); - - ALong = 0x02; - ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; - MV_WRITE(MV643XX_ETH_BAR_4, ALong); - - MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000); - - MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); - ALong &= ~(1 << 4); - MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); - -#ifdef BE_VERBOSE - printk("Pegasos II/Marvell MV64361: register unmapped\n"); - printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE); -#endif - - iounmap(mv643xx_reg_base); - mv643xx_reg_base = NULL; - - return 1; -} - - -/***********/ -/***********/ -int mv643xx_eth_add_pds(void) -{ - int ret = 0; - static struct pci_device_id pci_marvell_mv64360[] = { - { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) }, - { } - }; - -#ifdef BE_VERBOSE - printk("Pegasos II/Marvell MV64361: init\n"); -#endif - - if (pci_dev_present(pci_marvell_mv64360)) { - ret = platform_add_devices(mv643xx_eth_pd_devs, - ARRAY_SIZE(mv643xx_eth_pd_devs)); - - if ( Enable_SRAM() < 0) - { - eth0_pd.tx_sram_addr = 0; - eth0_pd.tx_sram_size = 0; - eth0_pd.rx_sram_addr = 0; - eth0_pd.rx_sram_size = 0; - - eth1_pd.tx_sram_addr = 0; - eth1_pd.tx_sram_size = 0; - eth1_pd.rx_sram_addr = 0; - eth1_pd.rx_sram_size = 0; - -#ifdef BE_VERBOSE - printk("Pegasos II/Marvell MV64361: Can't enable the " - "SRAM\n"); -#endif - } - } - -#ifdef BE_VERBOSE - printk("Pegasos II/Marvell MV64361: init is over\n"); -#endif - - return ret; -} - -device_initcall(mv643xx_eth_add_pds); diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c deleted file mode 100644 index 48996b78737..00000000000 --- a/arch/ppc/platforms/chrp_setup.c +++ /dev/null @@ -1,671 +0,0 @@ -/* - * arch/ppc/platforms/setup.c - * - * Copyright (C) 1995 Linus Torvalds - * Adapted from 'alpha' version by Gary Thomas - * Modified by Cort Dougan (cort@cs.nmt.edu) - */ - -/* - * bootup setup stuff.. - */ - -#include <linux/config.h> -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/stddef.h> -#include <linux/unistd.h> -#include <linux/ptrace.h> -#include <linux/slab.h> -#include <linux/user.h> -#include <linux/a.out.h> -#include <linux/tty.h> -#include <linux/major.h> -#include <linux/interrupt.h> -#include <linux/reboot.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/version.h> -#include <linux/adb.h> -#include <linux/module.h> -#include <linux/delay.h> -#include <linux/ide.h> -#include <linux/console.h> -#include <linux/seq_file.h> -#include <linux/root_dev.h> -#include <linux/initrd.h> -#include <linux/module.h> - -#include <asm/io.h> -#include <asm/pgtable.h> -#include <asm/prom.h> -#include <asm/gg2.h> -#include <asm/pci-bridge.h> -#include <asm/dma.h> -#include <asm/machdep.h> -#include <asm/irq.h> -#include <asm/hydra.h> -#include <asm/sections.h> -#include <asm/time.h> -#include <asm/btext.h> -#include <asm/i8259.h> -#include <asm/open_pic.h> -#include <asm/xmon.h> -#include "mem_pieces.h" - -unsigned long chrp_get_rtc_time(void); -int chrp_set_rtc_time(unsigned long nowtime); -void chrp_calibrate_decr(void); -long chrp_time_init(void); - -void chrp_find_bridges(void); -void chrp_event_scan(void); -void rtas_display_progress(char *, unsigned short); -void rtas_indicator_progress(char *, unsigned short); -void btext_progress(char *, unsigned short); - -extern int of_show_percpuinfo(struct seq_file *, int); - -int _chrp_type; -EXPORT_SYMBOL(_chrp_type); - -/* - * XXX this should be in xmon.h, but putting it there means xmon.h - * has to include <linux/interrupt.h> (to get irqreturn_t), which - * causes all sorts of problems. -- paulus - */ -extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); - -extern dev_t boot_dev; - -extern PTE *Hash, *Hash_end; -extern unsigned long Hash_size, Hash_mask; -extern int probingmem; -extern unsigned long loops_per_jiffy; -static int max_width; - -#ifdef CONFIG_SMP -extern struct smp_ops_t chrp_smp_ops; -#endif - -static const char *gg2_memtypes[4] = { - "FPM", "SDRAM", "EDO", "BEDO" -}; -static const char *gg2_cachesizes[4] = { - "256 KB", "512 KB", "1 MB", "Reserved" -}; -static const char *gg2_cachetypes[4] = { - "Asynchronous", "Reserved", "Flow-Through Synchronous", - "Pipelined Synchronous" -}; -static const char *gg2_cachemodes[4] = { - "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" -}; - -int -chrp_show_cpuinfo(struct seq_file *m) -{ - int i, sdramen; - unsigned int t; - struct device_node *root; - const char *model = ""; - - root = find_path_device("/"); - if (root) - model = get_property(root, "model", NULL); - seq_printf(m, "machine\t\t: CHRP %s\n", model); - - /* longtrail (goldengate) stuff */ - if (!strncmp(model, "IBM,LongTrail", 13)) { - /* VLSI VAS96011/12 `Golden Gate 2' */ - /* Memory banks */ - sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) - >>31) & 1; - for (i = 0; i < (sdramen ? 4 : 6); i++) { - t = in_le32(gg2_pci_config_base+ - GG2_PCI_DRAM_BANK0+ - i*4); - if (!(t & 1)) - continue; - switch ((t>>8) & 0x1f) { - case 0x1f: - model = "4 MB"; - break; - case 0x1e: - model = "8 MB"; - break; - case 0x1c: - model = "16 MB"; - break; - case 0x18: - model = "32 MB"; - break; - case 0x10: - model = "64 MB"; - break; - case 0x00: - model = "128 MB"; - break; - default: - model = "Reserved"; - break; - } - seq_printf(m, "memory bank %d\t: %s %s\n", i, model, - gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); - } - /* L2 cache */ - t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); - seq_printf(m, "board l2\t: %s %s (%s)\n", - gg2_cachesizes[(t>>7) & 3], - gg2_cachetypes[(t>>2) & 3], - gg2_cachemodes[t & 3]); - } - return 0; -} - -/* - * Fixes for the National Semiconductor PC78308VUL SuperI/O - * - * Some versions of Open Firmware incorrectly initialize the IRQ settings - * for keyboard and mouse - */ -static inline void __init sio_write(u8 val, u8 index) -{ - outb(index, 0x15c); - outb(val, 0x15d); -} - -static inline u8 __init sio_read(u8 index) -{ - outb(index, 0x15c); - return inb(0x15d); -} - -static void __init sio_fixup_irq(const char *name, u8 device, u8 level, - u8 type) -{ - u8 level0, type0, active; - - /* select logical device */ - sio_write(device, 0x07); - active = sio_read(0x30); - level0 = sio_read(0x70); - type0 = sio_read(0x71); - if (level0 != level || type0 != type || !active) { - printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " - "remapping to level %d, type %d, active\n", - name, level0, type0, !active ? "in" : "", level, type); - sio_write(0x01, 0x30); - sio_write(level, 0x70); - sio_write(type, 0x71); - } -} - -static void __init sio_init(void) -{ - struct device_node *root; - - if ((root = find_path_device("/")) && - !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) { - /* logical device 0 (KBC/Keyboard) */ - sio_fixup_irq("keyboard", 0, 1, 2); - /* select logical device 1 (KBC/Mouse) */ - sio_fixup_irq("mouse", 1, 12, 2); - } -} - - -static void __init pegasos_set_l2cr(void) -{ - struct device_node *np; - - /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ - if (_chrp_type != _CHRP_Pegasos) - return; - - /* Enable L2 cache if needed */ - np = find_type_devices("cpu"); - if (np != NULL) { - unsigned int *l2cr = (unsigned int *) - get_property (np, "l2cr", NULL); - if (l2cr == NULL) { - printk ("Pegasos l2cr : no cpu l2cr property found\n"); - return; - } - if (!((*l2cr) & 0x80000000)) { - printk ("Pegasos l2cr : L2 cache was not active, " - "activating\n"); - _set_L2CR(0); - _set_L2CR((*l2cr) | 0x80000000); - } - } -} - -void __init chrp_setup_arch(void) -{ - struct device_node *device; - - /* init to some ~sane value until calibrate_delay() runs */ - loops_per_jiffy = 50000000/HZ; - -#ifdef CONFIG_BLK_DEV_INITRD - /* this is fine for chrp */ - initrd_below_start_ok = 1; - - if (initrd_start) - ROOT_DEV = Root_RAM0; - else -#endif - ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */ - - /* On pegasos, enable the L2 cache if not already done by OF */ - pegasos_set_l2cr(); - - /* Lookup PCI host bridges */ - chrp_find_bridges(); - -#ifndef CONFIG_PPC64BRIDGE - /* - * Temporary fixes for PCI devices. - * -- Geert - */ - hydra_init(); /* Mac I/O */ - -#endif /* CONFIG_PPC64BRIDGE */ - - /* - * Fix the Super I/O configuration - */ - sio_init(); - - /* Get the event scan rate for the rtas so we know how - * often it expects a heartbeat. -- Cort - */ - if ( rtas_data ) { - struct property *p; - device = find_devices("rtas"); - for ( p = device->properties; - p && strncmp(p->name, "rtas-event-scan-rate", 20); - p = p->next ) - /* nothing */ ; - if ( p && *(unsigned long *)p->value ) { - ppc_md.heartbeat = chrp_event_scan; - ppc_md.heartbeat_reset = (HZ/(*(unsigned long *)p->value)*30)-1; - ppc_md.heartbeat_count = 1; - printk("RTAS Event Scan Rate: %lu (%lu jiffies)\n", - *(unsigned long *)p->value, ppc_md.heartbeat_reset ); - } - } - - pci_create_OF_bus_map(); -} - -void -chrp_event_scan(void) -{ - unsigned char log[1024]; - unsigned long ret = 0; - /* XXX: we should loop until the hardware says no more error logs -- Cort */ - call_rtas( "event-scan", 4, 1, &ret, 0xffffffff, 0, - __pa(log), 1024 ); - ppc_md.heartbeat_count = ppc_md.heartbeat_reset; -} - -void -chrp_restart(char *cmd) -{ - printk("RTAS system-reboot returned %d\n", - call_rtas("system-reboot", 0, 1, NULL)); - for (;;); -} - -void -chrp_power_off(void) -{ - /* allow power on only with power button press */ - printk("RTAS power-off returned %d\n", - call_rtas("power-off", 2, 1, NULL,0xffffffff,0xffffffff)); - for (;;); -} - -void -chrp_halt(void) -{ - chrp_power_off(); -} - -/* - * Finds the open-pic node and sets OpenPIC_Addr based on its reg property. - * Then checks if it has an interrupt-ranges property. If it does then - * we have a distributed open-pic, so call openpic_set_sources to tell - * the openpic code where to find the interrupt source registers. - */ -static void __init chrp_find_openpic(void) -{ - struct device_node *np; - int len, i; - unsigned int *iranges; - void __iomem *isu; - - np = find_type_devices("open-pic"); - if (np == NULL || np->n_addrs == 0) - return; - printk(KERN_INFO "OpenPIC at %x (size %x)\n", - np->addrs[0].address, np->addrs[0].size); - OpenPIC_Addr = ioremap(np->addrs[0].address, 0x40000); - if (OpenPIC_Addr == NULL) { - printk(KERN_ERR "Failed to map OpenPIC!\n"); - return; - } - - iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len); - if (iranges == NULL || len < 2 * sizeof(unsigned int)) - return; /* not distributed */ - - /* - * The first pair of cells in interrupt-ranges refers to the - * IDU; subsequent pairs refer to the ISUs. - */ - len /= 2 * sizeof(unsigned int); - if (np->n_addrs < len) { - printk(KERN_ERR "Insufficient addresses for distributed" - " OpenPIC (%d < %d)\n", np->n_addrs, len); - return; - } - if (iranges[1] != 0) { - printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", - iranges[0], iranges[0] + iranges[1] - 1); - openpic_set_sources(iranges[0], iranges[1], NULL); - } - for (i = 1; i < len; ++i) { - iranges += 2; - printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x (%x)\n", - iranges[0], iranges[0] + iranges[1] - 1, - np->addrs[i].address, np->addrs[i].size); - isu = ioremap(np->addrs[i].address, np->addrs[i].size); - if (isu != NULL) - openpic_set_sources(iranges[0], iranges[1], isu); - else - printk(KERN_ERR "Failed to map OpenPIC ISU at %x!\n", - np->addrs[i].address); - } -} - -#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) -static struct irqaction xmon_irqaction = { - .handler = xmon_irq, - .mask = CPU_MASK_NONE, - .name = "XMON break", -}; -#endif - -void __init chrp_init_IRQ(void) -{ - struct device_node *np; - unsigned long chrp_int_ack = 0; - unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS]; -#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) - struct device_node *kbd; -#endif - - for (np = find_devices("pci"); np != NULL; np = np->next) { - unsigned int *addrp = (unsigned int *) - get_property(np, "8259-interrupt-acknowledge", NULL); - - if (addrp == NULL) - continue; - chrp_int_ack = addrp[prom_n_addr_cells(np)-1]; - break; - } - if (np == NULL) - printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n"); - - chrp_find_openpic(); - - if (OpenPIC_Addr) { - prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS); - OpenPIC_InitSenses = init_senses; - OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS; - - openpic_init(NUM_8259_INTERRUPTS); - /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */ - openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade", - i8259_irq); - - } - i8259_init(chrp_int_ack, 0); - -#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) - /* see if there is a keyboard in the device tree - with a parent of type "adb" */ - for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next) - if (kbd->parent && kbd->parent->type - && strcmp(kbd->parent->type, "adb") == 0) - break; - if (kbd) - setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); -#endif -} - -void __init -chrp_init2(void) -{ -#ifdef CONFIG_NVRAM - chrp_nvram_init(); -#endif - - request_region(0x20,0x20,"pic1"); - request_region(0xa0,0x20,"pic2"); - request_region(0x00,0x20,"dma1"); - request_region(0x40,0x20,"timer"); - request_region(0x80,0x10,"dma page reg"); - request_region(0xc0,0x20,"dma2"); - - if (ppc_md.progress) - ppc_md.progress(" Have fun! ", 0x7777); -} - -static struct device_node *memory_node; - -static int __init get_mem_prop(char *name, struct mem_pieces *mp) -{ - struct reg_property *rp; - int i, s; - unsigned int *ip; - int nac = prom_n_addr_cells(memory_node); - int nsc = prom_n_size_cells(memory_node); - - ip = (unsigned int *) get_property(memory_node, name, &s); - if (ip == NULL) { - printk(KERN_ERR "error: couldn't get %s property on /memory\n", - name); - return 0; - } - s /= (nsc + nac) * 4; - rp = mp->regions; - for (i = 0; i < s; ++i, ip += nac+nsc) { - if (nac >= 2 && ip[nac-2] != 0) - continue; - rp->address = ip[nac-1]; - if (nsc >= 2 && ip[nac+nsc-2] != 0) - rp->size = ~0U; - else - rp->size = ip[nac+nsc-1]; - ++rp; - } - mp->n_regions = rp - mp->regions; - - /* Make sure the pieces are sorted. */ - mem_pieces_sort(mp); - mem_pieces_coalesce(mp); - return 1; -} - -static unsigned long __init chrp_find_end_of_memory(void) -{ - unsigned long a, total; - struct mem_pieces phys_mem; - - /* - * Find out where physical memory is, and check that it - * starts at 0 and is contiguous. It seems that RAM is - * always physically contiguous on Power Macintoshes. - * - * Supporting discontiguous physical memory isn't hard, - * it just makes the virtual <-> physical mapping functions - * more complicated (or else you end up wasting space - * in mem_map). - */ - memory_node = find_devices("memory"); - if (memory_node == NULL || !get_mem_prop("reg", &phys_mem) - || phys_mem.n_regions == 0) - panic("No RAM??"); - a = phys_mem.regions[0].address; - if (a != 0) - panic("RAM doesn't start at physical address 0"); - total = phys_mem.regions[0].size; - - if (phys_mem.n_regions > 1) { - printk("RAM starting at 0x%x is not contiguous\n", - phys_mem.regions[1].address); - printk("Using RAM from 0 to 0x%lx\n", total-1); - } - - return total; -} - -void __init -chrp_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7) -{ - struct device_node *root = find_path_device ("/"); - char *machine = NULL; - -#ifdef CONFIG_BLK_DEV_INITRD - /* take care of initrd if we have one */ - if ( r6 ) - { - initrd_start = r6 + KERNELBASE; - initrd_end = r6 + r7 + KERNELBASE; - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - ISA_DMA_THRESHOLD = ~0L; - DMA_MODE_READ = 0x44; - DMA_MODE_WRITE = 0x48; - isa_io_base = CHRP_ISA_IO_BASE; /* default value */ - ppc_do_canonicalize_irqs = 1; - - if (root) - machine = get_property(root, "model", NULL); - if (machine && strncmp(machine, "Pegasos", 7) == 0) { - _chrp_type = _CHRP_Pegasos; - } else if (machine && strncmp(machine, "IBM", 3) == 0) { - _chrp_type = _CHRP_IBM; - } else if (machine && strncmp(machine, "MOT", 3) == 0) { - _chrp_type = _CHRP_Motorola; - } else { - /* Let's assume it is an IBM chrp if all else fails */ - _chrp_type = _CHRP_IBM; - } - - ppc_md.setup_arch = chrp_setup_arch; - ppc_md.show_percpuinfo = of_show_percpuinfo; - ppc_md.show_cpuinfo = chrp_show_cpuinfo; - - ppc_md.init_IRQ = chrp_init_IRQ; - if (_chrp_type == _CHRP_Pegasos) - ppc_md.get_irq = i8259_irq; - else - ppc_md.get_irq = openpic_get_irq; - - ppc_md.init = chrp_init2; - - ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; - - ppc_md.restart = chrp_restart; - ppc_md.power_off = chrp_power_off; - ppc_md.halt = chrp_halt; - - ppc_md.time_init = chrp_time_init; - ppc_md.set_rtc_time = chrp_set_rtc_time; - ppc_md.get_rtc_time = chrp_get_rtc_time; - ppc_md.calibrate_decr = chrp_calibrate_decr; - - ppc_md.find_end_of_memory = chrp_find_end_of_memory; - - if (rtas_data) { - struct device_node *rtas; - unsigned int *p; - - rtas = find_devices("rtas"); - if (rtas != NULL) { - if (get_property(rtas, "display-character", NULL)) { - ppc_md.progress = rtas_display_progress; - p = (unsigned int *) get_property - (rtas, "ibm,display-line-length", NULL); - if (p) - max_width = *p; - } else if (get_property(rtas, "set-indicator", NULL)) - ppc_md.progress = rtas_indicator_progress; - } - } -#ifdef CONFIG_BOOTX_TEXT - if (ppc_md.progress == NULL && boot_text_mapped) - ppc_md.progress = btext_progress; -#endif - -#ifdef CONFIG_SMP - smp_ops = &chrp_smp_ops; -#endif /* CONFIG_SMP */ - - /* - * Print the banner, then scroll down so boot progress - * can be printed. -- Cort - */ - if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); -} - -void -rtas_display_progress(char *s, unsigned short hex) -{ - int width; - char *os = s; - - if ( call_rtas( "display-character", 1, 1, NULL, '\r' ) ) - return; - - width = max_width; - while ( *os ) - { - if ( (*os == '\n') || (*os == '\r') ) - width = max_width; - else - width--; - call_rtas( "display-character", 1, 1, NULL, *os++ ); - /* if we overwrite the screen length */ - if ( width == 0 ) - while ( (*os != 0) && (*os != '\n') && (*os != '\r') ) - os++; - } - - /*while ( width-- > 0 )*/ - call_rtas( "display-character", 1, 1, NULL, ' ' ); -} - -void -rtas_indicator_progress(char *s, unsigned short hex) -{ - call_rtas("set-indicator", 3, 1, NULL, 6, 0, hex); -} - -#ifdef CONFIG_BOOTX_TEXT -void -btext_progress(char *s, unsigned short hex) -{ - prom_print(s); - prom_print("\n"); -} -#endif /* CONFIG_BOOTX_TEXT */ diff --git a/arch/ppc/platforms/chrp_smp.c b/arch/ppc/platforms/chrp_smp.c deleted file mode 100644 index 97e539557ec..00000000000 --- a/arch/ppc/platforms/chrp_smp.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Smp support for CHRP machines. - * - * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great - * deal of code from the sparc and intel versions. - * - * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> - * - */ - -#include <linux/config.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/smp.h> -#include <linux/smp_lock.h> -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/spinlock.h> - -#include <asm/ptrace.h> -#include <asm/atomic.h> -#include <asm/irq.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/sections.h> -#include <asm/io.h> -#include <asm/prom.h> -#include <asm/smp.h> -#include <asm/residual.h> -#include <asm/time.h> -#include <asm/open_pic.h> -#include <asm/machdep.h> - -extern unsigned long smp_chrp_cpu_nr; - -static int __init -smp_chrp_probe(void) -{ - if (smp_chrp_cpu_nr > 1) - openpic_request_IPIs(); - - return smp_chrp_cpu_nr; -} - -static void __devinit -smp_chrp_kick_cpu(int nr) -{ - *(unsigned long *)KERNELBASE = nr; - asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory"); -} - -static void __devinit -smp_chrp_setup_cpu(int cpu_nr) -{ - if (OpenPIC_Addr) - do_openpic_setup_cpu(); -} - -static DEFINE_SPINLOCK(timebase_lock); -static unsigned int timebase_upper = 0, timebase_lower = 0; - -void __devinit -smp_chrp_give_timebase(void) -{ - spin_lock(&timebase_lock); - call_rtas("freeze-time-base", 0, 1, NULL); - timebase_upper = get_tbu(); - timebase_lower = get_tbl(); - spin_unlock(&timebase_lock); - - while (timebase_upper || timebase_lower) - barrier(); - call_rtas("thaw-time-base", 0, 1, NULL); -} - -void __devinit -smp_chrp_take_timebase(void) -{ - while (!(timebase_upper || timebase_lower)) - barrier(); - spin_lock(&timebase_lock); - set_tb(timebase_upper, timebase_lower); - timebase_upper = 0; - timebase_lower = 0; - spin_unlock(&timebase_lock); - printk("CPU %i taken timebase\n", smp_processor_id()); -} - -/* CHRP with openpic */ -struct smp_ops_t chrp_smp_ops = { - .message_pass = smp_openpic_message_pass, - .probe = smp_chrp_probe, - .kick_cpu = smp_chrp_kick_cpu, - .setup_cpu = smp_chrp_setup_cpu, - .give_timebase = smp_chrp_give_timebase, - .take_timebase = smp_chrp_take_timebase, -}; diff --git a/arch/ppc/platforms/chrp_time.c b/arch/ppc/platforms/chrp_time.c deleted file mode 100644 index 57753a55b58..00000000000 --- a/arch/ppc/platforms/chrp_time.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * arch/ppc/platforms/chrp_time.c - * - * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * - * Adapted for PowerPC (PReP) by Gary Thomas - * Modified by Cort Dougan (cort@cs.nmt.edu). - * Copied and modified from arch/i386/kernel/time.c - * - */ -#include <linux/errno.h> -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/time.h> -#include <linux/timex.h> -#include <linux/kernel_stat.h> -#include <linux/mc146818rtc.h> -#include <linux/init.h> -#include <linux/bcd.h> - -#include <asm/io.h> -#include <asm/nvram.h> -#include <asm/prom.h> -#include <asm/sections.h> -#include <asm/time.h> - -extern spinlock_t rtc_lock; - -static int nvram_as1 = NVRAM_AS1; -static int nvram_as0 = NVRAM_AS0; -static int nvram_data = NVRAM_DATA; - -long __init chrp_time_init(void) -{ - struct device_node *rtcs; - int base; - - rtcs = find_compatible_devices("rtc", "pnpPNP,b00"); - if (rtcs == NULL) - rtcs = find_compatible_devices("rtc", "ds1385-rtc"); - if (rtcs == NULL || rtcs->addrs == NULL) - return 0; - base = rtcs->addrs[0].address; - nvram_as1 = 0; - nvram_as0 = base; - nvram_data = base + 1; - - return 0; -} - -int chrp_cmos_clock_read(int addr) -{ - if (nvram_as1 != 0) - outb(addr>>8, nvram_as1); - outb(addr, nvram_as0); - return (inb(nvram_data)); -} - -void chrp_cmos_clock_write(unsigned long val, int addr) -{ - if (nvram_as1 != 0) - outb(addr>>8, nvram_as1); - outb(addr, nvram_as0); - outb(val, nvram_data); - return; -} - -/* - * Set the hardware clock. -- Cort - */ -int chrp_set_rtc_time(unsigned long nowtime) -{ - unsigned char save_control, save_freq_select; - struct rtc_time tm; - - spin_lock(&rtc_lock); - to_tm(nowtime, &tm); - - save_control = chrp_cmos_clock_read(RTC_CONTROL); /* tell the clock it's being set */ - - chrp_cmos_clock_write((save_control|RTC_SET), RTC_CONTROL); - - save_freq_select = chrp_cmos_clock_read(RTC_FREQ_SELECT); /* stop and reset prescaler */ - - chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); - - tm.tm_year -= 1900; - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(tm.tm_sec); - BIN_TO_BCD(tm.tm_min); - BIN_TO_BCD(tm.tm_hour); - BIN_TO_BCD(tm.tm_mon); - BIN_TO_BCD(tm.tm_mday); - BIN_TO_BCD(tm.tm_year); - } - chrp_cmos_clock_write(tm.tm_sec,RTC_SECONDS); - chrp_cmos_clock_write(tm.tm_min,RTC_MINUTES); - chrp_cmos_clock_write(tm.tm_hour,RTC_HOURS); - chrp_cmos_clock_write(tm.tm_mon,RTC_MONTH); - chrp_cmos_clock_write(tm.tm_mday,RTC_DAY_OF_MONTH); - chrp_cmos_clock_write(tm.tm_year,RTC_YEAR); - - /* The following flags have to be released exactly in this order, - * otherwise the DS12887 (popular MC146818A clone with integrated - * battery and quartz) will not reset the oscillator and will not - * update precisely 500 ms later. You won't find this mentioned in - * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn - */ - chrp_cmos_clock_write(save_control, RTC_CONTROL); - chrp_cmos_clock_write(save_freq_select, RTC_FREQ_SELECT); - - spin_unlock(&rtc_lock); - return 0; -} - -unsigned long chrp_get_rtc_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - int uip, i; - - /* The Linux interpretation of the CMOS clock register contents: - * When the Update-In-Progress (UIP) flag goes from 1 to 0, the - * RTC registers show the second which has precisely just started. - * Let's hope other operating systems interpret the RTC the same way. - */ - - /* Since the UIP flag is set for about 2.2 ms and the clock - * is typically written with a precision of 1 jiffy, trying - * to obtain a precision better than a few milliseconds is - * an illusion. Only consistency is interesting, this also - * allows to use the routine for /dev/rtc without a potential - * 1 second kernel busy loop triggered by any reader of /dev/rtc. - */ - - for ( i = 0; i<1000000; i++) { - uip = chrp_cmos_clock_read(RTC_FREQ_SELECT); - sec = chrp_cmos_clock_read(RTC_SECONDS); - min = chrp_cmos_clock_read(RTC_MINUTES); - hour = chrp_cmos_clock_read(RTC_HOURS); - day = chrp_cmos_clock_read(RTC_DAY_OF_MONTH); - mon = chrp_cmos_clock_read(RTC_MONTH); - year = chrp_cmos_clock_read(RTC_YEAR); - uip |= chrp_cmos_clock_read(RTC_FREQ_SELECT); - if ((uip & RTC_UIP)==0) break; - } - - if (!(chrp_cmos_clock_read(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); - } - if ((year += 1900) < 1970) - year += 100; - return mktime(year, mon, day, hour, min, sec); -} - -/* - * Calibrate the decrementer frequency with the VIA timer 1. - */ -#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */ - -/* VIA registers */ -#define RS 0x200 /* skip between registers */ -#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ -#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ -#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ -#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ -#define ACR (11*RS) /* Auxiliary control register */ -#define IFR (13*RS) /* Interrupt flag register */ - -/* Bits in ACR */ -#define T1MODE 0xc0 /* Timer 1 mode */ -#define T1MODE_CONT 0x40 /* continuous interrupts */ - -/* Bits in IFR and IER */ -#define T1_INT 0x40 /* Timer 1 interrupt */ - -static int __init chrp_via_calibrate_decr(void) -{ - struct device_node *vias; - volatile unsigned char __iomem *via; - int count = VIA_TIMER_FREQ_6 / 100; - unsigned int dstart, dend; - - vias = find_devices("via-cuda"); - if (vias == 0) - vias = find_devices("via"); - if (vias == 0 || vias->n_addrs == 0) - return 0; - via = ioremap(vias->addrs[0].address, vias->addrs[0].size); - - /* set timer 1 for continuous interrupts */ - out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT); - /* set the counter to a small value */ - out_8(&via[T1CH], 2); - /* set the latch to `count' */ - out_8(&via[T1LL], count); - out_8(&via[T1LH], count >> 8); - /* wait until it hits 0 */ - while ((in_8(&via[IFR]) & T1_INT) == 0) - ; - dstart = get_dec(); - /* clear the interrupt & wait until it hits 0 again */ - in_8(&via[T1CL]); - while ((in_8(&via[IFR]) & T1_INT) == 0) - ; - dend = get_dec(); - - tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100); - tb_to_us = mulhwu_scale_factor(dstart - dend, 60000); - - printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n", - tb_ticks_per_jiffy, dstart - dend); - - iounmap(via); - - return 1; -} - -void __init chrp_calibrate_decr(void) -{ - struct device_node *cpu; - unsigned int freq, *fp; - - if (chrp_via_calibrate_decr()) - return; - - /* - * The cpu node should have a timebase-frequency property - * to tell us the rate at which the decrementer counts. - */ - freq = 16666000; /* hardcoded default */ - cpu = find_type_devices("cpu"); - if (cpu != 0) { - fp = (unsigned int *) - get_property(cpu, "timebase-frequency", NULL); - if (fp != 0) - freq = *fp; - } - printk("time_init: decrementer frequency = %u.%.6u MHz\n", - freq/1000000, freq%1000000); - tb_ticks_per_jiffy = freq / HZ; - tb_to_us = mulhwu_scale_factor(freq, 1000000); -} diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c index 6ca7bcac947..790475c22fd 100644 --- a/arch/ppc/platforms/cpci690.c +++ b/arch/ppc/platforms/cpci690.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/cpci690.c - * * Board setup routines for the Force CPCI690 board. * * Author: Mark A. Greer <mgreer@mvista.com> @@ -290,7 +288,7 @@ cpci690_fixup_mpsc_pdata(struct platform_device *pdev) pdata->brg_clk_freq = cpci690_get_bus_freq(); } -static int __init +static int cpci690_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h index 49584c9cedf..0fa5a4c31b6 100644 --- a/arch/ppc/platforms/cpci690.h +++ b/arch/ppc/platforms/cpci690.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/cpci690.h - * * Definitions for Force CPCI690 * * Author: Mark A. Greer <mgreer@mvista.com> diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c index ffde8f6f630..31e8e21e1d5 100644 --- a/arch/ppc/platforms/ev64260.c +++ b/arch/ppc/platforms/ev64260.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64260.c - * * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board. * * Author: Mark A. Greer <mgreer@mvista.com> @@ -416,7 +414,7 @@ ev64260_fixup_mpsc_pdata(struct platform_device *pdev) return; } -static int __init +static int ev64260_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/ev64260.h b/arch/ppc/platforms/ev64260.h index bedffced3a0..44d90d56745 100644 --- a/arch/ppc/platforms/ev64260.h +++ b/arch/ppc/platforms/ev64260.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64260.h - * * Definitions for Marvell/Galileo EV-64260-BP Evaluation Board. * * Author: Mark A. Greer <mgreer@mvista.com> diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c index b9d844f88c2..104ac9b16e8 100644 --- a/arch/ppc/platforms/ev64360.c +++ b/arch/ppc/platforms/ev64360.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64360.c - * * Board setup routines for the Marvell EV-64360-BP Evaluation Board. * * Author: Lee Nicks <allinux@gmail.com> @@ -300,7 +298,7 @@ ev64360_fixup_eth_pdata(struct platform_device *pdev) } #endif -static int __init +static int ev64360_platform_notify(struct device *dev) { static struct { diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h index 68eabe49039..b30f4722690 100644 --- a/arch/ppc/platforms/ev64360.h +++ b/arch/ppc/platforms/ev64360.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/ev64360.h - * * Definitions for Marvell EV-64360-BP Evaluation Board. * * Author: Lee Nicks <allinux@gmail.com> diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h index a48fb8d723e..e1c0b1b6dcb 100644 --- a/arch/ppc/platforms/fads.h +++ b/arch/ppc/platforms/fads.h @@ -112,7 +112,7 @@ /* CPM Ethernet through SCC1 or SCC2 */ -#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */ +#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */ /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC1 use. * TCLK - CLK1, RCLK - CLK2. diff --git a/arch/ppc/platforms/gemini.h b/arch/ppc/platforms/gemini.h index 06de5924891..5528fd0a121 100644 --- a/arch/ppc/platforms/gemini.h +++ b/arch/ppc/platforms/gemini.h @@ -1,7 +1,4 @@ /* - * arch/ppc/platforms/gemini.h - * - * * Onboard registers and descriptions for Synergy Microsystems' * "Gemini" boards. * diff --git a/arch/ppc/platforms/gemini_prom.S b/arch/ppc/platforms/gemini_prom.S index 8c5065d5650..b181f210800 100644 --- a/arch/ppc/platforms/gemini_prom.S +++ b/arch/ppc/platforms/gemini_prom.S @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/gemini_prom.S - * * Not really prom support code (yet), but sort of anti-prom code. The current * bootloader does a number of things it shouldn't and doesn't do things that it * should. The stuff in here is mainly a hodge-podge collection of setup code diff --git a/arch/ppc/platforms/gemini_setup.c b/arch/ppc/platforms/gemini_setup.c index 729897c5903..0090ff15460 100644 --- a/arch/ppc/platforms/gemini_setup.c +++ b/arch/ppc/platforms/gemini_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/gemini_setup.c - * * Copyright (C) 1995 Linus Torvalds * Adapted from 'alpha' version by Gary Thomas * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c index 50039a204c2..75dc2ee87d2 100644 --- a/arch/ppc/platforms/hdpu.c +++ b/arch/ppc/platforms/hdpu.c @@ -1,7 +1,4 @@ - /* - * arch/ppc/platforms/hdpu_setup.c - * * Board setup routines for the Sky Computers HDPU Compute Blade. * * Written by Brian Waite <waite@skycomputers.com> @@ -319,11 +316,10 @@ static void __init hdpu_fixup_eth_pdata(struct platform_device *pd) struct mv643xx_eth_platform_data *eth_pd; eth_pd = pd->dev.platform_data; - eth_pd->port_serial_control = - mv64x60_read(&bh, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd->id) & ~1); - eth_pd->force_phy_addr = 1; eth_pd->phy_addr = pd->id; + eth_pd->speed = SPEED_100; + eth_pd->duplex = DUPLEX_FULL; eth_pd->tx_queue_size = 400; eth_pd->rx_queue_size = 800; } @@ -354,7 +350,7 @@ static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd) } #endif -static int __init hdpu_platform_notify(struct device *dev) +static int hdpu_platform_notify(struct device *dev) { static struct { char *bus_id; diff --git a/arch/ppc/platforms/hdpu.h b/arch/ppc/platforms/hdpu.h index 07c3cffb5c7..f9e020b6970 100644 --- a/arch/ppc/platforms/hdpu.h +++ b/arch/ppc/platforms/hdpu.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/hdpu.h - * * Definitions for Sky Computers HDPU board. * * Brian Waite <waite@skycomputers.com> diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index 6e58e30ceed..ad21280e892 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/katana.c - * * Board setup routines for the Artesyn Katana cPCI boards. * * Author: Tim Montgomery <timm@artesyncp.com> @@ -598,7 +596,7 @@ katana_fixup_mv64xxx_pdata(struct platform_device *pdev) } #endif -static int __init +static int katana_platform_notify(struct device *dev) { static struct { @@ -664,12 +662,11 @@ katana_setup_mtd(void) ptbl_entries = (size >= (64*MB)) ? 6 : 4; - if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition), + if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition), GFP_KERNEL)) == NULL) { printk(KERN_WARNING "Can't alloc MTD partition table\n"); return -ENOMEM; } - memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition)); ptbl[0].name = "Monitor"; ptbl[0].size = KATANA_MTD_MONITOR_SIZE; diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h index 597257eff2e..0a9b036526b 100644 --- a/arch/ppc/platforms/katana.h +++ b/arch/ppc/platforms/katana.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/katana.h - * * Definitions for Artesyn Katana750i/3750 board. * * Author: Tim Montgomery <timm@artesyncp.com> diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c index 7ed52dc340c..fecbe9adc9e 100644 --- a/arch/ppc/platforms/lite5200.c +++ b/arch/ppc/platforms/lite5200.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/lite5200.c - * * Platform support file for the Freescale LITE5200 based on MPC52xx. * A maximum of this file should be moved to syslib/mpc52xx_????? * so that new platform based on MPC52xx need a minimal platform file @@ -36,8 +34,7 @@ #include <asm/mpc52xx.h> #include <asm/ppc_sys.h> #include <asm/machdep.h> - -#include <syslib/mpc52xx_pci.h> +#include <asm/pci-bridge.h> extern int powersave_nap; @@ -70,44 +67,53 @@ lite5200_show_cpuinfo(struct seq_file *m) } #ifdef CONFIG_PCI +#ifdef CONFIG_LITE5200B +static int +lite5200_map_irq(struct pci_dev *dev, unsigned char idsel, + unsigned char pin) +{ + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + {MPC52xx_IRQ0, MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3}, + {MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3, MPC52xx_IRQ0}, + }; + + const long min_idsel = 24, max_idsel = 25, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; +} +#else /* Original Lite */ static int lite5200_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) { return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1; } #endif +#endif static void __init lite5200_setup_cpu(void) { - struct mpc52xx_cdm __iomem *cdm; struct mpc52xx_gpio __iomem *gpio; struct mpc52xx_intr __iomem *intr; - struct mpc52xx_xlb __iomem *xlb; u32 port_config; u32 intr_ctrl; /* Map zones */ - cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE); gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE); - xlb = ioremap(MPC52xx_PA(MPC52xx_XLB_OFFSET), MPC52xx_XLB_SIZE); intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE); - if (!cdm || !gpio || !xlb || !intr) { - printk("lite5200.c: Error while mapping CDM/GPIO/XLB/INTR during" - "lite5200_setup_cpu\n"); + if (!gpio || !intr) { + printk(KERN_ERR __FILE__ ": " + "Error while mapping GPIO/INTR during " + "lite5200_setup_cpu\n"); goto unmap_regs; } - /* Use internal 48 Mhz */ - out_8(&cdm->ext_48mhz_en, 0x00); - out_8(&cdm->fd_enable, 0x01); - if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ - out_be16(&cdm->fd_counters, 0x0001); - else - out_be16(&cdm->fd_counters, 0x5555); - /* Get port mux config */ port_config = in_be32(&gpio->port_config); @@ -118,29 +124,29 @@ lite5200_setup_cpu(void) port_config &= ~0x00007000; /* Differential mode - USB1 only */ port_config |= 0x00001000; + /* ATA CS is on csb_4/5 */ + port_config &= ~0x03000000; + port_config |= 0x01000000; + /* Commit port config */ out_be32(&gpio->port_config, port_config); - /* Configure the XLB Arbiter */ - out_be32(&xlb->master_pri_enable, 0xff); - out_be32(&xlb->master_priority, 0x11111111); - - /* Enable ram snooping for 1GB window */ - out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_SNOOP); - out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d); - - /* IRQ[0-3] setup : IRQ0 - Level Active Low */ - /* IRQ[1-3] - Level Active High */ + /* IRQ[0-3] setup */ intr_ctrl = in_be32(&intr->ctrl); intr_ctrl &= ~0x00ff0000; - intr_ctrl |= 0x00c00000; +#ifdef CONFIG_LITE5200B + /* IRQ[0-3] Level Active Low */ + intr_ctrl |= 0x00ff0000; +#else + /* IRQ0 Level Active Low + * IRQ[1-3] Level Active High */ + intr_ctrl |= 0x00c00000; +#endif out_be32(&intr->ctrl, intr_ctrl); /* Unmap reg zone */ unmap_regs: - if (cdm) iounmap(cdm); if (gpio) iounmap(gpio); - if (xlb) iounmap(xlb); if (intr) iounmap(intr); } @@ -148,7 +154,8 @@ static void __init lite5200_setup_arch(void) { /* CPU & Port mux setup */ - lite5200_setup_cpu(); + mpc52xx_setup_cpu(); /* Generic */ + lite5200_setup_cpu(); /* Platform specific */ #ifdef CONFIG_PCI /* PCI Bridge setup */ diff --git a/arch/ppc/platforms/lite5200.h b/arch/ppc/platforms/lite5200.h index c1de2aa4717..852a18e24d0 100644 --- a/arch/ppc/platforms/lite5200.h +++ b/arch/ppc/platforms/lite5200.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/lite5200.h - * * Definitions for Freescale LITE5200 : MPC52xx Standard Development * Platform board support * diff --git a/arch/ppc/platforms/lopec.c b/arch/ppc/platforms/lopec.c index 06d247c23b8..c6445a727ca 100644 --- a/arch/ppc/platforms/lopec.c +++ b/arch/ppc/platforms/lopec.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/lopec.c - * * Setup routines for the Motorola LoPEC. * * Author: Dan Cox diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c new file mode 100644 index 00000000000..bc9b94f77e3 --- /dev/null +++ b/arch/ppc/platforms/mpc8272ads_setup.c @@ -0,0 +1,236 @@ +/* + * arch/ppc/platforms/82xx/pq2ads_pd.c + * + * MPC82xx Board-specific PlatformDevice descriptions + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/ioport.h> +#include <linux/fs_enet_pd.h> +#include <linux/platform_device.h> + +#include <asm/io.h> +#include <asm/mpc8260.h> +#include <asm/cpm2.h> +#include <asm/immap_cpm2.h> +#include <asm/irq.h> +#include <asm/ppc_sys.h> +#include <asm/ppcboot.h> + +#include "pq2ads_pd.h" + +static void init_fcc1_ioports(void); +static void init_fcc2_ioports(void); + +static struct fs_mii_bus_info mii_bus_info = { + .method = fsmii_bitbang, + .id = 0, + .i.bitbang = { + .mdio_port = fsiop_portc, + .mdio_bit = 18, + .mdc_port = fsiop_portc, + .mdc_bit = 19, + .delay = 1, + }, +}; + +static struct fs_platform_info mpc82xx_fcc1_pdata = { + .fs_no = fsid_fcc1, + .cp_page = CPM_CR_FCC1_PAGE, + .cp_block = CPM_CR_FCC1_SBLOCK, + .clk_trx = (PC_F1RXCLK | PC_F1TXCLK), + .clk_route = CMX1_CLK_ROUTE, + .clk_mask = CMX1_CLK_MASK, + .init_ioports = init_fcc1_ioports, + + .phy_addr = 0, +#ifdef PHY_INTERRUPT + .phy_irq = PHY_INTERRUPT, +#else + .phy_irq = -1; +#endif + .mem_offset = FCC1_MEM_OFFSET, + .bus_info = &mii_bus_info, + .rx_ring = 32, + .tx_ring = 32, + .rx_copybreak = 240, + .use_napi = 0, + .napi_weight = 17, +}; + +static struct fs_platform_info mpc82xx_fcc2_pdata = { + .fs_no = fsid_fcc2, + .cp_page = CPM_CR_FCC2_PAGE, + .cp_block = CPM_CR_FCC2_SBLOCK, + .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), + .clk_route = CMX2_CLK_ROUTE, + .clk_mask = CMX2_CLK_MASK, + .init_ioports = init_fcc2_ioports, + + .phy_addr = 3, +#ifdef PHY_INTERRUPT + .phy_irq = PHY_INTERRUPT, +#else + .phy_irq = -1; +#endif + .mem_offset = FCC2_MEM_OFFSET, + .bus_info = &mii_bus_info, + .rx_ring = 32, + .tx_ring = 32, + .rx_copybreak = 240, + .use_napi = 0, + .napi_weight = 17, +}; + +static void init_fcc1_ioports(void) +{ + struct io_port *io; + u32 tempval; + cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t)); + u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32)); + + io = &immap->im_ioport; + + /* Enable the PHY */ + clrbits32(bcsr, BCSR1_FETHIEN); + setbits32(bcsr, BCSR1_FETH_RST); + + /* FCC1 pins are on port A/C. */ + /* Configure port A and C pins for FCC1 Ethernet. */ + + tempval = in_be32(&io->iop_pdira); + tempval &= ~PA1_DIRA0; + tempval |= PA1_DIRA1; + out_be32(&io->iop_pdira, tempval); + + tempval = in_be32(&io->iop_psora); + tempval &= ~PA1_PSORA0; + tempval |= PA1_PSORA1; + out_be32(&io->iop_psora, tempval); + + setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1); + + /* Alter clocks */ + tempval = PC_F1TXCLK|PC_F1RXCLK; + + clrbits32(&io->iop_psorc, tempval); + clrbits32(&io->iop_pdirc, tempval); + setbits32(&io->iop_pparc, tempval); + + clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK); + setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE); + iounmap(bcsr); + iounmap(immap); +} + +static void init_fcc2_ioports(void) +{ + cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t)); + u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32)); + + struct io_port *io; + u32 tempval; + + immap = cpm2_immr; + + io = &immap->im_ioport; + + /* Enable the PHY */ + clrbits32(bcsr, BCSR3_FETHIEN2); + setbits32(bcsr, BCSR3_FETH2_RST); + + /* FCC2 are port B/C. */ + /* Configure port A and C pins for FCC2 Ethernet. */ + + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB2_DIRB0; + tempval |= PB2_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB2_PSORB0; + tempval |= PB2_PSORB1; + out_be32(&io->iop_psorb, tempval); + + setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1); + + tempval = PC_F2RXCLK|PC_F2TXCLK; + + /* Alter clocks */ + clrbits32(&io->iop_psorc,tempval); + clrbits32(&io->iop_pdirc,tempval); + setbits32(&io->iop_pparc,tempval); + + clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK); + setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE); + + iounmap(bcsr); + iounmap(immap); +} + + +static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev, + int idx) +{ + bd_t* bi = (void*)__res; + int fs_no = fsid_fcc1+pdev->id-1; + + mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase; + mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c; + + switch(fs_no) { + case fsid_fcc1: + memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6); + pdev->dev.platform_data = &mpc82xx_fcc1_pdata; + break; + case fsid_fcc2: + memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6); + mpc82xx_fcc2_pdata.macaddr[5] ^= 1; + pdev->dev.platform_data = &mpc82xx_fcc2_pdata; + break; + } +} + +static int mpc8272ads_platform_notify(struct device *dev) +{ + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fcc", + .rtn = mpc8272ads_fixup_enet_pdata + }, + { + .bus_id = NULL + } + }; + platform_notify_map(dev_map,dev); + + return 0; + +} + +int __init mpc8272ads_init(void) +{ + printk(KERN_NOTICE "mpc8272ads: Init\n"); + + platform_notify = mpc8272ads_platform_notify; + + ppc_sys_device_initfunc(); + + ppc_sys_device_disable_all(); + ppc_sys_device_enable(MPC82xx_CPM_FCC1); + ppc_sys_device_enable(MPC82xx_CPM_FCC2); + + return 0; +} + +arch_initcall(mpc8272ads_init); diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c new file mode 100644 index 00000000000..ac8fcc68afe --- /dev/null +++ b/arch/ppc/platforms/mpc866ads_setup.c @@ -0,0 +1,273 @@ +/*arch/ppc/platforms/mpc885ads-setup.c + * + * Platform setup for the Freescale mpc885ads board + * + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/device.h> + +#include <linux/fs_enet_pd.h> +#include <linux/mii.h> + +#include <asm/delay.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/page.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/ppcboot.h> +#include <asm/8xx_immap.h> +#include <asm/commproc.h> +#include <asm/ppc_sys.h> +#include <asm/mpc8xx.h> + +extern unsigned char __res[]; + +static struct fs_mii_bus_info fec_mii_bus_info = { + .method = fsmii_fec, + .id = 0, +}; + +static struct fs_mii_bus_info scc_mii_bus_info = { + .method = fsmii_fixed, + .id = 0, + .i.fixed.speed = 10, + .i.fixed.duplex = 0, +}; + +static struct fs_platform_info mpc8xx_fec_pdata[] = { + { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 15, + .phy_irq = -1, + + .use_rmii = 0, + + .bus_info = &fec_mii_bus_info, + } +}; + +static struct fs_platform_info mpc8xx_scc_pdata = { + .rx_ring = 64, + .tx_ring = 8, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = -1, + .phy_irq = -1, + + .bus_info = &scc_mii_bus_info, +}; + +void __init board_init(void) +{ + volatile cpm8xx_t *cp = cpmp; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ + clrbits32(bcsr_io,(0x80000000 >> 7)); +#else + setbits32(bcsr_io,(0x80000000 >> 7)); + + cp->cp_pbpar &= ~(0x000000c0); + cp->cp_pbdir |= 0x000000c0; + cp->cp_smc[0].smc_smcmr = 0; + cp->cp_smc[0].smc_smce = 0; +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + cp->cp_simode &= ~(0xe0000000 >> 1); + cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ + clrbits32(bcsr_io,(0x80000000 >> 13)); +#else + clrbits32(bcsr_io,(0x80000000 >> 13)); + cp->cp_pbpar &= ~(0x00000c00); + cp->cp_pbdir |= 0x00000c00; + cp->cp_smc[1].smc_smcmr = 0; + cp->cp_smc[1].smc_smce = 0; +#endif + iounmap(bcsr_io); +} + +static void setup_fec1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + setbits16(&immap->im_ioport.iop_pdpar, 0x1fff); + setbits16(&immap->im_ioport.iop_pddir, 0x1fff); +} + +static void setup_scc1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } + + /* Enable the PHY. + */ + clrbits32(bcsr_io,BCSR1_ETHEN); + + /* Configure port A pins for Txd and Rxd. + */ + /* Disable receive and transmit in case EPPC-Bug started it. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + /* Configure port A for TCLK and RCLK. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); + setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); + setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); + +} + +static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) +{ + struct fs_platform_info *fpi = pdev->dev.platform_data; + + volatile cpm8xx_t *cp; + bd_t *bd = (bd_t *) __res; + char *e; + int i; + + /* Get pointer to Communication Processor */ + cp = cpmp; + switch (fs_no) { + case fsid_fec1: + fpi = &mpc8xx_fec_pdata[0]; + fpi->init_ioports = &setup_fec1_ioports; + + break; + case fsid_scc1: + fpi = &mpc8xx_scc_pdata; + fpi->init_ioports = &setup_scc1_ioports; + + break; + default: + printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); + return; + } + + pdev->dev.platform_data = fpi; + fpi->fs_no = fs_no; + + e = (unsigned char *)&bd->bi_enetaddr; + for (i = 0; i < 6; i++) + fpi->macaddr[i] = *e++; + + fpi->macaddr[5 - pdev->id]++; + +} + +static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for FEC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) + return; + mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); +} + +static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for SCC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) + return; + + mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); +} + +static int mpc866ads_platform_notify(struct device *dev) +{ + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fec", + .rtn = mpc866ads_fixup_fec_enet_pdata, + }, + { + .bus_id = "fsl-cpm-scc", + .rtn = mpc866ads_fixup_scc_enet_pdata, + }, + { + .bus_id = NULL + } + }; + + platform_notify_map(dev_map,dev); + + return 0; +} + +int __init mpc866ads_init(void) +{ + printk(KERN_NOTICE "mpc866ads: Init\n"); + + platform_notify = mpc866ads_platform_notify; + + ppc_sys_device_initfunc(); + ppc_sys_device_disable_all(); + +#ifdef MPC8xx_SECOND_ETH_SCC1 + ppc_sys_device_enable(MPC8xx_CPM_SCC1); +#endif + ppc_sys_device_enable(MPC8xx_CPM_FEC1); + + return 0; +} + +arch_initcall(mpc866ads_init); diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c new file mode 100644 index 00000000000..50a99e5f7c6 --- /dev/null +++ b/arch/ppc/platforms/mpc885ads_setup.c @@ -0,0 +1,389 @@ +/*arch/ppc/platforms/mpc885ads-setup.c + * + * Platform setup for the Freescale mpc885ads board + * + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/device.h> + +#include <linux/fs_enet_pd.h> +#include <linux/mii.h> + +#include <asm/delay.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/page.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/ppcboot.h> +#include <asm/8xx_immap.h> +#include <asm/commproc.h> +#include <asm/ppc_sys.h> + +extern unsigned char __res[]; + +static void __init mpc885ads_scc_phy_init(char); + +static struct fs_mii_bus_info fec_mii_bus_info = { + .method = fsmii_fec, + .id = 0, +}; + +static struct fs_mii_bus_info scc_mii_bus_info = { +#ifdef CONFIG_SCC_ENET_8xx_FIXED + .method = fsmii_fixed, +#else + .method = fsmii_fec, +#endif + + .id = 0, +}; + +static struct fs_platform_info mpc8xx_fec_pdata[] = { + { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 0, + .phy_irq = SIU_IRQ7, + + .bus_info = &fec_mii_bus_info, + }, { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 1, + .phy_irq = SIU_IRQ7, + + .bus_info = &fec_mii_bus_info, + } +}; + +static struct fs_platform_info mpc8xx_scc_pdata = { + .rx_ring = 64, + .tx_ring = 8, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 2, +#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED + .phy_irq = -1, +#else + .phy_irq = SIU_IRQ7, +#endif + + .bus_info = &scc_mii_bus_info, +}; + +void __init board_init(void) +{ + volatile cpm8xx_t *cp = cpmp; + unsigned int *bcsr_io; + +#ifdef CONFIG_FS_ENET + immap_t *immap = (immap_t *) IMAP_ADDR; +#endif + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ + clrbits32(bcsr_io, BCSR1_RS232EN_1); +#else + setbits32(bcsr_io,BCSR1_RS232EN_1); + cp->cp_smc[0].smc_smcmr = 0; + cp->cp_smc[0].smc_smce = 0; +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + cp->cp_simode &= ~(0xe0000000 >> 1); + cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ + clrbits32(bcsr_io,BCSR1_RS232EN_2); +#else + setbits32(bcsr_io,BCSR1_RS232EN_2); + cp->cp_smc[1].smc_smcmr = 0; + cp->cp_smc[1].smc_smce = 0; +#endif + iounmap(bcsr_io); + +#ifdef CONFIG_FS_ENET + /* use MDC for MII (common) */ + setbits16(&immap->im_ioport.iop_pdpar, 0x0080); + clrbits16(&immap->im_ioport.iop_pddir, 0x0080); +#endif +} + +static void setup_fec1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + /* configure FEC1 pins */ + setbits16(&immap->im_ioport.iop_papar, 0xf830); + setbits16(&immap->im_ioport.iop_padir, 0x0830); + clrbits16(&immap->im_ioport.iop_padir, 0xf000); + setbits32(&immap->im_cpm.cp_pbpar, 0x00001001); + + clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001); + setbits16(&immap->im_ioport.iop_pcpar, 0x000c); + clrbits16(&immap->im_ioport.iop_pcdir, 0x000c); + setbits32(&immap->im_cpm.cp_pepar, 0x00000003); + + setbits32(&immap->im_cpm.cp_pedir, 0x00000003); + clrbits32(&immap->im_cpm.cp_peso, 0x00000003); + clrbits32(&immap->im_cpm.cp_cptr, 0x00000100); +} + +static void setup_fec2_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + /* configure FEC2 pins */ + setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc); + setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc); + setbits32(&immap->im_cpm.cp_peso, 0x00037800); + clrbits32(&immap->im_cpm.cp_peso, 0x000087fc); + clrbits32(&immap->im_cpm.cp_cptr, 0x00000080); +} + +static void setup_scc3_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } + + /* Enable the PHY. + */ + setbits32(bcsr_io+4, BCSR4_ETH10_RST); + /* Configure port A pins for Txd and Rxd. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port E for TCLK and RCLK. + */ + setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); + clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pedir, + PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); + setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); + setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); + + /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. + */ + immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode + * by H/W setting after reset. SCC ethernet controller support only half duplex. + * This discrepancy of modes causes a lot of carrier lost errors. + */ + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA); + setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); + + setbits32(bcsr_io+1, BCSR1_ETHEN); + iounmap(bcsr_io); +} + +static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) +{ + struct fs_platform_info *fpi = pdev->dev.platform_data; + + volatile cpm8xx_t *cp; + bd_t *bd = (bd_t *) __res; + char *e; + int i; + + /* Get pointer to Communication Processor */ + cp = cpmp; + switch (fs_no) { + case fsid_fec1: + fpi = &mpc8xx_fec_pdata[0]; + fpi->init_ioports = &setup_fec1_ioports; + break; + case fsid_fec2: + fpi = &mpc8xx_fec_pdata[1]; + fpi->init_ioports = &setup_fec2_ioports; + break; + case fsid_scc3: + fpi = &mpc8xx_scc_pdata; + fpi->init_ioports = &setup_scc3_ioports; + mpc885ads_scc_phy_init(fpi->phy_addr); + break; + default: + printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); + return; + } + + pdev->dev.platform_data = fpi; + fpi->fs_no = fs_no; + + e = (unsigned char *)&bd->bi_enetaddr; + for (i = 0; i < 6; i++) + fpi->macaddr[i] = *e++; + + fpi->macaddr[5 - pdev->id]++; + +} + +static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for FEC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) + return; + mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); +} + +static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for SCC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) + return; + + mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); +} + +/* SCC ethernet controller does not have MII management channel. FEC1 MII + * channel is used to communicate with the 10Mbit PHY. + */ + +#define MII_ECNTRL_PINMUX 0x4 +#define FEC_ECNTRL_PINMUX 0x00000004 +#define FEC_RCNTRL_MII_MODE 0x00000004 + +/* Make MII read/write commands. + */ +#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \ + ((VAL) & 0xffff) | ((PHY_ADDR) << 23)) + +static void mpc885ads_scc_phy_init(char phy_addr) +{ + volatile immap_t *immap; + volatile fec_t *fecp; + bd_t *bd; + + bd = (bd_t *) __res; + immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */ + fecp = &(immap->im_cpm.cp_fec); + + /* Enable MII pins of the FEC1 + */ + setbits16(&immap->im_ioport.iop_pdpar, 0x0080); + clrbits16(&immap->im_ioport.iop_pddir, 0x0080); + /* Set MII speed to 2.5 MHz + */ + out_be32(&fecp->fec_mii_speed, + ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1); + + /* Enable FEC pin MUX + */ + setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); + setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); + + out_be32(&fecp->fec_mii_data, + mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr)); + udelay(100); + out_be32(&fecp->fec_mii_data, + mk_mii_write(MII_ADVERTISE, + ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr)); + udelay(100); + + /* Disable FEC MII settings + */ + clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); + clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); + out_be32(&fecp->fec_mii_speed, 0); +} + +static int mpc885ads_platform_notify(struct device *dev) +{ + + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fec", + .rtn = mpc885ads_fixup_fec_enet_pdata, + }, + { + .bus_id = "fsl-cpm-scc", + .rtn = mpc885ads_fixup_scc_enet_pdata, + }, + { + .bus_id = NULL + } + }; + + platform_notify_map(dev_map,dev); + +} + +int __init mpc885ads_init(void) +{ + printk(KERN_NOTICE "mpc885ads: Init\n"); + + platform_notify = mpc885ads_platform_notify; + + ppc_sys_device_initfunc(); + ppc_sys_device_disable_all(); + + ppc_sys_device_enable(MPC8xx_CPM_FEC1); + +#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 + ppc_sys_device_enable(MPC8xx_CPM_SCC1); + +#endif +#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 + ppc_sys_device_enable(MPC8xx_CPM_FEC2); +#endif + + return 0; +} + +arch_initcall(mpc885ads_init); diff --git a/arch/ppc/platforms/mvme5100.c b/arch/ppc/platforms/mvme5100.c index 108eb182ddd..c717cd92c02 100644 --- a/arch/ppc/platforms/mvme5100.c +++ b/arch/ppc/platforms/mvme5100.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/mvme5100.c - * * Board setup routines for the Motorola MVME5100. * * Author: Matt Porter <mporter@mvista.com> diff --git a/arch/ppc/platforms/pal4.h b/arch/ppc/platforms/pal4.h index 641a11a3165..8569c423d88 100644 --- a/arch/ppc/platforms/pal4.h +++ b/arch/ppc/platforms/pal4.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4.h - * * Definitions for SBS Palomar IV board * * Author: Dan Cox diff --git a/arch/ppc/platforms/pal4_pci.c b/arch/ppc/platforms/pal4_pci.c index c3b1b757a48..d81ae1c7e1c 100644 --- a/arch/ppc/platforms/pal4_pci.c +++ b/arch/ppc/platforms/pal4_pci.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4_pci.c - * * PCI support for SBS Palomar IV * * Author: Dan Cox diff --git a/arch/ppc/platforms/pal4_serial.h b/arch/ppc/platforms/pal4_serial.h index a715c66e1ad..a75343224cf 100644 --- a/arch/ppc/platforms/pal4_serial.h +++ b/arch/ppc/platforms/pal4_serial.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4_serial.h - * * Definitions for SBS PalomarIV serial support * * Author: Dan Cox diff --git a/arch/ppc/platforms/pal4_setup.c b/arch/ppc/platforms/pal4_setup.c index f93a3f87193..3c3d881df00 100644 --- a/arch/ppc/platforms/pal4_setup.c +++ b/arch/ppc/platforms/pal4_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pal4_setup.c - * * Board setup routines for the SBS PalomarIV. * * Author: Dan Cox diff --git a/arch/ppc/platforms/powerpmc250.c b/arch/ppc/platforms/powerpmc250.c index e6b520e6e13..c3a86be11fb 100644 --- a/arch/ppc/platforms/powerpmc250.c +++ b/arch/ppc/platforms/powerpmc250.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/powerpmc250.c - * * Board setup routines for Force PowerPMC-250 Processor PMC * * Author: Troy Benjegerdes <tbenjegerdes@mvista.com> diff --git a/arch/ppc/platforms/pplus.c b/arch/ppc/platforms/pplus.c index 22bd40cfb09..de2761ebe0d 100644 --- a/arch/ppc/platforms/pplus.c +++ b/arch/ppc/platforms/pplus.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pplus.c - * * Board and PCI setup routines for MCG PowerPlus * * Author: Randy Vinson <rvinson@mvista.com> diff --git a/arch/ppc/platforms/pplus.h b/arch/ppc/platforms/pplus.h index 90f0cb2d409..a07cbbdd72c 100644 --- a/arch/ppc/platforms/pplus.h +++ b/arch/ppc/platforms/pplus.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pplus.h - * * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. * * Author: Mark A. Greerinclude/asm-ppc/hawk.h diff --git a/arch/ppc/platforms/pq2ads.c b/arch/ppc/platforms/pq2ads.c index 71c9fca1fe9..3365fd788a7 100644 --- a/arch/ppc/platforms/pq2ads.c +++ b/arch/ppc/platforms/pq2ads.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/pq2ads.c - * * PQ2ADS platform support * * Author: Kumar Gala <galak@kernel.crashing.org> diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h index 067d9a5aebc..6b26dd36c64 100644 --- a/arch/ppc/platforms/pq2ads.h +++ b/arch/ppc/platforms/pq2ads.h @@ -13,6 +13,10 @@ #include <asm/ppcboot.h> +#if defined(CONFIG_ADS8272) +#define BOARD_CHIP_NAME "8272" +#endif + /* Memory map is configured by the PROM startup. * We just map a few things we need. The CSR is actually 4 byte-wide * registers that can be accessed as 8-, 16-, or 32-bit values. diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h new file mode 100644 index 00000000000..8f14a43eafe --- /dev/null +++ b/arch/ppc/platforms/pq2ads_pd.h @@ -0,0 +1,114 @@ +#ifndef __PQ2ADS_PD_H +#define __PQ2ADS_PD_H +/* + * arch/ppc/platforms/82xx/pq2ads_pd.h + * + * Some defines for MPC82xx board-specific PlatformDevice descriptions + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* FCC1 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK9-12 */ + +#define F1_RXCLK 11 +#define F1_TXCLK 10 + +/* FCC2 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK13-16 */ +#define F2_RXCLK 15 +#define F2_TXCLK 16 + +/* FCC3 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK13-16 */ +#define F3_RXCLK 13 +#define F3_TXCLK 14 + +/* Automatically generates register configurations */ +#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ + +#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ +#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ +#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ +#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ +#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ +#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ + +#define PC_F1RXCLK PC_CLK(F1_RXCLK) +#define PC_F1TXCLK PC_CLK(F1_TXCLK) +#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) +#define CMX1_CLK_MASK ((uint)0xff000000) + +#define PC_F2RXCLK PC_CLK(F2_RXCLK) +#define PC_F2TXCLK PC_CLK(F2_TXCLK) +#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) +#define CMX2_CLK_MASK ((uint)0x00ff0000) + +#define PC_F3RXCLK PC_CLK(F3_RXCLK) +#define PC_F3TXCLK PC_CLK(F3_TXCLK) +#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) +#define CMX3_CLK_MASK ((uint)0x0000ff00) + +/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PA1_COL 0x00000001U +#define PA1_CRS 0x00000002U +#define PA1_TXER 0x00000004U +#define PA1_TXEN 0x00000008U +#define PA1_RXDV 0x00000010U +#define PA1_RXER 0x00000020U +#define PA1_TXDAT 0x00003c00U +#define PA1_RXDAT 0x0003c000U +#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) +#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ + PA1_RXDV | PA1_RXER) +#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) +#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) + + +/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB2_TXER 0x00000001U +#define PB2_RXDV 0x00000002U +#define PB2_TXEN 0x00000004U +#define PB2_RXER 0x00000008U +#define PB2_COL 0x00000010U +#define PB2_CRS 0x00000020U +#define PB2_TXDAT 0x000003c0U +#define PB2_RXDAT 0x00003c00U +#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ + PB2_RXER | PB2_RXDV | PB2_TXER) +#define PB2_PSORB1 (PB2_TXEN) +#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) +#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) + + +/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB3_RXDV 0x00004000U +#define PB3_RXER 0x00008000U +#define PB3_TXER 0x00010000U +#define PB3_TXEN 0x00020000U +#define PB3_COL 0x00040000U +#define PB3_CRS 0x00080000U +#define PB3_TXDAT 0x0f000000U +#define PB3_RXDAT 0x00f00000U +#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ + PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) +#define PB3_PSORB1 0 +#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) +#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) + +#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) +#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) +#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) + +#endif diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c index d0653580200..e86f6156d58 100644 --- a/arch/ppc/platforms/prep_setup.c +++ b/arch/ppc/platforms/prep_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/setup.c - * * Copyright (C) 1995 Linus Torvalds * Adapted from 'alpha' version by Gary Thomas * Modified by Cort Dougan (cort@cs.nmt.edu) @@ -738,7 +736,7 @@ ibm_statusled_progress(char *s, unsigned short hex) hex = 0xfff; if (!notifier_installed) { ++notifier_installed; - notifier_chain_register(&panic_notifier_list, + atomic_notifier_chain_register(&panic_notifier_list, &ibm_statusled_block); } } @@ -1069,15 +1067,13 @@ prep_map_io(void) static int __init prep_request_io(void) { - if (_machine == _MACH_prep) { #ifdef CONFIG_NVRAM - request_region(PREP_NVRAM_AS0, 0x8, "nvram"); + request_region(PREP_NVRAM_AS0, 0x8, "nvram"); #endif - request_region(0x00,0x20,"dma1"); - request_region(0x40,0x20,"timer"); - request_region(0x80,0x10,"dma page reg"); - request_region(0xc0,0x20,"dma2"); - } + request_region(0x00,0x20,"dma1"); + request_region(0x40,0x20,"timer"); + request_region(0x80,0x10,"dma page reg"); + request_region(0xc0,0x20,"dma2"); return 0; } diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c index 0bb14a5e824..cdd9cfb13ee 100644 --- a/arch/ppc/platforms/prpmc750.c +++ b/arch/ppc/platforms/prpmc750.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/prpmc750_setup.c - * * Board setup routines for Motorola PrPMC750 * * Author: Matt Porter <mporter@mvista.com> diff --git a/arch/ppc/platforms/prpmc800.c b/arch/ppc/platforms/prpmc800.c index de7baefacd3..e459a199fb1 100644 --- a/arch/ppc/platforms/prpmc800.c +++ b/arch/ppc/platforms/prpmc800.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/prpmc800.c - * * Author: Dale Farnsworth <dale.farnsworth@mvista.com> * * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 872c0a3ba3c..bc26b6d71c1 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/radstone_ppc7d.c - * * Board setup routines for the Radstone PPC7D boards. * * Author: James Chapman <jchapman@katalix.com> @@ -685,11 +683,10 @@ ppc7d_fixup_i2c_pdata(struct platform_device *pdev) pdata = pdev->dev.platform_data; if (pdata == NULL) { - pdata = kmalloc(sizeof(*pdata), GFP_KERNEL); + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); if (pdata == NULL) return; - memset(pdata, 0, sizeof(*pdata)); pdev->dev.platform_data = pdata; } @@ -712,7 +709,7 @@ ppc7d_fixup_i2c_pdata(struct platform_device *pdev) } #endif -static int __init ppc7d_platform_notify(struct device *dev) +static int ppc7d_platform_notify(struct device *dev) { static struct { char *bus_id; diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h index 938375510be..2bb093a0c03 100644 --- a/arch/ppc/platforms/radstone_ppc7d.h +++ b/arch/ppc/platforms/radstone_ppc7d.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/radstone_ppc7d.h - * * Board definitions for the Radstone PPC7D boards. * * Author: James Chapman <jchapman@katalix.com> diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c index 9eeed357230..6dc459decb2 100644 --- a/arch/ppc/platforms/sandpoint.c +++ b/arch/ppc/platforms/sandpoint.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sandpoint_setup.c - * * Board setup routines for the Motorola SPS Sandpoint Test Platform. * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/sandpoint.h b/arch/ppc/platforms/sandpoint.h index f4e982cb69d..3b64e641848 100644 --- a/arch/ppc/platforms/sandpoint.h +++ b/arch/ppc/platforms/sandpoint.h @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sandpoint.h - * * Definitions for Motorola SPS Sandpoint Test Platform * * Author: Mark A. Greer diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c index 74c9ff72c3d..866807b4ad0 100644 --- a/arch/ppc/platforms/sbc82xx.c +++ b/arch/ppc/platforms/sbc82xx.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/sbc82xx.c - * * SBC82XX platform support * * Author: Guy Streeter <streeter@redhat.com> diff --git a/arch/ppc/platforms/spruce.c b/arch/ppc/platforms/spruce.c index 69e1de7971f..3783deccd9b 100644 --- a/arch/ppc/platforms/spruce.c +++ b/arch/ppc/platforms/spruce.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/spruce.c - * * Board and PCI setup routines for IBM Spruce * * Author: MontaVista Software <source@mvista.com> diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c index 3409139330b..b766339f44a 100644 --- a/arch/ppc/platforms/tqm8260_setup.c +++ b/arch/ppc/platforms/tqm8260_setup.c @@ -1,6 +1,4 @@ /* - * arch/ppc/platforms/tqm8260_setup.c - * * TQM8260 platform support * * Author: Allen Curtis <acurtis@onz.com> |