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authorThomas Gleixner <tglx@linutronix.de>2011-05-14 12:06:36 +0200
committerThomas Gleixner <tglx@linutronix.de>2011-05-14 12:06:36 +0200
commita18f22a968de17b29f2310cdb7ba69163e65ec15 (patch)
treea7d56d88fad5e444d7661484109758a2f436129e /arch/s390/kernel/time.c
parenta1c57e0fec53defe745e64417eacdbd3618c3e66 (diff)
parent798778b8653f64b7b2162ac70eca10367cff6ce8 (diff)
Merge branch 'consolidate-clksrc-i8253' of master.kernel.org:~rmk/linux-2.6-arm into timers/clocksource
Conflicts: arch/ia64/kernel/cyclone.c arch/mips/kernel/i8253.c arch/x86/kernel/i8253.c Reason: Resolve conflicts so further cleanups do not conflict further Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/s390/kernel/time.c')
-rw-r--r--arch/s390/kernel/time.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 9e7b039458d..87be655557a 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -724,7 +724,7 @@ static void clock_sync_cpu(struct clock_sync_data *sync)
}
/*
- * Sync the TOD clock using the port refered to by aibp. This port
+ * Sync the TOD clock using the port referred to by aibp. This port
* has to be enabled and the other port has to be disabled. The
* last eacr update has to be more than 1.6 seconds in the past.
*/
@@ -1012,7 +1012,7 @@ static void etr_work_fn(struct work_struct *work)
eacr = etr_handle_update(&aib, eacr);
/*
- * Select ports to enable. The prefered synchronization mode is PPS.
+ * Select ports to enable. The preferred synchronization mode is PPS.
* If a port can be enabled depends on a number of things:
* 1) The port needs to be online and uptodate. A port is not
* disabled just because it is not uptodate, but it is only
@@ -1091,7 +1091,7 @@ static void etr_work_fn(struct work_struct *work)
/*
* Update eacr and try to synchronize the clock. If the update
* of eacr caused a stepping port switch (or if we have to
- * assume that a stepping port switch has occured) or the
+ * assume that a stepping port switch has occurred) or the
* clock syncing failed, reset the sync check control bit
* and set up a timer to try again after 0.5 seconds
*/