diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2010-01-13 19:11:14 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-01-13 19:11:14 +0900 |
| commit | 782bb5a532f883540bf403afb19f735a4eefd95b (patch) | |
| tree | c2eec8aff6797fda269d4f1c3d4ed19ff1d584d7 /arch/sh/include/asm/pgtable_pmd.h | |
| parent | 206582c3161f165f5bf49ececa962c5f95fdf0a3 (diff) | |
sh: default to extended TLB support.
All SH-X2 and SH-X3 parts support an extended TLB mode, which has been
left as experimental since support was originally merged. Now that it's
had some time to stabilize and get some exposure to various platforms,
we can drop it as an option and default enable it across the board.
This is also good future proofing for newer parts that will drop support
for the legacy TLB mode completely.
This will also force 3-level page tables for all newer parts, which is
necessary both for the varying page sizes and larger memories.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/asm/pgtable_pmd.h')
| -rw-r--r-- | arch/sh/include/asm/pgtable_pmd.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/sh/include/asm/pgtable_pmd.h b/arch/sh/include/asm/pgtable_pmd.h index 42a180e534a..587b05e1d04 100644 --- a/arch/sh/include/asm/pgtable_pmd.h +++ b/arch/sh/include/asm/pgtable_pmd.h @@ -7,11 +7,12 @@ * Some cores need a 3-level page table layout, for example when using * 64-bit PTEs and 4K pages. */ +#define PAGETABLE_LEVELS 3 -#define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */ +#define PTE_MAGNITUDE 3 /* 64-bit PTEs on SH-X2 TLB */ /* PGD bits */ -#define PGDIR_SHIFT 30 +#define PGDIR_SHIFT 30 #define PTRS_PER_PGD 4 #define USER_PTRS_PER_PGD 2 |