diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2006-12-25 10:19:56 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-13 10:54:45 +0900 |
| commit | 11c1965687b0a472add948d4240dfe65a2fcb298 (patch) | |
| tree | 69a71a34591bbdc6339dbe72de36819479f96198 /arch/sh/kernel/cpu/sh2a | |
| parent | aec5e0e1c179fac4bbca4007a3f0d3107275a73c (diff) | |
sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh2a')
| -rw-r--r-- | arch/sh/kernel/cpu/sh2a/probe.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 87c6c054208..426f6db01fc 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -17,14 +17,14 @@ int __init detect_cpu_and_cache_system(void) { /* Just SH7206 for now .. */ - cpu_data->type = CPU_SH7206; + current_cpu_data.type = CPU_SH7206; - cpu_data->dcache.ways = 4; - cpu_data->dcache.way_incr = (1 << 11); - cpu_data->dcache.sets = 128; - cpu_data->dcache.entry_shift = 4; - cpu_data->dcache.linesz = L1_CACHE_BYTES; - cpu_data->dcache.flags = 0; + current_cpu_data.dcache.ways = 4; + current_cpu_data.dcache.way_incr = (1 << 11); + current_cpu_data.dcache.sets = 128; + current_cpu_data.dcache.entry_shift = 4; + current_cpu_data.dcache.linesz = L1_CACHE_BYTES; + current_cpu_data.dcache.flags = 0; /* * The icache is the same as the dcache as far as this setup is @@ -32,7 +32,7 @@ int __init detect_cpu_and_cache_system(void) * lacks the U bit that the dcache has, none of this has any bearing * on the cache info. */ - cpu_data->icache = cpu_data->dcache; + current_cpu_data.icache = current_cpu_data.dcache; return 0; } |