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| author | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:36:55 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:36:55 +0200 |
| commit | bc588df79ebfb710abc27342fccf336a68ed1216 (patch) | |
| tree | e50e125eaa6da83fa715704e53c1bde013d1ef8e /arch/sparc/include/asm/dcr.h | |
| parent | bce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff) | |
| parent | 15dd859cacf312f606f54502d1f66537a1e5c78c (diff) | |
Merge branch 'x86/core' into x86/xsave
Diffstat (limited to 'arch/sparc/include/asm/dcr.h')
| -rw-r--r-- | arch/sparc/include/asm/dcr.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/dcr.h b/arch/sparc/include/asm/dcr.h new file mode 100644 index 00000000000..620c9ba642e --- /dev/null +++ b/arch/sparc/include/asm/dcr.h @@ -0,0 +1,14 @@ +#ifndef _SPARC64_DCR_H +#define _SPARC64_DCR_H + +/* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */ +#define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */ +#define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */ +#define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */ +#define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */ +#define DCR_SI 0x0000000000000008 /* Single Instruction Disable */ +#define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */ +#define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */ +#define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */ + +#endif /* _SPARC64_DCR_H */ |