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authorIngo Molnar <mingo@elte.hu>2008-07-30 19:36:55 +0200
committerIngo Molnar <mingo@elte.hu>2008-07-30 19:36:55 +0200
commitbc588df79ebfb710abc27342fccf336a68ed1216 (patch)
treee50e125eaa6da83fa715704e53c1bde013d1ef8e /arch/sparc/include/asm/lsu.h
parentbce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff)
parent15dd859cacf312f606f54502d1f66537a1e5c78c (diff)
Merge branch 'x86/core' into x86/xsave
Diffstat (limited to 'arch/sparc/include/asm/lsu.h')
-rw-r--r--arch/sparc/include/asm/lsu.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/lsu.h b/arch/sparc/include/asm/lsu.h
new file mode 100644
index 00000000000..7190f8de90a
--- /dev/null
+++ b/arch/sparc/include/asm/lsu.h
@@ -0,0 +1,19 @@
+#ifndef _SPARC64_LSU_H
+#define _SPARC64_LSU_H
+
+#include <linux/const.h>
+
+/* LSU Control Register */
+#define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
+#define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
+#define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
+#define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
+#define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
+#define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
+#define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
+#define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
+#define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
+#define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable. */
+#define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
+
+#endif /* !(_SPARC64_LSU_H) */