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authorJaroslav Kysela <perex@perex.cz>2010-02-16 11:19:18 +0100
committerJaroslav Kysela <perex@perex.cz>2010-02-16 11:19:18 +0100
commitba9341dfef6b0201cd30e3904dcd0a47d3dc35e0 (patch)
treed83637979db83bb9d5a23e190148b90b60c976d2 /arch/sparc/kernel/perf_event.c
parentd39e82db73eb876c60d00f00219d767b3be30307 (diff)
parentf167e1d073278fe231bbdd5d6c24fb9d091aa544 (diff)
Merge branch 'fixes' into devel
Diffstat (limited to 'arch/sparc/kernel/perf_event.c')
-rw-r--r--arch/sparc/kernel/perf_event.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index fa5936e1c3b..198fb4e79ba 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
data.addr = 0;
cpuc = &__get_cpu_var(cpu_hw_events);
+
+ /* If the PMU has the TOE IRQ enable bits, we need to do a
+ * dummy write to the %pcr to clear the overflow bits and thus
+ * the interrupt.
+ *
+ * Do this before we peek at the counters to determine
+ * overflow so we don't lose any events.
+ */
+ if (sparc_pmu->irq_bit)
+ pcr_ops->write(cpuc->pcr);
+
for (idx = 0; idx < MAX_HWEVENTS; idx++) {
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;