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| author | Grant Likely <grant.likely@secretlab.ca> | 2012-07-24 22:31:09 -0600 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2012-07-24 22:34:40 -0600 |
| commit | 6aeea3ecc33b1f36dbc3b80461d15a7052ae424f (patch) | |
| tree | bbd273e3e0ca76094aed8e9c77e5adfe2b07f779 /arch/tile/include/asm/cache.h | |
| parent | 9844a5524ec532aee826c35e3031637c7fc8287b (diff) | |
| parent | bdc0077af574800d24318b6945cf2344e8dbb050 (diff) | |
Merge remote-tracking branch 'origin' into irqdomain/next
Diffstat (limited to 'arch/tile/include/asm/cache.h')
| -rw-r--r-- | arch/tile/include/asm/cache.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index 392e5333dd8..a9a529964e0 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -27,11 +27,17 @@ #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) /* - * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN. + * TILEPro I/O is not always coherent (networking typically uses coherent + * I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the + * L2 cacheline size helps ensure that kernel heap allocations are aligned. + * TILE-Gx I/O is always coherent when used on hash-for-home pages. + * + * However, it's possible at runtime to request not to use hash-for-home + * for the kernel heap, in which case the kernel will use flush-and-inval + * to manage coherence. As a result, we use L2_CACHE_BYTES for the + * DMA minimum alignment to avoid false sharing in the kernel heap. */ -#ifndef __tilegx__ #define ARCH_DMA_MINALIGN L2_CACHE_BYTES -#endif /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT |