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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-09-03 09:26:33 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-09-03 09:26:33 +0300 |
| commit | c50e86ce7c2961a41f2f7aa6e4fd6c99229ba205 (patch) | |
| tree | 4ea36009719bd8fc523239fe1bdccb90f0dce3ae /arch/tile/include/asm/cache.h | |
| parent | 14d33d384693eb6083396199de516fdef320f7af (diff) | |
| parent | 4cbe5a555fa58a79b6ecbb6c531b8bab0650778d (diff) | |
Merge tag 'v3.6-rc4'
Merge 3.6-rc4 to get latest OMAP and device tree fixes.
Diffstat (limited to 'arch/tile/include/asm/cache.h')
| -rw-r--r-- | arch/tile/include/asm/cache.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index 392e5333dd8..a9a529964e0 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -27,11 +27,17 @@ #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) /* - * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN. + * TILEPro I/O is not always coherent (networking typically uses coherent + * I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the + * L2 cacheline size helps ensure that kernel heap allocations are aligned. + * TILE-Gx I/O is always coherent when used on hash-for-home pages. + * + * However, it's possible at runtime to request not to use hash-for-home + * for the kernel heap, in which case the kernel will use flush-and-inval + * to manage coherence. As a result, we use L2_CACHE_BYTES for the + * DMA minimum alignment to avoid false sharing in the kernel heap. */ -#ifndef __tilegx__ #define ARCH_DMA_MINALIGN L2_CACHE_BYTES -#endif /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT |