diff options
| author | Andi Kleen <ak@linux.intel.com> | 2011-03-03 10:34:48 +0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-03-04 11:32:53 +0100 |
| commit | e994d7d23a0bae34cd28834e85522ed4e782faf7 (patch) | |
| tree | f9b08a69bdccf047cba9449adee4dd86ed1e8892 /arch/x86/include/asm/smp.h | |
| parent | a7e3ed1e470116c9d12c2f778431a481a6be8ab6 (diff) | |
perf: Fix LLC-* events on Intel Nehalem/Westmere
On Intel Nehalem and Westmere CPUs the generic perf LLC-* events count the
L2 caches, not the real L3 LLC - this was inconsistent with behavior on
other CPUs.
Fixing this requires the use of the special OFFCORE_RESPONSE
events which need a separate mask register.
This has been implemented by the previous patch, now use this infrastructure
to set correct events for the LLC-* on Nehalem and Westmere.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1299119690-13991-3-git-send-email-ming.m.lin@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/smp.h')
0 files changed, 0 insertions, 0 deletions