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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-09 18:11:28 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-09 18:11:28 -0800
commita8f76842142890883f46b8e7f57f87cf224a832a (patch)
treebbc829912f06fc6693d5e8bed29c4afbd14a6ce5 /arch/x86/include/asm
parentc93ecedab35f5305542a9fe5cfbd37377189589e (diff)
parent0e1540208ef34a2246822fa56f751efe23748e7a (diff)
Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 SoC updates from Ingo Molnar: "Various Intel Atom SoC updates (mostly to enhance debuggability), plus an apb_timer cleanup" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: pmc_atom: Expose contents of PSS x86: pmc_atom: Clean up init function x86: pmc-atom: Remove unused macro x86: pmc_atom: don%27t check for NULL twice x86: pmc-atom: Assign debugfs node as soon as possible x86/platform: Remove unused function from apb_timer.c
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r--arch/x86/include/asm/pmc_atom.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index fc7a17c05d3..bc0fc086655 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -53,6 +53,28 @@
/* Sleep state counter is in units of of 32us */
#define PMC_TMR_SHIFT 5
+/* Power status of power islands */
+#define PMC_PSS 0x98
+
+#define PMC_PSS_BIT_GBE BIT(0)
+#define PMC_PSS_BIT_SATA BIT(1)
+#define PMC_PSS_BIT_HDA BIT(2)
+#define PMC_PSS_BIT_SEC BIT(3)
+#define PMC_PSS_BIT_PCIE BIT(4)
+#define PMC_PSS_BIT_LPSS BIT(5)
+#define PMC_PSS_BIT_LPE BIT(6)
+#define PMC_PSS_BIT_DFX BIT(7)
+#define PMC_PSS_BIT_USH_CTRL BIT(8)
+#define PMC_PSS_BIT_USH_SUS BIT(9)
+#define PMC_PSS_BIT_USH_VCCS BIT(10)
+#define PMC_PSS_BIT_USH_VCCA BIT(11)
+#define PMC_PSS_BIT_OTG_CTRL BIT(12)
+#define PMC_PSS_BIT_OTG_VCCS BIT(13)
+#define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14)
+#define PMC_PSS_BIT_OTG_VCCA BIT(15)
+#define PMC_PSS_BIT_USB BIT(16)
+#define PMC_PSS_BIT_USB_SUS BIT(17)
+
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0