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authorOlof Johansson <olof@lixom.net>2013-08-11 15:33:54 -0700
committerOlof Johansson <olof@lixom.net>2013-08-11 15:33:54 -0700
commit4ddbed9618724d52a7a79c1e10ef5adb46fcccf7 (patch)
treeffe64efb333d7dcdb5b2cf43ffef97b25261702c /arch/x86/kernel/acpi/sleep.c
parent16649596d701c0f4f767bbcad7da4d6343ba8a9e (diff)
parentfa8c5a811e0e7c3e1c49b2e58fcb4db549b5719a (diff)
Merge tag 'boards-3.12' of git://git.infradead.org/linux-mvebu into next/boards
From Jason Cooper: mvebu boards changes for v3.12 - convert kirkwood, dove, orion5x to DT init of mv643xx_eth - _lots_ of board code removal :) - convert kirkwood, dove and orion5x to DT init of clocksource and irqchip * tag 'boards-3.12' of git://git.infradead.org/linux-mvebu: ARM: plat-orion: add reg offset to DT irq driver stub ARM: kirkwood: remove obsolete SDIO clock gate workaround ARM: kirkwood: convert to DT irqchip and clocksource ARM: dove: convert to DT irqchip and clocksource ARM: orion5x: update intc device tree node to new reg layout ARM: kirkwood: move device tree nodes to DT irqchip and clocksource ARM: dove: move device tree nodes to DT irqchip and clocksource ARM: orion5x: remove legacy mv643xx_eth board setup ARM: kirkwood: remove legacy clk alias for mv643xx_eth ARM: kirkwood: remove redundant DT board files ARM: dove: remove legacy mv643xx_eth setup ARM: orion5x: add gigabit ethernet and mvmdio device tree nodes ARM: kirkwood: add gigabit ethernet and mvmdio device tree nodes ARM: dove: add gigabit ethernet and mvmdio device tree nodes + Linux 3.11-rc2 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/x86/kernel/acpi/sleep.c')
-rw-r--r--arch/x86/kernel/acpi/sleep.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 2a34aaf3c8f..33120100ff5 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -48,9 +48,20 @@ int x86_acpi_suspend_lowlevel(void)
#ifndef CONFIG_64BIT
native_store_gdt((struct desc_ptr *)&header->pmode_gdt);
+ /*
+ * We have to check that we can write back the value, and not
+ * just read it. At least on 90 nm Pentium M (Family 6, Model
+ * 13), reading an invalid MSR is not guaranteed to trap, see
+ * Erratum X4 in "Intel Pentium M Processor on 90 nm Process
+ * with 2-MB L2 Cache and IntelĀ® Processor A100 and A110 on 90
+ * nm process with 512-KB L2 Cache Specification Update".
+ */
if (!rdmsr_safe(MSR_EFER,
&header->pmode_efer_low,
- &header->pmode_efer_high))
+ &header->pmode_efer_high) &&
+ !wrmsr_safe(MSR_EFER,
+ header->pmode_efer_low,
+ header->pmode_efer_high))
header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
#endif /* !CONFIG_64BIT */
@@ -61,7 +72,10 @@ int x86_acpi_suspend_lowlevel(void)
}
if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
&header->pmode_misc_en_low,
- &header->pmode_misc_en_high))
+ &header->pmode_misc_en_high) &&
+ !wrmsr_safe(MSR_IA32_MISC_ENABLE,
+ header->pmode_misc_en_low,
+ header->pmode_misc_en_high))
header->pmode_behavior |=
(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
header->realmode_flags = acpi_realmode_flags;