diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:36:55 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:36:55 +0200 |
commit | bc588df79ebfb710abc27342fccf336a68ed1216 (patch) | |
tree | e50e125eaa6da83fa715704e53c1bde013d1ef8e /arch/x86/kernel/cpu/intel.c | |
parent | bce7f793daec3e65ec5c5705d2457b81fe7b5725 (diff) | |
parent | 15dd859cacf312f606f54502d1f66537a1e5c78c (diff) |
Merge branch 'x86/core' into x86/xsave
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r-- | arch/x86/kernel/cpu/intel.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index fe9224c51d3..b75f2569b8f 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -226,6 +226,20 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) if (cpu_has_bts) ds_init_intel(c); + + /* + * See if we have a good local APIC by checking for buggy Pentia, + * i.e. all B steppings and the C2 stepping of P54C when using their + * integrated APIC (see 11AP erratum in "Pentium Processor + * Specification Update"). + */ + if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && + (c->x86_mask < 0x6 || c->x86_mask == 0xb)) + set_cpu_cap(c, X86_FEATURE_11AP); + +#ifdef CONFIG_X86_NUMAQ + numaq_tsc_disable(); +#endif } static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |