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authorArnd Bergmann <arnd@arndb.de>2012-05-11 17:15:31 +0200
committerArnd Bergmann <arnd@arndb.de>2012-05-11 17:15:31 +0200
commit93c6d8927fa692faef3d7d945bd4fe84b0185ad4 (patch)
tree0a971c86114656ec4e39f7789d9faeb70432c36a /arch/x86/kernel/cpu/intel_cacheinfo.c
parentea01d31a07ae182028d2398380948f5a4ee09953 (diff)
parent50260924afd4b745bfb6e5f1caee381a1875fc31 (diff)
Merge branch 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/clock
Shawn Guo <shawn.guo@linaro.org> writes: mxs common clk porting for v3.5. It depends on the following two branches. [1] git://git.linaro.org/people/mturquette/linux.git clk-next [2] http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-arm.git clkdev As the mxs device tree conversion will constantly touch clock files, to save the conflicts, the updated mxs/dt branch coming later will based on this pull-request. * 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs: remove now unused timer_clk argument from mxs_timer_init ARM: mxs: remove old clock support ARM: mxs: switch to common clk framework ARM: mxs: change the lookup name for fec phy clock ARM: mxs: request clock for timer clk: mxs: add clock support for imx28 clk: mxs: add clock support for imx23 clk: mxs: add mxs specific clocks Includes an update to Linux 3.4-rc6 Conflicts: drivers/clk/Makefile Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/x86/kernel/cpu/intel_cacheinfo.c')
-rw-r--r--arch/x86/kernel/cpu/intel_cacheinfo.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed98a6..b8f3653dddb 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
/* check if @slot is already used or the index is already disabled */
ret = amd_get_l3_disable_slot(nb, slot);
if (ret >= 0)
- return -EINVAL;
+ return -EEXIST;
if (index > nb->l3_cache.indices)
return -EINVAL;
/* check whether the other slot has disabled the same index already */
if (index == amd_get_l3_disable_slot(nb, !slot))
- return -EINVAL;
+ return -EEXIST;
amd_l3_disable_index(nb, cpu, slot, index);
@@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
if (err) {
if (err == -EEXIST)
- printk(KERN_WARNING "L3 disable slot %d in use!\n",
- slot);
+ pr_warning("L3 slot %d in use/index already disabled!\n",
+ slot);
return err;
}
return count;