diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-07 10:17:56 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-07 10:17:56 +0200 |
| commit | f1615bbe9be4def59c3b3eaddb60722efeed16c2 (patch) | |
| tree | ca3020e65447576fc1826e819651e6ba072030b5 /drivers/cpufreq/exynos-cpufreq.h | |
| parent | cfb3c0ab0903abb6ea5215b37eebd9c2a1f057eb (diff) | |
| parent | cd3de83f147601356395b57a8673e9c5ff1e59d1 (diff) | |
Merge tag 'v3.16-rc4' into drm-intel-next-queued
Due to Dave's vacation drm-next hasn't opened yet for 3.17 so I
couldn't move my drm-intel-next queue forward yet like I usually do.
Just pull in the latest upstream -rc to unblock patch merging - I
don't want to needlessly rebase my current patch pile really and void
all the testing we've done already.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/cpufreq/exynos-cpufreq.h')
| -rw-r--r-- | drivers/cpufreq/exynos-cpufreq.h | 39 |
1 files changed, 23 insertions, 16 deletions
diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h index 3ddade8a512..9f2062a7cc0 100644 --- a/drivers/cpufreq/exynos-cpufreq.h +++ b/drivers/cpufreq/exynos-cpufreq.h @@ -17,6 +17,13 @@ enum cpufreq_level_index { L20, }; +enum exynos_soc_type { + EXYNOS_SOC_4210, + EXYNOS_SOC_4212, + EXYNOS_SOC_4412, + EXYNOS_SOC_5250, +}; + #define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \ { \ .freq = (f) * 1000, \ @@ -34,6 +41,8 @@ struct apll_freq { }; struct exynos_dvfs_info { + enum exynos_soc_type type; + struct device *dev; unsigned long mpll_freq_khz; unsigned int pll_safe_idx; struct clk *cpu_clk; @@ -41,6 +50,7 @@ struct exynos_dvfs_info { struct cpufreq_frequency_table *freq_table; void (*set_freq)(unsigned int, unsigned int); bool (*need_apll_change)(unsigned int, unsigned int); + void __iomem *cmu_regs; }; #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ @@ -68,24 +78,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) } #endif -#include <plat/cpu.h> -#include <mach/map.h> - -#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200) -#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400) +#define EXYNOS4_CLKSRC_CPU 0x14200 +#define EXYNOS4_CLKMUX_STATCPU 0x14400 -#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500) -#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504) -#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600) -#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604) +#define EXYNOS4_CLKDIV_CPU 0x14500 +#define EXYNOS4_CLKDIV_CPU1 0x14504 +#define EXYNOS4_CLKDIV_STATCPU 0x14600 +#define EXYNOS4_CLKDIV_STATCPU1 0x14604 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000) -#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100) -#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400) -#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500) -#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504) -#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600) -#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604) +#define EXYNOS5_APLL_LOCK 0x00000 +#define EXYNOS5_APLL_CON0 0x00100 +#define EXYNOS5_CLKMUX_STATCPU 0x00400 +#define EXYNOS5_CLKDIV_CPU0 0x00500 +#define EXYNOS5_CLKDIV_CPU1 0x00504 +#define EXYNOS5_CLKDIV_STATCPU0 0x00600 +#define EXYNOS5_CLKDIV_STATCPU1 0x00604 |