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authorMark A. Grondona <mgrondona@llnl.gov>2011-10-18 11:02:58 -0200
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-11-01 10:01:55 -0200
commitc6e13b528f5a6c6a6ae260007d4fd14c3dbc5648 (patch)
tree92703334e6ed7b715d55c304735358c41e288d41 /drivers/edac/sb_edac.c
parent3d78c9af78e080db1961fd30ede1720d6e6e5999 (diff)
EDAC: Fix incorrect edac mode reporting in sb_edac
The edac driver for Sandy Bridge was found to be reporting "FPM" for edac_mode, which clearly doesn't make sense. It was found that sb_edac.c:get_dimm_config was reusing a variable for both mem_type and edac_type, and thus was overwriting the value after setting it correctly. This patch fixes that issue. Before the patch: /sys/devices/system/edac/mc/mc0/csrow0/edac_mode:FPM /sys/devices/system/edac/mc/mc0/csrow1/edac_mode:FPM /sys/devices/system/edac/mc/mc0/csrow2/edac_mode:FPM /sys/devices/system/edac/mc/mc0/csrow3/edac_mode:FPM After: /sys/devices/system/edac/mc/mc0/csrow0/edac_mode:S4ECD4ED /sys/devices/system/edac/mc/mc0/csrow1/edac_mode:S4ECD4ED /sys/devices/system/edac/mc/mc0/csrow2/edac_mode:S4ECD4ED /sys/devices/system/edac/mc/mc0/csrow3/edac_mode:S4ECD4ED Signed-off-by: Mark A. Grondona <mgrondona@llnl.gov> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac/sb_edac.c')
-rw-r--r--drivers/edac/sb_edac.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 8118f12cb8c..7a402bfbee7 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -559,6 +559,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
unsigned long last_page = 0;
u32 reg;
enum edac_type mode;
+ enum mem_type mtype;
pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
pvt->sbridge_dev->source_id = SOURCE_ID(reg);
@@ -601,10 +602,10 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
if (IS_RDIMM_ENABLED(reg)) {
/* FIXME: Can also be LRDIMM */
debugf0("Memory is registered\n");
- mode = MEM_RDDR3;
+ mtype = MEM_RDDR3;
} else {
debugf0("Memory is unregistered\n");
- mode = MEM_DDR3;
+ mtype = MEM_DDR3;
}
/* On all supported DDR3 DIMM types, there are 8 banks available */
@@ -643,7 +644,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
csr->ce_count = 0;
csr->ue_count = 0;
- csr->mtype = mode;
+ csr->mtype = mtype;
csr->edac_mode = mode;
csr->nr_channels = 1;
csr->channels[0].chan_idx = i;