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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-06-28 02:04:25 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-08-08 17:43:33 +0200
commitaad3d14d25c33c8e510c41aaaf2668e8d32811ab (patch)
tree826cb4299754fd4cf3d8d9eb8475158f1a5ae470 /drivers/gpu/drm/i915/i915_reg.h
parenta5043453aa2412ece984373294529d177324c901 (diff)
drm/i915: Add DP training pattern 3 for CHV
CHV supports DP training pattern 3. Add the required stuff. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e01a1a0b961..e355fc8d4d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3489,6 +3489,8 @@ enum punit_power_well {
#define DP_LINK_TRAIN_OFF (3 << 28)
#define DP_LINK_TRAIN_MASK (3 << 28)
#define DP_LINK_TRAIN_SHIFT 28
+#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
+#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
/* CPT Link training mode */
#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)