diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2012-08-01 13:49:13 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2012-08-01 13:49:13 +0900 |
| commit | 91ba548cfd5cc8ee93b9435527efb8fa4caf5c5e (patch) | |
| tree | c96ed92413044a28d17783e84a8824bfd2437af1 /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | b9ccfda293ee6fca9a89a1584f0900e0627b975e (diff) | |
| parent | 4dc4c51675c137c30838425ecc8d471ff5eb138b (diff) | |
Merge branch 'sh/dmaengine' into sh-latest
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 46d1e886c69..933c7485917 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -170,6 +170,15 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) udelay(600); + /* We need to program FDI_RX_MISC with the default TP1 to TP2 + * values before enabling the receiver, and configure the delay + * for the FDI timing generator to 90h. Luckily, all the other + * bits are supposed to be zeroed, so we can write those values + * directly. + */ + I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | + FDI_RX_FDI_DELAY_90); + /* Enable CPU FDI Receiver with auto-training */ reg = FDI_RX_CTL(pipe); I915_WRITE(reg, @@ -726,8 +735,7 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, I915_WRITE(DDI_FUNC_CTL(pipe), temp); - intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); - intel_hdmi_set_spd_infoframe(encoder); + intel_hdmi->set_infoframes(encoder, adjusted_mode); } void intel_ddi_dpms(struct drm_encoder *encoder, int mode) |