diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-06-13 13:37:51 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-07 11:24:47 +0200 |
| commit | e37c67a1c5743ac7fc7f946290fee96f84248ca7 (patch) | |
| tree | 035478bcc66abf056bcea99cbf487852cf204c68 /drivers/gpu/drm/i915/intel_display.c | |
| parent | 29dc7ef3bbd3a78d35154f8b103b2f8a724f7986 (diff) | |
drm/i915: Use 200MHz cdclk on vlv when all pipes are off
Drop the cdclk frequency to 200MHz on vlv when all pipes are off. In
theory we should be able to use 200MHz also when the pixel clock is at
most 90% of 200MHz. However in practice all we seem to get is a solid
color picture or an otherwise corrupted display.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5940011bcd2..d127e76d81a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4556,14 +4556,19 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, * 400MHz * So we check to see whether we're above 90% of the lower bin and * adjust if needed. + * + * We seem to get an unstable or solid color picture at 200MHz. + * Not sure what's wrong. For now use 200MHz only when all pipes + * are off. */ if (max_pixclk > freq_320*9/10) return 400000; else if (max_pixclk > 266667*9/10) return freq_320; - else + else if (max_pixclk > 0) return 266667; - /* Looks like the 200MHz CDclk freq doesn't work on some configs */ + else + return 200000; } /* compute the max pixel clock for new configuration */ |