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authorDave Airlie <airlied@redhat.com>2014-03-18 19:06:53 +1000
committerDave Airlie <airlied@redhat.com>2014-03-18 19:06:53 +1000
commit8ad2bc9796994ecba9f4ba2fc9abca27ee9d193d (patch)
treeb36c83fa93da7f18c1331252fb82a87431697443 /drivers/gpu/drm/i915/intel_dsi.c
parente40d641099213145a034981e646dc2180a488152 (diff)
parente19b9137142988bec5a76c5f8bdf12a77ea802b0 (diff)
Merge branch 'drm-intel-next' of git://git.freedesktop.org/git/drm-intel into drm-next
- fine-grained display power domains for byt (Imre) - runtime pm prep patches for !hsw from Paulo - WiZ hashing flag updates from Ville - ppgtt setup cleanup and enabling of full 4G range on bdw (Ben) - fixes from Jesse for the inherited intial config code - gpu reset code improvements from Mika - per-pipe num_planes refactoring from Damien - stability fixes around bdw forcewake handling and other bdw w/a from Mika Ken - and as usual a pile of smaller fixes all over * 'drm-intel-next' of git://git.freedesktop.org/git/drm-intel: (107 commits) drm/i915: Go OCD on the Makefile drm/i915: Implement command buffer parsing logic drm/i915: Refactor shmem pread setup drm/i915: Avoid div by zero when pixel clock is large drm/i915: power domains: add vlv power wells drm/i915: factor out intel_set_cpu_fifo_underrun_reporting_nolock drm/i915: vlv: factor out valleyview_display_irq_install drm/i915: sanity check power well sw state against hw state drm/i915: factor out reset_vblank_counter drm/i915: sanitize PUNIT register macro definitions drm/i915: vlv: keep first level vblank IRQs masked drm/i915: check pipe power domain when reading its hw state drm/i915: check port power domain when reading the encoder hw state drm/i915: get port power domain in connector detect handlers drm/i915: add port power domains drm/i915: add noop power well handlers instead of NULL checking them drm/i915: split power well 'set' handler to separate enable/disable/sync_hw drm/i915: add init power domain to always-on power wells drm/i915: move power domain macros to intel_pm.c drm/i915: Disable full ppgtt by default ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dsi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3ee1db1407b..cf7322e9527 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -243,11 +243,16 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ enum intel_display_power_domain power_domain;
u32 port, func;
enum pipe p;
DRM_DEBUG_KMS("\n");
+ power_domain = intel_display_port_power_domain(encoder);
+ if (!intel_display_power_enabled(dev_priv, power_domain))
+ return false;
+
/* XXX: this only works for one DSI output */
for (p = PIPE_A; p <= PIPE_B; p++) {
port = I915_READ(MIPI_PORT_CTRL(p));
@@ -488,8 +493,19 @@ static enum drm_connector_status
intel_dsi_detect(struct drm_connector *connector, bool force)
{
struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
+ struct intel_encoder *intel_encoder = &intel_dsi->base;
+ enum intel_display_power_domain power_domain;
+ enum drm_connector_status connector_status;
+ struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
+
DRM_DEBUG_KMS("\n");
- return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
+ power_domain = intel_display_port_power_domain(intel_encoder);
+
+ intel_display_power_get(dev_priv, power_domain);
+ connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
+ intel_display_power_put(dev_priv, power_domain);
+
+ return connector_status;
}
static int intel_dsi_get_modes(struct drm_connector *connector)