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authorGajanan Bhat <gajanan.bhat@intel.com>2014-08-05 23:15:54 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-08-08 17:44:00 +0200
commita398e9c79eea74ba2f3f24ac08902661682f008c (patch)
tree43cb0ab75a3ea8947b4a50a380219223b93abb9b /drivers/gpu/drm/i915/intel_pm.c
parent0948c2651413d56c90d7ee9c99d75bef82d4c351 (diff)
drm/i915: Round-up clock and limit drain latency
Round up clock computation and limit drain latency to maximum of 0x7F. Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de27439636e..19bd7212f4a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1285,11 +1285,14 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
return false;
- entries = (clock / 1000) * pixel_size;
+ entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
*prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
DRAIN_LATENCY_PRECISION_32;
*drain_latency = (64 * (*prec_mult) * 4) / entries;
+ if (*drain_latency > DRAIN_LATENCY_MASK)
+ *drain_latency = DRAIN_LATENCY_MASK;
+
return true;
}