diff options
| author | Dave Airlie <airlied@gmail.com> | 2013-01-26 18:17:39 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2013-01-26 18:17:39 +1000 |
| commit | 483674325f64a37c7696edb12ce6ad3e535421bc (patch) | |
| tree | b9b334854ad4fa931b211f0f44a47e4d75d3c514 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | f0f21aa53a30fffd69899794da3a077960f27771 (diff) | |
| parent | 4518f611ba21ba165ea3714055938a8984a44ff9 (diff) | |
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel
Just a few small things:
- 2x workaround bits from Chris to fix up the new scanline waits enabled
in 3.8 on snb. People who've been struck by this on dual-screen also
need to upgrade the ddx.
- Dump the kernel version into i915_error_state, we've had a few mixups
there recently.
- Disable gfx DMAR on gen4 devices, acked by David Woodhouse.
* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
drm/i915: dump UTS_RELEASE into the error_state
iommu/intel: disable DMAR for g4x integrated gfx
drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
drm/i915: Disable AsyncFlip performance optimisations
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ae253e04c39..42ff97d667d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -505,13 +505,25 @@ static int init_render_ring(struct intel_ring_buffer *ring) struct drm_i915_private *dev_priv = dev->dev_private; int ret = init_ring_common(ring); - if (INTEL_INFO(dev)->gen > 3) { + if (INTEL_INFO(dev)->gen > 3) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); - if (IS_GEN7(dev)) - I915_WRITE(GFX_MODE_GEN7, - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | - _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); - } + + /* We need to disable the AsyncFlip performance optimisations in order + * to use MI_WAIT_FOR_EVENT within the CS. It should already be + * programmed to '1' on all products. + */ + if (INTEL_INFO(dev)->gen >= 6) + I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); + + /* Required for the hardware to program scanline values for waiting */ + if (INTEL_INFO(dev)->gen == 6) + I915_WRITE(GFX_MODE, + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); + + if (IS_GEN7(dev)) + I915_WRITE(GFX_MODE_GEN7, + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); if (INTEL_INFO(dev)->gen >= 5) { ret = init_pipe_control(ring); |