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authorLinus Torvalds <torvalds@linux-foundation.org>2011-02-15 15:25:33 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2011-02-15 15:25:33 -0800
commitb90be8662b1d7bd84637edb8f96e904f865a2fe2 (patch)
tree814e9fcace371347ded09bce56726ef31a55da25 /drivers/gpu/drm/i915/intel_ringbuffer.c
parentc612cc211d7f3ba4c4626d55166b3103d15efd76 (diff)
parent5b40ddf888398ce4cccbf3b9d0a18d90149ed7ff (diff)
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (27 commits) drm/radeon/kms: hopefully fix pll issues for real (v3) drm/radeon/kms: add bounds checking to avivo pll algo drm: fix wrong usages of drm_device in DRM Developer's Guide drm/radeon/kms: fix a few more atombios endian issues drm/radeon/kms: improve 6xx/7xx CS error output drm/radeon/kms: check AA resolve registers on r300 drm/radeon/kms: fix tracking of BLENDCNTL, COLOR_CHANNEL_MASK, and GB_Z on r300 drm/radeon/kms: use linear aligned for evergreen/ni bo blits drm/radeon/kms: use linear aligned for 6xx/7xx bo blits drm/radeon: fix race between GPU reset and TTM delayed delete thread. drm/radeon/kms: evergreen/ni big endian fixes (v2) drm/radeon/kms: 6xx/7xx big endian fixes drm/radeon/kms: atombios big endian fixes drm/radeon: 6xx/7xx non-kms endian fixes drm/radeon/kms: optimize CS state checking for r100->r500 drm: do not leak kernel addresses via /proc/dri/*/vma drm/radeon/kms: add connector table for mac g5 9600 radeon mkregtable: Add missing fclose() calls drm/radeon/kms: fix interlaced modes on dce4+ drm/radeon: fix memory debugging since d961db75ce86a84f1f04e91ad1014653ed7d9f46 ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c26
1 files changed, 16 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6218fa97aa1..445f27efe67 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1059,22 +1059,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
}
static int gen6_ring_flush(struct intel_ring_buffer *ring,
- u32 invalidate_domains,
- u32 flush_domains)
+ u32 invalidate, u32 flush)
{
+ uint32_t cmd;
int ret;
- if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
+ if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0)
return 0;
ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
- intel_ring_emit(ring, MI_FLUSH_DW);
- intel_ring_emit(ring, 0);
+ cmd = MI_FLUSH_DW;
+ if (invalidate & I915_GEM_GPU_DOMAINS)
+ cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
+ intel_ring_emit(ring, cmd);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
}
@@ -1230,22 +1233,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring,
}
static int blt_ring_flush(struct intel_ring_buffer *ring,
- u32 invalidate_domains,
- u32 flush_domains)
+ u32 invalidate, u32 flush)
{
+ uint32_t cmd;
int ret;
- if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
+ if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0)
return 0;
ret = blt_ring_begin(ring, 4);
if (ret)
return ret;
- intel_ring_emit(ring, MI_FLUSH_DW);
- intel_ring_emit(ring, 0);
+ cmd = MI_FLUSH_DW;
+ if (invalidate & I915_GEM_DOMAIN_RENDER)
+ cmd |= MI_INVALIDATE_TLB;
+ intel_ring_emit(ring, cmd);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return 0;
}