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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-02-10 10:26:38 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-02-10 10:26:38 +0000 |
| commit | df9ab9771c64f5229843bfe2a20fe0ee6ac59fc1 (patch) | |
| tree | a091be1024bd76627f78e791e377126e47703b7b /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | ed8f8ce38d0f7b505d7da2d79522972e962457c2 (diff) | |
| parent | 4e1c0664de11e4b5861957ab4ddff2aeeffd042f (diff) | |
Merge branch 'devel-stable' into for-next
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9f445e9a75d..c7bc93d28d8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -362,12 +362,15 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; /* * TLB invalidate requires a post-sync write. */ flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; + /* Workaround: we must issue a pipe_control with CS-stall bit * set before a pipe_control command that has the state cache * invalidate bit set. */ |