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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-07 11:05:45 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-08 18:10:13 +0100
commit7167d7c677ef066c56df276dc35b044c4840151a (patch)
tree0b60984efaa0f482ef74b8f486c4491dd0adc41e /drivers/gpu/drm/i915
parent0fbe7870d7e97d6fa595652a8f8eaf159e4bb6c9 (diff)
drm/i915: Optimize gen8_enable|disable_vblank functions
Let's cache the IMR value like on other platforms. This is needed to implement the underrun reporting since then we'll have two places that change the same register at runtime. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c18
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a06de99ed3f..9ea0df2c710 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2203,17 +2203,14 @@ static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long irqflags;
- uint32_t imr;
if (!i915_pipe_enabled(dev, pipe))
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
- if ((imr & GEN8_PIPE_VBLANK) == 1) {
- I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr & ~GEN8_PIPE_VBLANK);
- POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
- }
+ dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
+ I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+ POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
return 0;
}
@@ -2270,17 +2267,14 @@ static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long irqflags;
- uint32_t imr;
if (!i915_pipe_enabled(dev, pipe))
return;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
- if ((imr & GEN8_PIPE_VBLANK) == 0) {
- I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr | GEN8_PIPE_VBLANK);
- POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
- }
+ dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
+ I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+ POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}