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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-06 12:52:06 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-08 22:04:38 +0200 |
| commit | 5d536e2858ead64ea945552ec6a491f968c55888 (patch) | |
| tree | 4f903dae6e0869623aa9a1f857f688c2a5de58bb /drivers/gpu/drm/omapdrm/omap_fb.c | |
| parent | 4a33e48d0e121953342194b45d33dc752353d62b (diff) | |
drm/i915: dvo needs a P2 divisor of 4
Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23
"FPA0/A1 P2 Clock Divide":
0 = Divide by 2
1 = Divide by 4. This bit must be set in DVO non-gang mode
So copy the current limits (which should be good for i8xx) and create
a new set for dvo encoders.
Reviewed-by: Chris Wilson <chris@chris-wilson.oc.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/omap_fb.c')
0 files changed, 0 insertions, 0 deletions