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authorMichel Dänzer <michel.daenzer@amd.com>2014-07-17 19:01:08 +0900
committerAlex Deucher <alexander.deucher@amd.com>2014-08-05 08:53:33 -0400
commit02376d8282b88f07d0716da6155094c8760b1a13 (patch)
tree9e81e9b229f9230f2d42f8e80fdd50966eac13bc /drivers/gpu/drm/radeon/radeon_prime.c
parent77497f2735ad6e29c55475e15e9790dbfa2c2ef8 (diff)
drm/radeon: Allow write-combined CPU mappings of BOs in GTT (v2)
v2: fix rebase onto drm-fixes Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_prime.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_prime.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index 20074560fc2..f7e48d329db 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -65,7 +65,7 @@ struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
int ret;
ret = radeon_bo_create(rdev, size, PAGE_SIZE, false,
- RADEON_GEM_DOMAIN_GTT, sg, &bo);
+ RADEON_GEM_DOMAIN_GTT, 0, sg, &bo);
if (ret)
return ERR_PTR(ret);