diff options
author | Herbert Xu <herbert@gondor.apana.org.au> | 2013-09-07 12:53:35 +1000 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2013-09-07 12:53:35 +1000 |
commit | eeca9fad52fc4bfdf42c38bfcf383e932eb3e9d6 (patch) | |
tree | cc51c880459d41c0e8d7576405bef4c987bc7aa0 /drivers/media/usb/em28xx/em28xx-reg.h | |
parent | ff6f83fc9d44db09997937c3475d525a6866fbb4 (diff) | |
parent | b48a97be8e6c2afdba2f3b61fd88c3c7743fbd73 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
Merge upstream tree in order to reinstate crct10dif.
Diffstat (limited to 'drivers/media/usb/em28xx/em28xx-reg.h')
-rw-r--r-- | drivers/media/usb/em28xx/em28xx-reg.h | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/drivers/media/usb/em28xx/em28xx-reg.h b/drivers/media/usb/em28xx/em28xx-reg.h index 622871db04a..0e047784796 100644 --- a/drivers/media/usb/em28xx/em28xx-reg.h +++ b/drivers/media/usb/em28xx/em28xx-reg.h @@ -49,8 +49,9 @@ /* GPIO/GPO registers */ -#define EM2880_R04_GPO 0x04 /* em2880-em2883 only */ -#define EM28XX_R08_GPIO 0x08 /* em2820 or upper */ +#define EM2880_R04_GPO 0x04 /* em2880-em2883 only */ +#define EM2820_R08_GPIO_CTRL 0x08 /* em2820-em2873/83 only */ +#define EM2820_R09_GPIO_STATE 0x09 /* em2820-em2873/83 only */ #define EM28XX_R06_I2C_CLK 0x06 @@ -67,7 +68,8 @@ #define EM28XX_R0A_CHIPID 0x0a -#define EM28XX_R0C_USBSUSP 0x0c /* */ +#define EM28XX_R0C_USBSUSP 0x0c +#define EM28XX_R0C_USBSUSP_SNAPSHOT 0x20 /* 1=button pressed, needs reset */ #define EM28XX_R0E_AUDIOSRC 0x0e #define EM28XX_R0F_XCLK 0x0f @@ -193,7 +195,20 @@ #define EM2874_R50_IR_CONFIG 0x50 #define EM2874_R51_IR 0x51 #define EM2874_R5F_TS_ENABLE 0x5f -#define EM2874_R80_GPIO 0x80 + +/* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */ +/* + * NOTE: not all ports are bonded out; + * Some ports are multiplexed with special function I/O + */ +#define EM2874_R80_GPIO_P0_CTRL 0x80 +#define EM2874_R81_GPIO_P1_CTRL 0x81 +#define EM2874_R82_GPIO_P2_CTRL 0x82 +#define EM2874_R83_GPIO_P3_CTRL 0x83 +#define EM2874_R84_GPIO_P0_STATE 0x84 +#define EM2874_R85_GPIO_P1_STATE 0x85 +#define EM2874_R86_GPIO_P2_STATE 0x86 +#define EM2874_R87_GPIO_P3_STATE 0x87 /* em2874 IR config register (0x50) */ #define EM2874_IR_NEC 0x00 |