diff options
| author | Philipp Zabel <philipp.zabel@gmail.com> | 2009-06-05 18:31:01 +0200 |
|---|---|---|
| committer | Samuel Ortiz <sameol@linux.intel.com> | 2009-06-17 19:41:39 +0200 |
| commit | 6483c1b5e1a6e3489640a1376e951395982e9615 (patch) | |
| tree | 48dfc13997457dfbd7927762909c9b4dcab5643c /drivers/mfd/asic3.c | |
| parent | 9e5aca58c2d2202937939dad8f9ce5d789ae4de8 (diff) | |
mfd: asic3: add asic3_set_register common operation
Used to configure single bits of the SDHWCTRL_SDCONF and EXTCF_RESET/SELECT
registers needed for DS1WM, MMC/SDIO and PCMCIA functionality.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/asic3.c')
| -rw-r--r-- | drivers/mfd/asic3.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c index 9e485459f63..ad3c5913599 100644 --- a/drivers/mfd/asic3.c +++ b/drivers/mfd/asic3.c @@ -52,6 +52,21 @@ static inline u32 asic3_read_register(struct asic3 *asic, (reg >> asic->bus_shift)); } +void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&asic->lock, flags); + val = asic3_read_register(asic, reg); + if (set) + val |= bits; + else + val &= ~bits; + asic3_write_register(asic, reg, val); + spin_unlock_irqrestore(&asic->lock, flags); +} + /* IRQs */ #define MAX_ASIC_ISR_LOOPS 20 #define ASIC3_GPIO_BASE_INCR \ |