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authorSantosh Rastapur <santosh@chelsio.com>2013-03-14 05:08:51 +0000
committerDavid S. Miller <davem@davemloft.net>2013-03-14 11:35:54 -0400
commit22adfe0a85ca3808e09e7b4787cb08299d89aeaa (patch)
treefd9c1b4a122c91c69f7038f2956f9d741a8959e1 /drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
parent251f9e88a2c1e61071bd0eefa0f5f2e1ebc3fcff (diff)
cxgb4: Add T5 write combining support
This patch implements a low latency Write Combining (aka Write Coalescing) work request path. PCIE maps User Space Doorbell BAR2 region writes to the new interface to SGE. SGE pulls a new message from PCIE new interface and if its a coalesced write work request then pushes it for processing. This patch copies coalesced work request to memory mapped BAR2 space. Signed-off-by: Santosh Rastapur <santosh@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/cxgb4.h')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index a91dea621fc..f8ff30e749b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -439,6 +439,7 @@ struct sge_txq {
spinlock_t db_lock;
int db_disabled;
unsigned short db_pidx;
+ u64 udb;
};
struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
@@ -543,6 +544,7 @@ enum chip_type {
struct adapter {
void __iomem *regs;
+ void __iomem *bar2;
struct pci_dev *pdev;
struct device *pdev_dev;
unsigned int mbox;