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authorOskar Schirmer <oskar@scara.com>2013-08-05 07:36:02 +0000
committerMark Brown <broonie@linaro.org>2013-08-05 17:03:42 +0100
commite06e4c2d530fd4995c41083009647263ccd77d3b (patch)
treef9a823c1ad1b12e386089d9ad1436845486ef0c6 /drivers/net/ethernet/i825xx/Makefile
parentcb23e852aabb50f5083fb734c2067220d087d26e (diff)
ASoC: sgtl5000: fix codec clock source transition to avoid clockless moment
Powering down PLL before switching to a mode that does not use it is a bad idea. It would cause the SGTL5000 be without internal clock supply, especially on the I2C interface, which would make subsequent access to it fail. Thus, in case of not using PLL any longer, first set the mode control, then power down PLL. Signed-off-by: Oskar Schirmer <oskar@scara.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/net/ethernet/i825xx/Makefile')
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