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authorJeff Garzik <jeff@garzik.org>2006-09-19 15:27:07 -0400
committerJeff Garzik <jeff@garzik.org>2006-09-19 15:27:07 -0400
commitf8ec473387f70d103c83ffb3ab50cb2b1380d0c0 (patch)
tree8abcae6e3e7c4692519196c26dac4a82e65753b4 /drivers/net/ixgb/ixgb_hw.c
parent23b6b0e3e8306ce3d00e0c87196bfaad335b9096 (diff)
e1000, ixgb: Remove pointless wrappers
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/ixgb/ixgb_hw.c')
-rw-r--r--drivers/net/ixgb/ixgb_hw.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
index 2b1515574fa..acc6df7a6b3 100644
--- a/drivers/net/ixgb/ixgb_hw.c
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -83,7 +83,7 @@ static uint32_t ixgb_mac_reset(struct ixgb_hw *hw)
#endif
/* Delay a few ms just to allow the reset to complete */
- msec_delay(IXGB_DELAY_AFTER_RESET);
+ msleep(IXGB_DELAY_AFTER_RESET);
ctrl_reg = IXGB_READ_REG(hw, CTRL0);
#ifdef DBG
/* Make sure the self-clearing global reset bit did self clear */
@@ -133,7 +133,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
*/
IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
- msec_delay(IXGB_DELAY_BEFORE_RESET);
+ msleep(IXGB_DELAY_BEFORE_RESET);
/* Issue a global reset to the MAC. This will reset the chip's
* transmit, receive, DMA, and link units. It will not effect
@@ -300,7 +300,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
#endif
/* Delay a few ms just to allow the reset to complete */
- msec_delay(IXGB_DELAY_AFTER_EE_RESET);
+ msleep(IXGB_DELAY_AFTER_EE_RESET);
if (ixgb_get_eeprom_data(hw) == FALSE) {
return(FALSE);