diff options
| author | Rajkumar Manoharan <rmanoharan@atheros.com> | 2010-09-03 16:00:00 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-09-07 13:54:34 -0400 |
| commit | c2ba33424600e742f4d44ba2237024e6322a00fa (patch) | |
| tree | 93b56c34cd06a705254845601474eb0eb8e8daeb /drivers/net/wireless/ath/ath9k/ar9002_hw.c | |
| parent | 7cf1f2dd7de98e9a18536ab885d28ecb57e76cb1 (diff) | |
ath9k_hw: Restore ANI registers to default during partial reset for AR9271
For AR9271 chips, if partial reset is done while scanning, the cycpwrThr1
will be set to maximum. This causes the degrade in DL throughput.
So restore the ANI registers to default during the partial reset.
Signed-off-by: Rajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_hw.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9002_hw.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c index 303c63da5ea..94392daebaa 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c @@ -580,3 +580,53 @@ void ar9002_hw_attach_ops(struct ath_hw *ah) else ath9k_hw_attach_ani_ops_old(ah); } + +void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) +{ + u32 modesIndex; + int i; + + switch (chan->chanmode) { + case CHANNEL_A: + case CHANNEL_A_HT20: + modesIndex = 1; + break; + case CHANNEL_A_HT40PLUS: + case CHANNEL_A_HT40MINUS: + modesIndex = 2; + break; + case CHANNEL_G: + case CHANNEL_G_HT20: + case CHANNEL_B: + modesIndex = 4; + break; + case CHANNEL_G_HT40PLUS: + case CHANNEL_G_HT40MINUS: + modesIndex = 3; + break; + + default: + return; + } + + ENABLE_REGWRITE_BUFFER(ah); + + for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); + u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); + u32 val_orig; + + if (reg == AR_PHY_CCK_DETECT) { + val_orig = REG_READ(ah, reg); + val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; + val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; + + REG_WRITE(ah, reg, val|val_orig); + } else + REG_WRITE(ah, reg, val); + } + + REGWRITE_BUFFER_FLUSH(ah); + DISABLE_REGWRITE_BUFFER(ah); + +} |