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authorJon Mason <mason@myri.com>2011-10-14 14:56:16 -0500
committerJesse Barnes <jbarnes@virtuousgeek.org>2011-10-27 12:45:44 -0700
commita513a99a7cebfb452839cc09c9c0586f72d96414 (patch)
tree566fb8a8fa8c02ede05b2694dd16a8efea5342bb /drivers/pci
parenta1c473aa11e61bc871be16279c9bf976acf22504 (diff)
PCI: Clean-up MPS debug output
Clean-up MPS debug output to make it a single line and aligned, thus making it more readable for a large number of buses and devices in a single system. Suggested by Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Jon Mason <mason@myri.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/probe.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 48294243985..04e74f48571 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1428,24 +1428,25 @@ static void pcie_write_mrrs(struct pci_dev *dev)
static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
{
- int mps = 128 << *(u8 *)data;
+ int mps, orig_mps;
if (!pci_is_pcie(dev))
return 0;
- dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
- pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
+ mps = 128 << *(u8 *)data;
+ orig_mps = pcie_get_mps(dev);
pcie_write_mps(dev, mps);
pcie_write_mrrs(dev);
- dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
- pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
+ dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
+ "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
+ orig_mps, pcie_get_readrq(dev));
return 0;
}
-/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down,
+/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
* parents then children fashion. If this changes, then this code will not
* work as designed.
*/