diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-08-23 17:40:56 +0100 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2010-09-08 12:23:03 -0600 |
commit | be7852a839b6dcd86db1a2d25b9a1a99f38db2db (patch) | |
tree | 9ecd429f529c524bae5bd2bbdfe47364a4cbe106 /drivers/spi | |
parent | c3f139b65585a5f29df47b2302ff8dbd9bdad0b0 (diff) |
spi/spi_s3c64xx: Warn if PIO transfers time out
When using PIO we have a timeout for the TX and RX FIFOs to ensure that
the data actually gets transferred. Warn if we hit that timeout - it
should never happen, but this makes sure we'll find out if it does.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi')
-rw-r--r-- | drivers/spi/spi_s3c64xx.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c index ef9dacabe06..c3038da2648 100644 --- a/drivers/spi/spi_s3c64xx.c +++ b/drivers/spi/spi_s3c64xx.c @@ -200,6 +200,9 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) val = readl(regs + S3C64XX_SPI_STATUS); } while (TX_FIFO_LVL(val, sci) && loops--); + if (loops == 0) + dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); + /* Flush RxFIFO*/ loops = msecs_to_loops(1); do { @@ -210,6 +213,9 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) break; } while (loops--); + if (loops == 0) + dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); + val = readl(regs + S3C64XX_SPI_CH_CFG); val &= ~S3C64XX_SPI_CH_SW_RST; writel(val, regs + S3C64XX_SPI_CH_CFG); |