diff options
| author | Greg Kroah-Hartman <gregkh@suse.de> | 2010-05-21 12:48:55 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-05-21 12:48:55 -0700 |
| commit | c8d1a126924fcbc1d61ceb830226e0c7afdcc841 (patch) | |
| tree | d3f3c850481c33b7f433175e83a189f958b1b868 /drivers/staging/winbond | |
| parent | d7dbf4ffee1c7a17e2e5b5f01efe76fbd1671db6 (diff) | |
| parent | 107c161b7ddeeb7da43509cc6b29211885ccd9af (diff) | |
Merge staging-next tree into Linus's latest version
Conflicts:
drivers/staging/arlan/arlan-main.c
drivers/staging/comedi/drivers/cb_das16_cs.c
drivers/staging/cx25821/cx25821-alsa.c
drivers/staging/dt3155/dt3155_drv.c
drivers/staging/hv/hv.c
drivers/staging/netwave/netwave_cs.c
drivers/staging/wavelan/wavelan.c
drivers/staging/wavelan/wavelan_cs.c
drivers/staging/wlags49_h2/wl_cs.c
This required a bit of hand merging due to the conflicts
that happened in the later .34-rc releases, as well as
some staging driver changing coming in through other trees
(v4l and pcmcia).
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/winbond')
28 files changed, 4134 insertions, 4667 deletions
diff --git a/drivers/staging/winbond/README b/drivers/staging/winbond/TODO index cb944e4bf17..8c1baaf6d8a 100644 --- a/drivers/staging/winbond/README +++ b/drivers/staging/winbond/TODO @@ -2,10 +2,11 @@ TODO: - sparse cleanups - checkpatch cleanups - kerneldoc cleanups + - fix severeCamelCaseInfestation - remove typedefs - remove unused ioctls - use cfg80211 for regulatory stuff - fix 4k stack problems Please send patches to Greg Kroah-Hartman <greg@kroah.com> and -Pavel Machek <pavel@suse.cz> +Pavel Machek <pavel@ucw.cz> diff --git a/drivers/staging/winbond/core.h b/drivers/staging/winbond/core.h index 0a2060bf4f9..b87d6c07600 100644 --- a/drivers/staging/winbond/core.h +++ b/drivers/staging/winbond/core.h @@ -12,14 +12,16 @@ #define WB_MAX_LINK_NAME_LEN 40 struct wbsoft_priv { - u32 adapterIndex; // 20060703.4 Add for using padapterContext global adapter point + u32 adapterIndex; /* 20060703.4 Add for using padapterContext + global adapter point */ - struct wb_local_para sLocalPara; // Myself connected parameters + struct wb_local_para sLocalPara; /* Myself connected + parameters */ - MLME_FRAME sMlmeFrame; // connect to peerSTA parameters + MLME_FRAME sMlmeFrame; /* connect to peerSTA parameters */ - struct wb35_mto_params sMtoPara; // MTO_struct ... - struct hw_data sHwData; //For HAL + struct wb35_mto_params sMtoPara; /* MTO_struct ... */ + struct hw_data sHwData; /*For HAL */ struct wb35_mds Mds; spinlock_t SpinLock; @@ -30,7 +32,7 @@ struct wbsoft_priv { u32 TxByteCount; struct sk_buff *packet_return; - s32 netif_state_stop; // 1: stop 0: normal + s32 netif_state_stop; /* 1: stop 0: normal */ struct iw_statistics iw_stats; u8 LinkName[WB_MAX_LINK_NAME_LEN]; diff --git a/drivers/staging/winbond/localpara.h b/drivers/staging/winbond/localpara.h index fcf6a0442dc..d7980575bed 100644 --- a/drivers/staging/winbond/localpara.h +++ b/drivers/staging/winbond/localpara.h @@ -1,263 +1,267 @@ #ifndef __WINBOND_LOCALPARA_H #define __WINBOND_LOCALPARA_H -//============================================================= -// LocalPara.h - -//============================================================= +/* + * ============================================================= + * LocalPara.h - + * ============================================================= + */ #include "mac_structures.h" -//Define the local ability +/* Define the local ability */ -#define LOCAL_DEFAULT_BEACON_PERIOD 100 //ms -#define LOCAL_DEFAULT_ATIM_WINDOW 0 -#define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 //0x0001: ESS - //0x0010: Privacy - //0x0020: short preamble - //0x0400: short slot time -#define LOCAL_DEFAULT_LISTEN_INTERVAL 5 +#define LOCAL_DEFAULT_BEACON_PERIOD 100 /* ms */ +#define LOCAL_DEFAULT_ATIM_WINDOW 0 +#define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 /* + * 0x0001: ESS + * 0x0010: Privacy + * 0x0020: short preamble + * 0x0400: short slot time + */ +#define LOCAL_DEFAULT_LISTEN_INTERVAL 5 -//#define LOCAL_DEFAULT_24_CHANNEL_NUM 11 // channel 1..11 -#define LOCAL_DEFAULT_24_CHANNEL_NUM 13 // channel 1..13 -#define LOCAL_DEFAULT_5_CHANNEL_NUM 8 // channel 36..64 +#define LOCAL_DEFAULT_24_CHANNEL_NUM 13 /* channel 1..13 */ +#define LOCAL_DEFAULT_5_CHANNEL_NUM 8 /* channel 36..64 */ -#define LOCAL_USA_24_CHANNEL_NUM 11 -#define LOCAL_USA_5_CHANNEL_NUM 12 -#define LOCAL_EUROPE_24_CHANNEL_NUM 13 -#define LOCAL_EUROPE_5_CHANNEL_NUM 19 -#define LOCAL_JAPAN_24_CHANNEL_NUM 14 -#define LOCAL_JAPAN_5_CHANNEL_NUM 11 -#define LOCAL_UNKNOWN_24_CHANNEL_NUM 14 -#define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 //not include 165 +#define LOCAL_USA_24_CHANNEL_NUM 11 +#define LOCAL_USA_5_CHANNEL_NUM 12 +#define LOCAL_EUROPE_24_CHANNEL_NUM 13 +#define LOCAL_EUROPE_5_CHANNEL_NUM 19 +#define LOCAL_JAPAN_24_CHANNEL_NUM 14 +#define LOCAL_JAPAN_5_CHANNEL_NUM 11 +#define LOCAL_UNKNOWN_24_CHANNEL_NUM 14 +#define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 /* not include 165 */ - -#define psLOCAL (&(adapter->sLocalPara)) +#define psLOCAL (&(adapter->sLocalPara)) #define MODE_802_11_BG 0 #define MODE_802_11_A 1 #define MODE_802_11_ABG 2 #define MODE_802_11_BG_IBSS 3 #define MODE_802_11_B 4 -#define MODE_AUTO 255 +#define MODE_AUTO 255 #define BAND_TYPE_DSSS 0 #define BAND_TYPE_OFDM_24 1 #define BAND_TYPE_OFDM_5 2 -//refer Bitmap2RateValue table -#define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 //the bitmap value of all the H/W supported rates - //1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 -#define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 //the bitmap value of all the H/W supported rates - //except to non-OFDM rates - //6, 9, 12, 18, 24, 36, 48, 54 - -#define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826 -#define LOCAL_11B_BASIC_RATE_BITMAP 0x826 -#define LOCAL_11B_OPERATION_RATE_BITMAP 0x826 -#define LOCAL_11G_BASIC_RATE_BITMAP 0x826 //1, 2, 5.5, 11 -#define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 //6, 9, 12, 18, 24, 36, 48, 54 -#define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 //6, 12, 24 -#define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 //9, 18, 36, 48, 54 - - - -#define PWR_ACTIVE 0 -#define PWR_SAVE 1 +/* refer Bitmap2RateValue table */ + +/* the bitmap value of all the H/W supported rates: */ +/* 1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 */ +#define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 +/* the bitmap value of all the H/W supported rates except to non-OFDM rates: */ +/* 6, 9, 12, 18, 24, 36, 48, 54 */ +#define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 +#define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826 +#define LOCAL_11B_BASIC_RATE_BITMAP 0x826 +#define LOCAL_11B_OPERATION_RATE_BITMAP 0x826 +#define LOCAL_11G_BASIC_RATE_BITMAP 0x826 /* 1, 2, 5.5, 11 */ +#define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 /* 6, 9, 12, 18, 24, 36, 48, 54 */ +#define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 /* 6, 12, 24 */ +#define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 /* 9, 18, 36, 48, 54 */ + + +#define PWR_ACTIVE 0 +#define PWR_SAVE 1 #define PWR_TX_IDLE_CYCLE 6 -//bPreambleMode and bSlotTimeMode -#define AUTO_MODE 0 -#define LONG_MODE 1 - -//Region definition -#define REGION_AUTO 0xff -#define REGION_UNKNOWN 0 -#define REGION_EUROPE 1 //ETSI -#define REGION_JAPAN 2 //MKK -#define REGION_USA 3 //FCC -#define REGION_FRANCE 4 //FRANCE -#define REGION_SPAIN 5 //SPAIN -#define REGION_ISRAEL 6 //ISRAEL -//#define REGION_CANADA 7 //IC +/* bPreambleMode and bSlotTimeMode */ +#define AUTO_MODE 0 +#define LONG_MODE 1 + +/* Region definition */ +#define REGION_AUTO 0xff +#define REGION_UNKNOWN 0 +#define REGION_EUROPE 1 /* ETSI */ +#define REGION_JAPAN 2 /* MKK */ +#define REGION_USA 3 /* FCC */ +#define REGION_FRANCE 4 /* FRANCE */ +#define REGION_SPAIN 5 /* SPAIN */ +#define REGION_ISRAEL 6 /* ISRAEL */ #define MAX_BSS_DESCRIPT_ELEMENT 32 -#define MAX_PMKID_CandidateList 16 - -//High byte : Event number, low byte : reason -//Event definition -//-- SME/MLME event -#define EVENT_RCV_DEAUTH 0x0100 -#define EVENT_JOIN_FAIL 0x0200 -#define EVENT_AUTH_FAIL 0x0300 -#define EVENT_ASSOC_FAIL 0x0400 -#define EVENT_LOST_SIGNAL 0x0500 -#define EVENT_BSS_DESCRIPT_LACK 0x0600 -#define EVENT_COUNTERMEASURE 0x0700 -#define EVENT_JOIN_FILTER 0x0800 -//-- TX/RX event -#define EVENT_RX_BUFF_UNAVAILABLE 0x4100 - -#define EVENT_CONNECT 0x8100 -#define EVENT_DISCONNECT 0x8200 -#define EVENT_SCAN_REQ 0x8300 - -//Reason of Event +#define MAX_PMKID_CandidateList 16 + +/* + * High byte : Event number, low byte : reason + * Event definition + * -- SME/MLME event + */ +#define EVENT_RCV_DEAUTH 0x0100 +#define EVENT_JOIN_FAIL 0x0200 +#define EVENT_AUTH_FAIL 0x0300 +#define EVENT_ASSOC_FAIL 0x0400 +#define EVENT_LOST_SIGNAL 0x0500 +#define EVENT_BSS_DESCRIPT_LACK 0x0600 +#define EVENT_COUNTERMEASURE 0x0700 +#define EVENT_JOIN_FILTER 0x0800 +/* -- TX/RX event */ +#define EVENT_RX_BUFF_UNAVAILABLE 0x4100 + +#define EVENT_CONNECT 0x8100 +#define EVENT_DISCONNECT 0x8200 +#define EVENT_SCAN_REQ 0x8300 + +/* Reason of Event */ #define EVENT_REASON_FILTER_BASIC_RATE 0x0001 -#define EVENT_REASON_FILTER_PRIVACY 0x0002 +#define EVENT_REASON_FILTER_PRIVACY 0x0002 #define EVENT_REASON_FILTER_AUTH_MODE 0x0003 -#define EVENT_REASON_TIMEOUT 0x00ff +#define EVENT_REASON_TIMEOUT 0x00ff -// 20061108 WPS IE buffer -#define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes +/* Due to[E id][Length][OUI][Data] may be 257 bytes */ +#define MAX_IE_APPEND_SIZE (256 + 4) -struct chan_info -{ - u8 band; - u8 ChanNo; +struct chan_info { + u8 band; + u8 ChanNo; }; -struct radio_off -{ - u8 boHwRadioOff; - u8 boSwRadioOff; +struct radio_off { + u8 boHwRadioOff; + u8 boSwRadioOff; }; -//=========================================================================== -struct wb_local_para -{ - u8 PermanentAddress[ MAC_ADDR_LENGTH + 2 ]; // read from EPROM, manufacture set for each NetCard - u8 ThisMacAddress[ MAC_ADDR_LENGTH + 2 ]; // the driver will use actually. - - u32 MTUsize; // Ind to Uplayer, Max transmission unit size - - u8 region_INF; //region setting from INF - u8 region; //real region setting of the device - u8 Reserved_1[2]; - - //// power-save variables - u8 iPowerSaveMode; // 0 indicates it is on, 1 indicates it is off - u8 ATIMmode; - u8 ExcludeUnencrypted; - - u16 CheckCountForPS; //Unit ime count for the decision to enter PS mode - u8 boHasTxActivity; //tx activity has occurred - u8 boMacPsValid; //Power save mode obtained from H/W is valid or not - - //// Rate - u8 TxRateMode; // Initial, input from Registry, may be updated by GUI - //Tx Rate Mode: auto(DTO on), max, 1M, 2M, .. - u8 CurrentTxRate; // The current Tx rate - u8 CurrentTxRateForMng; // The current Tx rate for management frames - // It will be decided before connection succeeds. - u8 CurrentTxFallbackRate; - - //for Rate handler - u8 BRateSet[32]; //basic rate set - u8 SRateSet[32]; //support rate set - - u8 NumOfBRate; - u8 NumOfSRate; - u8 NumOfDsssRateInSRate; //number of DSSS rates in supported rate set - u8 reserved1; - - u32 dwBasicRateBitmap; //bit map of basic rates - u32 dwSupportRateBitmap; //bit map of all support rates including - //basic and operational rates - - ////For SME/MLME handler - u16 wOldSTAindex; // valid when boHandover=TRUE, store old connected STA index - u16 wConnectedSTAindex; // Index of peerly connected AP or IBSS in - // the descriptionset. - u16 Association_ID; // The Association ID in the (Re)Association - // Response frame. - u16 ListenInterval; // The listen interval when SME invoking MLME_ - // (Re)Associate_Request(). - - struct radio_off RadioOffStatus; - u8 Reserved0[2]; - - u8 boMsRadioOff; // Ndis demands to be true when set Disassoc. OID and be false when set SSID OID. - u8 bAntennaNo; //which antenna - u8 bConnectFlag; //the connect status flag for roaming task - - u8 RoamStatus; - u8 reserved7[3]; - - struct chan_info CurrentChan; //Current channel no. and channel band. It may be changed by scanning. - u8 boHandover; // Roaming, Hnadover to other AP. - u8 boCCAbusy; - - u16 CWMax; // It may not be the real value that H/W used - u8 CWMin; // 255: set according to 802.11 spec. - u8 reserved2; - - //11G: - u8 bMacOperationMode; // operation in 802.11b or 802.11g - u8 bSlotTimeMode; //AUTO, s32 - u8 bPreambleMode; //AUTO, s32 - u8 boNonERPpresent; - - u8 boProtectMechanism; // H/W will take the necessary action based on this variable - u8 boShortPreamble; // H/W will take the necessary action based on this variable - u8 boShortSlotTime; // H/W will take the necessary action based on this variable - u8 reserved_3; - - u32 RSN_IE_Bitmap; //added by WS - u32 RSN_OUI_Type; //added by WS - - //For the BSSID - u8 HwBssid[MAC_ADDR_LENGTH + 2]; - u32 HwBssidValid; - - //For scan list - u8 BssListCount; //Total count of valid descriptor indexes - u8 boReceiveUncorrectInfo; //important settings in beacon/probe resp. have been changed - u8 NoOfJoinerInIbss; - u8 reserved_4; - - u8 BssListIndex[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //Store the valid descriptor indexes obtained from scannings - u8 JoinerInIbss[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //save the BssDescriptor index in this - //IBSS. The index 0 is local descriptor - //(psLOCAL->wConnectedSTAindex). - //If CONNECTED : NoOfJoinerInIbss >=2 - // else : NoOfJoinerInIbss <=1 - - //// General Statistics, count at Rx_handler or Tx_callback interrupt handler - u64 GS_XMIT_OK; // Good Frames Transmitted - u64 GS_RCV_OK; // Good Frames Received - u32 GS_RCV_ERROR; // Frames received with crc error - u32 GS_XMIT_ERROR; // Bad Frames Transmitted - u32 GS_RCV_NO_BUFFER; // Receive Buffer underrun - u32 GS_XMIT_ONE_COLLISION; // one collision - u32 GS_XMIT_MORE_COLLISIONS;// more collisions - - //================================================================ - // Statistics (no matter whether it had done successfully) -wkchen - //================================================================ - u32 _NumRxMSDU; - u32 _NumTxMSDU; - u32 _dot11WEPExcludedCount; - u32 _dot11WEPUndecryptableCount; - u32 _dot11FrameDuplicateCount; - - struct chan_info IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU. - u8 reserved_5[2]; //It may not be used after considering RF type, - //region and modulation type. - - u8 reserved_6[2]; //two variables are for wep key error detection added by ws 02/02/04 - - u32 bWepKeyError; - u32 bToSelfPacketReceived; - u32 WepKeyDetectTimerCount; - - u16 SignalLostTh; - u16 SignalRoamTh; - - // 20061108 WPS IE Append +struct wb_local_para { + /* read from EPROM, manufacture set for each NetCard */ + u8 PermanentAddress[MAC_ADDR_LENGTH + 2]; + /* the driver will use this one actually. */ + u8 ThisMacAddress[MAC_ADDR_LENGTH + 2]; + u32 MTUsize; /* Ind to Uplayer, Max transmission unit size */ + u8 region_INF; /* region setting from INF */ + u8 region; /* real region setting of the device */ + u8 Reserved_1[2]; + + /* power-save variables */ + u8 iPowerSaveMode; /* 0 indicates on, 1 indicates off */ + u8 ATIMmode; + u8 ExcludeUnencrypted; + /* Unit ime count for the decision to enter PS mode */ + u16 CheckCountForPS; + u8 boHasTxActivity;/* tx activity has occurred */ + u8 boMacPsValid; /* Power save mode obtained from H/W is valid or not */ + + /* Rate */ + u8 TxRateMode; /* + * Initial, input from Registry, + * may be updated by GUI + * Tx Rate Mode: auto(DTO on), max, 1M, 2M, .. + */ + u8 CurrentTxRate; /* The current Tx rate */ + u8 CurrentTxRateForMng; /* + * The current Tx rate for management + * frames. It will be decided before + * connection succeeds. + */ + u8 CurrentTxFallbackRate; + + /* for Rate handler */ + u8 BRateSet[32]; /* basic rate set */ + u8 SRateSet[32]; /* support rate set */ + + u8 NumOfBRate; + u8 NumOfSRate; + u8 NumOfDsssRateInSRate; /* number of DSSS rates in supported rate set */ + u8 reserved1; + + u32 dwBasicRateBitmap; /* bit map of basic rates */ + + u32 dwSupportRateBitmap; /* bit map of all support rates including basic and operational rates */ + + + /* For SME/MLME handler */ + + u16 wOldSTAindex; /* valid when boHandover=TRUE, store old connected STA index */ + u16 wConnectedSTAindex; /* Index of peerly connected AP or IBSS in the descriptionset. */ + u16 Association_ID; /* The Association ID in the (Re)Association Response frame. */ + u16 ListenInterval; /* The listen interval when SME invoking MLME_ (Re)Associate_Request(). */ + + struct radio_off RadioOffStatus; + u8 Reserved0[2]; + u8 boMsRadioOff; /* Ndis demands to be true when set Disassoc. OID and be false when set SSID OID. */ + u8 bAntennaNo; /* which antenna */ + u8 bConnectFlag; /* the connect status flag for roaming task */ + + u8 RoamStatus; + u8 reserved7[3]; + + struct chan_info CurrentChan; /* Current channel no. and channel band. It may be changed by scanning. */ + u8 boHandover; /* Roaming, Hnadover to other AP. */ + u8 boCCAbusy; + + u16 CWMax; /* It may not be the real value that H/W used */ + u8 CWMin; /* 255: set according to 802.11 spec. */ + u8 reserved2; + + /* 11G: */ + u8 bMacOperationMode; /* operation in 802.11b or 802.11g */ + u8 bSlotTimeMode; /* AUTO, s32 */ + u8 bPreambleMode; /* AUTO, s32 */ + u8 boNonERPpresent; + + u8 boProtectMechanism; /* H/W will take the necessary action based on this variable */ + u8 boShortPreamble; /* Same here */ + u8 boShortSlotTime; /* Same here */ + u8 reserved_3; + + u32 RSN_IE_Bitmap; + u32 RSN_OUI_Type; + + /* For the BSSID */ + u8 HwBssid[MAC_ADDR_LENGTH + 2]; + u32 HwBssidValid; + + /* For scan list */ + u8 BssListCount; /* Total count of valid descriptor indexes */ + u8 boReceiveUncorrectInfo; /* important settings in beacon/probe resp. have been changed */ + u8 NoOfJoinerInIbss; + u8 reserved_4; + + /* Store the valid descriptor indexes obtained from scannings */ + u8 BssListIndex[(MAX_BSS_DESCRIPT_ELEMENT + 3) & ~0x03]; + /* + * Save the BssDescriptor index in this IBSS. + * The index 0 is local descriptor (psLOCAL->wConnectedSTAindex). + * If CONNECTED : NoOfJoinerInIbss >= 2 + * else : NoOfJoinerInIbss <= 1 + */ + u8 JoinerInIbss[(MAX_BSS_DESCRIPT_ELEMENT + 3) & ~0x03]; + + /* General Statistics, count at Rx_handler or Tx_callback interrupt handler */ + u64 GS_XMIT_OK; /* Good Frames Transmitted */ + u64 GS_RCV_OK; /* Good Frames Received */ + u32 GS_RCV_ERROR; /* Frames received with crc error */ + u32 GS_XMIT_ERROR; /* Bad Frames Transmitted */ + u32 GS_RCV_NO_BUFFER; /* Receive Buffer underrun */ + u32 GS_XMIT_ONE_COLLISION; /* one collision */ + u32 GS_XMIT_MORE_COLLISIONS;/* more collisions */ + + /* + * ================================================================ + * Statistics (no matter whether it had done successfully) -wkchen + * ================================================================ + */ + u32 _NumRxMSDU; + u32 _NumTxMSDU; + u32 _dot11WEPExcludedCount; + u32 _dot11WEPUndecryptableCount; + u32 _dot11FrameDuplicateCount; + + struct chan_info IbssChanSetting; /* 2B. Start IBSS Channel setting by registry or WWU. */ + u8 reserved_5[2]; /* It may not be used after considering RF type, region and modulation type. */ + + u8 reserved_6[2]; /* two variables are for wep key error detection */ + u32 bWepKeyError; + u32 bToSelfPacketReceived; + u32 WepKeyDetectTimerCount; + + u16 SignalLostTh; + u16 SignalRoamTh; + u8 IE_Append_data[MAX_IE_APPEND_SIZE]; u16 IE_Append_size; u16 reserved_7; - }; #endif diff --git a/drivers/staging/winbond/mac_structures.h b/drivers/staging/winbond/mac_structures.h index 0d1619601c0..7441015cb18 100644 --- a/drivers/staging/winbond/mac_structures.h +++ b/drivers/staging/winbond/mac_structures.h @@ -1,4 +1,4 @@ -//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ // MAC_Structures.h // // This file contains the definitions and data structures used by SW-MAC. @@ -16,24 +16,24 @@ // Deleted some unused. // 20021129 PD43 Austin // 20030617 increase the 802.11g definition -//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ #ifndef _MAC_Structures_H_ #define _MAC_Structures_H_ #include <linux/skbuff.h> -//========================================================= +/*========================================================= // Some miscellaneous definitions -//----- +//-----*/ #define MAX_CHANNELS 30 #define MAC_ADDR_LENGTH 6 -#define MAX_WEP_KEY_SIZE 16 // 128 bits -#define MAX_802_11_FRAGMENT_NUMBER 10 // By spec +#define MAX_WEP_KEY_SIZE 16 /* 128 bits */ +#define MAX_802_11_FRAGMENT_NUMBER 10 /* By spec */ -//======================================================== +/* ======================================================== // 802.11 Frame define -//----- +//----- */ #define MASK_PROTOCOL_VERSION_TYPE 0x0F #define MASK_FRAGMENT_NUMBER 0x000F #define SEQUENCE_NUMBER_SHIFT 4 @@ -41,8 +41,8 @@ #define DOT_11_MAC_HEADER_SIZE 24 #define DOT_11_SNAP_SIZE 6 #define DOT_11_DURATION_OFFSET 2 -#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset -#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame// +#define DOT_11_SEQUENCE_OFFSET 22 /* Sequence control offset */ +#define DOT_11_TYPE_OFFSET 30 /* The start offset of 802.11 Frame// */ #define DOT_11_DATA_OFFSET 24 #define DOT_11_DA_OFFSET 4 #define DOT_3_TYPE_ARP 0x80F3 @@ -54,7 +54,7 @@ #define MAX_ETHERNET_PACKET_SIZE 1514 -//----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) +/* ----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ #define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00 #define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10 #define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20 @@ -67,7 +67,7 @@ #define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0 #define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0 -//----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) +/* ----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ #define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4 #define MAC_SUBTYPE_CONTROL_RTS 0xB4 #define MAC_SUBTYPE_CONTROL_CTS 0xC4 @@ -75,7 +75,7 @@ #define MAC_SUBTYPE_CONTROL_CFEND 0xE4 #define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4 -//----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) +/* ----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) */ #define MAC_SUBTYPE_DATA 0x08 #define MAC_SUBTYPE_DATA_CFACK 0x18 #define MAC_SUBTYPE_DATA_CFPOLL 0x28 @@ -85,12 +85,12 @@ #define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78 -//----- Frame Type of Bits (2, 3) +/* ----- Frame Type of Bits (2, 3) */ #define MAC_TYPE_MANAGEMENT 0x00 #define MAC_TYPE_CONTROL 0x04 #define MAC_TYPE_DATA 0x08 -//----- definitions for Management Frame Element ID (1 BYTE) +/* ----- definitions for Management Frame Element ID (1 BYTE) */ #define ELEMENT_ID_SSID 0 #define ELEMENT_ID_SUPPORTED_RATES 1 #define ELEMENT_ID_FH_PARAMETER_SET 2 @@ -116,13 +116,6 @@ #define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6) #define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2) -//======================================================== -typedef enum enum_PowerManagementMode -{ - ACTIVE = 0, - POWER_SAVE -} WB_PM_Mode, *PWB_PM_MODE; - //=================================================================== // Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen // length of ReasonCode is 2 Octs. @@ -137,7 +130,7 @@ typedef enum enum_PowerManagementMode #define REASON_CLASS3_FRAME_FROM_NONASSO_STA 7 #define DISASS_REASON_LEFT_BSS 8 #define REASON_NOT_AUTH_YET 9 -//802.11i define +/* 802.11i define */ #define REASON_INVALID_IE 13 #define REASON_MIC_ERROR 14 #define REASON_4WAY_HANDSHAKE_TIMEOUT 15 @@ -182,13 +175,12 @@ enum enum_MMPDUResultCode } WB_MMPDURESULTCODE, *PWB_MMPDURESULTCODE; */ -//=========================================================== +/*=========================================================== // enum_TxRate -- // Define the transmission constants based on W89C32 MAC // target specification. -//=========================================================== -typedef enum enum_TxRate -{ +//===========================================================*/ +typedef enum enum_TxRate { TXRATE_1M = 0, TXRATE_2MLONG = 2, TXRATE_2MSHORT = 3, @@ -196,7 +188,7 @@ typedef enum enum_TxRate TXRATE_55MSHORT = 5, TXRATE_11MLONG = 6, TXRATE_11MSHORT = 7, - TXRATE_AUTO = 255 // PD43 20021108 + TXRATE_AUTO = 255 /* PD43 20021108 */ } WB_TXRATE, *PWB_TXRATE; @@ -232,7 +224,7 @@ typedef enum enum_TxRate #define RATE_54M 108 #define RATE_MAX 255 -//CAPABILITY +/* CAPABILITY */ #define CAPABILITY_ESS_BIT 0x0001 #define CAPABILITY_IBSS_BIT 0x0002 #define CAPABILITY_CF_POLL_BIT 0x0004 @@ -245,53 +237,48 @@ typedef enum enum_TxRate #define CAPABILITY_DSSS_OFDM_BIT 0x2000 -struct Capability_Information_Element -{ - union - { - u16 __attribute__ ((packed)) wValue; - #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian - struct _Capability - { - //-- 11G -- - u8 Reserved3 : 2; - u8 DSSS_OFDM : 1; - u8 Reserved2 : 2; - u8 Short_Slot_Time : 1; - u8 Reserved1 : 2; - u8 Channel_Agility : 1; - u8 PBCC : 1; - u8 ShortPreamble : 1; - u8 CF_Privacy : 1; - u8 CF_Poll_Request : 1; - u8 CF_Pollable : 1; - u8 IBSS : 1; - u8 ESS : 1; +struct Capability_Information_Element { + union { + u16 __attribute__ ((packed)) wValue; + #ifdef _BIG_ENDIAN_ /* 20060926 add by anson's endian */ + struct _Capability { + /* -- 11G -- */ + u8 Reserved3:2; + u8 DSSS_OFDM:1; + u8 Reserved2:2; + u8 Short_Slot_Time:1; + u8 Reserved1:2; + u8 Channel_Agility:1; + u8 PBCC:1; + u8 ShortPreamble:1; + u8 CF_Privacy:1; + u8 CF_Poll_Request:1; + u8 CF_Pollable:1; + u8 IBSS:1; + u8 ESS:1; } __attribute__ ((packed)) Capability; #else - struct _Capability - { - u8 ESS : 1; - u8 IBSS : 1; - u8 CF_Pollable : 1; - u8 CF_Poll_Request : 1; - u8 CF_Privacy : 1; - u8 ShortPreamble : 1; - u8 PBCC : 1; - u8 Channel_Agility : 1; - u8 Reserved1 : 2; - //-- 11G -- - u8 Short_Slot_Time : 1; - u8 Reserved2 : 2; - u8 DSSS_OFDM : 1; - u8 Reserved3 : 2; + struct _Capability { + u8 ESS:1; + u8 IBSS:1; + u8 CF_Pollable:1; + u8 CF_Poll_Request:1; + u8 CF_Privacy:1; + u8 ShortPreamble:1; + u8 PBCC:1; + u8 Channel_Agility:1; + u8 Reserved1:2; + /* -- 11G -- */ + u8 Short_Slot_Time:1; + u8 Reserved2:2; + u8 DSSS_OFDM:1; + u8 Reserved3:2; } __attribute__ ((packed)) Capability; #endif - }__attribute__ ((packed)) ; -}__attribute__ ((packed)); + } __attribute__ ((packed)) ; +} __attribute__ ((packed)); -struct FH_Parameter_Set_Element -{ +struct FH_Parameter_Set_Element { u8 Element_ID; u8 Length; u8 Dwell_Time[2]; @@ -300,39 +287,34 @@ struct FH_Parameter_Set_Element u8 Hop_Index; }; -struct DS_Parameter_Set_Element -{ +struct DS_Parameter_Set_Element { u8 Element_ID; u8 Length; u8 Current_Channel; }; -struct Supported_Rates_Element -{ +struct Supported_Rates_Element { u8 Element_ID; u8 Length; u8 SupportedRates[8]; -}__attribute__ ((packed)); +} __attribute__ ((packed)); -struct SSID_Element -{ +struct SSID_Element { u8 Element_ID; u8 Length; u8 SSID[32]; -}__attribute__ ((packed)) ; +} __attribute__ ((packed)) ; -struct CF_Parameter_Set_Element -{ +struct CF_Parameter_Set_Element { u8 Element_ID; u8 Length; u8 CFP_Count; u8 CFP_Period; - u8 CFP_MaxDuration[2]; // in Time Units - u8 CFP_DurRemaining[2]; // in time units + u8 CFP_MaxDuration[2]; /* in Time Units */ + u8 CFP_DurRemaining[2]; /* in time units */ }; -struct TIM_Element -{ +struct TIM_Element { u8 Element_ID; u8 Length; u8 DTIM_Count; @@ -341,24 +323,21 @@ struct TIM_Element u8 Partial_Virtual_Bitmap[251]; }; -struct IBSS_Parameter_Set_Element -{ +struct IBSS_Parameter_Set_Element { u8 Element_ID; u8 Length; u8 ATIM_Window[2]; }; -struct Challenge_Text_Element -{ +struct Challenge_Text_Element { u8 Element_ID; u8 Length; u8 Challenge_Text[253]; }; -struct PHY_Parameter_Set_Element -{ -// int aSlotTime; -// int aSifsTime; +struct PHY_Parameter_Set_Element { +/* int aSlotTime; */ +/* int aSifsTime; */ s32 aCCATime; s32 aRxTxTurnaroundTime; s32 aTxPLCPDelay; @@ -374,18 +353,17 @@ struct PHY_Parameter_Set_Element s32 aPLCPHeaderLength; s32 aMPDUDurationFactor; s32 aMPDUMaxLength; -// int aCWmin; -// int aCWmax; +/* int aCWmin; */ +/* int aCWmax; */ }; -//-- 11G -- -struct ERP_Information_Element -{ +/* -- 11G -- */ +struct ERP_Information_Element { u8 Element_ID; u8 Length; - #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian - u8 Reserved:5; //20060926 add by anson - u8 Barker_Preamble_Mode:1; + #ifdef _BIG_ENDIAN_ /* 20060926 add by anson's endian */ + u8 Reserved:5; /* 20060926 add by anson */ + u8 Barker_Preamble_Mode:1; u8 Use_Protection:1; u8 NonERP_Present:1; #else @@ -396,54 +374,53 @@ struct ERP_Information_Element #endif }; -struct Extended_Supported_Rates_Element -{ +struct Extended_Supported_Rates_Element { u8 Element_ID; u8 Length; u8 ExtendedSupportedRates[255]; -}__attribute__ ((packed)); +} __attribute__ ((packed)); -//WPA(802.11i draft 3.0) +/* WPA(802.11i draft 3.0) */ #define VERSION_WPA 1 #ifdef _WPA2_ #define VERSION_WPA2 1 -#endif //end def _WPA2_ -#define OUI_WPA 0x00F25000 //WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type +#endif /* end def _WPA2_ */ +#define OUI_WPA 0x00F25000 /* WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type */ #ifdef _WPA2_ -#define OUI_WPA2 0x00AC0F00 // for wpa2 change to 0x00ACOF04 by Ws 26/04/04 -#endif //end def _WPA2_ +#define OUI_WPA2 0x00AC0F00 /* for wpa2 change to 0x00ACOF04 by Ws 26/04/04 */ +#endif /* end def _WPA2_ */ #define OUI_WPA_ADDITIONAL 0x01 -#define WLAN_MIN_RSN_WPA_LENGTH 6 //added by ws 09/10/04 +#define WLAN_MIN_RSN_WPA_LENGTH 6 /* added by ws 09/10/04 */ #ifdef _WPA2_ -#define WLAN_MIN_RSN_WPA2_LENGTH 2 // Fix to 2 09/14/05 -#endif //end def _WPA2_ +#define WLAN_MIN_RSN_WPA2_LENGTH 2 /* Fix to 2 09/14/05 */ +#endif /* end def _WPA2_ */ #define oui_wpa (u32)(OUI_WPA|OUI_WPA_ADDITIONAL) -#define WPA_OUI_BIG ((u32) 0x01F25000)//added by ws 09/23/04 -#define WPA_OUI_LITTLE ((u32) 0x01F25001)//added by ws 09/23/04 +#define WPA_OUI_BIG ((u32) 0x01F25000)/* added by ws 09/23/04 */ +#define WPA_OUI_LITTLE ((u32) 0x01F25001)/* added by ws 09/23/04 */ -#define WPA_WPS_OUI cpu_to_le32(0x04F25000) // 20061108 For WPS. It's little endian. Big endian is 0x0050F204 +#define WPA_WPS_OUI cpu_to_le32(0x04F25000) /* 20061108 For WPS. It's little endian. Big endian is 0x0050F204 */ -//-----WPA2----- +/* -----WPA2----- */ #ifdef _WPA2_ #define WPA2_OUI_BIG ((u32)0x01AC0F00) #define WPA2_OUI_LITTLE ((u32)0x01AC0F01) -#endif //end def _WPA2_ +#endif /* end def _WPA2_ */ -//Authentication suite -#define OUI_AUTH_WPA_NONE 0x00 //for WPA_NONE +/* Authentication suite */ +#define OUI_AUTH_WPA_NONE 0x00 /* for WPA_NONE */ #define OUI_AUTH_8021X 0x01 #define OUI_AUTH_PSK 0x02 -//Cipher suite -#define OUI_CIPHER_GROUP_KEY 0x00 //added by ws 05/21/04 +/* Cipher suite */ +#define OUI_CIPHER_GROUP_KEY 0x00 /* added by ws 05/21/04 */ #define OUI_CIPHER_WEP_40 0x01 #define OUI_CIPHER_TKIP 0x02 #define OUI_CIPHER_CCMP 0x04 #define OUI_CIPHER_WEP_104 0x05 -typedef struct _SUITE_SELECTOR_ +struct suite_selector { union { @@ -454,35 +431,35 @@ typedef struct _SUITE_SELECTOR_ u8 Type; }SuitSelector; }; -}SUITE_SELECTOR; +}; //-- WPA -- struct RSN_Information_Element { u8 Element_ID; u8 Length; - SUITE_SELECTOR OuiWPAAdditional;//WPA version 2.0 additional field, and should be 00:50:F2:01 + struct suite_selector OuiWPAAdditional; /* WPA version 2.0 additional field, and should be 00:50:F2:01 */ u16 Version; - SUITE_SELECTOR GroupKeySuite; + struct suite_selector GroupKeySuite; u16 PairwiseKeySuiteCount; - SUITE_SELECTOR PairwiseKeySuite[1]; + struct suite_selector PairwiseKeySuite[1]; }__attribute__ ((packed)); struct RSN_Auth_Sub_Information_Element { u16 AuthKeyMngtSuiteCount; - SUITE_SELECTOR AuthKeyMngtSuite[1]; + struct suite_selector AuthKeyMngtSuite[1]; }__attribute__ ((packed)); -//-- WPA2 -- +/* -- WPA2 -- */ struct RSN_Capability_Element { union { u16 __attribute__ ((packed)) wValue; - #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian + #ifdef _BIG_ENDIAN_ /* 20060927 add by anson's endian */ struct _RSN_Capability { - u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201 + u16 __attribute__ ((packed)) Reserved2 : 8; /* 20051201 */ u16 __attribute__ ((packed)) Reserved1 : 2; u16 __attribute__ ((packed)) GTK_Replay_Counter : 2; u16 __attribute__ ((packed)) PTK_Replay_Counter : 2; @@ -497,7 +474,7 @@ struct RSN_Capability_Element u16 __attribute__ ((packed)) PTK_Replay_Counter : 2; u16 __attribute__ ((packed)) GTK_Replay_Counter : 2; u16 __attribute__ ((packed)) Reserved1 : 2; - u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201 + u16 __attribute__ ((packed)) Reserved2 : 8; /* 20051201 */ }__attribute__ ((packed)) RSN_Capability; #endif @@ -505,43 +482,43 @@ struct RSN_Capability_Element }__attribute__ ((packed)) ; #ifdef _WPA2_ -typedef struct _PMKID +struct pmkid { u8 pValue[16]; -}PMKID; +}; struct WPA2_RSN_Information_Element { u8 Element_ID; u8 Length; u16 Version; - SUITE_SELECTOR GroupKeySuite; + struct suite_selector GroupKeySuite; u16 PairwiseKeySuiteCount; - SUITE_SELECTOR PairwiseKeySuite[1]; + struct suite_selector PairwiseKeySuite[1]; }__attribute__ ((packed)); struct WPA2_RSN_Auth_Sub_Information_Element { u16 AuthKeyMngtSuiteCount; - SUITE_SELECTOR AuthKeyMngtSuite[1]; + struct suite_selector AuthKeyMngtSuite[1]; }__attribute__ ((packed)); struct PMKID_Information_Element { u16 PMKID_Count; - PMKID pmkid [16] ; + struct pmkid pmkid[16]; }__attribute__ ((packed)); -#endif //enddef _WPA2_ -//============================================================ +#endif /* enddef _WPA2_ */ +/*============================================================ // MAC Frame structure (different type) and subfield structure -//============================================================ +//============================================================*/ struct MAC_frame_control { - u8 mac_frame_info; // a combination of the [Protocol Version, Control Type, Control Subtype] - #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian + u8 mac_frame_info; /* a combination of the [Protocol Version, Control Type, Control Subtype]*/ + #ifdef _BIG_ENDIAN_ /* 20060927 add by anson's endian */ u8 order:1; u8 WEP:1; u8 more_data:1; @@ -563,24 +540,24 @@ struct MAC_frame_control } __attribute__ ((packed)); struct Management_Frame { - struct MAC_frame_control frame_control; // 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0 + struct MAC_frame_control frame_control; /* 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0 */ u16 duration; - u8 DA[MAC_ADDR_LENGTH]; // Addr1 - u8 SA[MAC_ADDR_LENGTH]; // Addr2 - u8 BSSID[MAC_ADDR_LENGTH]; // Addr3 + u8 DA[MAC_ADDR_LENGTH]; /* Addr1 */ + u8 SA[MAC_ADDR_LENGTH]; /* Addr2 */ + u8 BSSID[MAC_ADDR_LENGTH]; /* Addr3 */ u16 Sequence_Control; - // Management Frame Body <= 325 bytes - // FCS 4 bytes -}__attribute__ ((packed)); + /* Management Frame Body <= 325 bytes */ + /* FCS 4 bytes */ +} __attribute__ ((packed)); -// SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it. +/* SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it. */ struct Control_Frame { - struct MAC_frame_control frame_control; // ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0 + struct MAC_frame_control frame_control; /* ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0 */ u16 duration; u8 RA[MAC_ADDR_LENGTH]; u8 TA[MAC_ADDR_LENGTH]; u16 FCS; -}__attribute__ ((packed)); +} __attribute__ ((packed)); struct Data_Frame { struct MAC_frame_control frame_control; @@ -589,32 +566,29 @@ struct Data_Frame { u8 Addr2[MAC_ADDR_LENGTH]; u8 Addr3[MAC_ADDR_LENGTH]; u16 Sequence_Control; - u8 Addr4[MAC_ADDR_LENGTH]; // only exist when ToDS=FromDS=1 - // Data Frame Body <= 2312 - // FCS -}__attribute__ ((packed)); + u8 Addr4[MAC_ADDR_LENGTH]; /* only exist when ToDS=FromDS=1 */ + /* Data Frame Body <= 2312 */ + /* FCS */ +} __attribute__ ((packed)); -struct Disassociation_Frame_Body -{ +struct Disassociation_Frame_Body { u16 reasonCode; -}__attribute__ ((packed)); +} __attribute__ ((packed)); -struct Association_Request_Frame_Body -{ +struct Association_Request_Frame_Body { u16 capability_information; u16 listenInterval; - u8 Current_AP_Address[MAC_ADDR_LENGTH];//for reassociation only - // SSID (2+32 bytes) - // Supported_Rates (2+8 bytes) -}__attribute__ ((packed)); + u8 Current_AP_Address[MAC_ADDR_LENGTH];/* for reassociation only */ + /* SSID (2+32 bytes) */ + /* Supported_Rates (2+8 bytes) */ +} __attribute__ ((packed)); -struct Association_Response_Frame_Body -{ +struct Association_Response_Frame_Body { u16 capability_information; u16 statusCode; u16 Association_ID; struct Supported_Rates_Element supportedRates; -}__attribute__ ((packed)); +} __attribute__ ((packed)); /*struct Reassociation_Request_Frame_Body { @@ -624,44 +598,40 @@ struct Association_Response_Frame_Body // SSID (2+32 bytes) // Supported_Rates (2+8 bytes) };*/ -// eliminated by WS 07/22/04 comboined with associateion request frame. +/* eliminated by WS 07/22/04 comboined with associateion request frame. */ -struct Reassociation_Response_Frame_Body -{ +struct Reassociation_Response_Frame_Body { u16 capability_information; u16 statusCode; u16 Association_ID; struct Supported_Rates_Element supportedRates; -}__attribute__ ((packed)); +} __attribute__ ((packed)); -struct Deauthentication_Frame_Body -{ +struct Deauthentication_Frame_Body { u16 reasonCode; -}__attribute__ ((packed)); +} __attribute__ ((packed)); -struct Probe_Response_Frame_Body -{ +struct Probe_Response_Frame_Body { u16 Timestamp; u16 Beacon_Interval; u16 Capability_Information; - // SSID + /* SSID // Supported_Rates // PHY parameter Set (DS Parameters) // CF parameter Set - // IBSS parameter Set -}__attribute__ ((packed)); + // IBSS parameter Set */ +} __attribute__ ((packed)); -struct Authentication_Frame_Body -{ +struct Authentication_Frame_Body { u16 algorithmNumber; u16 sequenceNumber; u16 statusCode; - // NB: don't include ChallengeText in this structure - // struct Challenge_Text_Element sChallengeTextElement; // wkchen added -}__attribute__ ((packed)); + /* NB: don't include ChallengeText in this structure + // struct Challenge_Text_Element sChallengeTextElement; // wkchen added */ +} __attribute__ ((packed)); -#endif // _MAC_Structure_H_ +#endif /* _MAC_Structure_H_ */ diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c index 37e0c185d11..e8320a6f59a 100644 --- a/drivers/staging/winbond/mds.c +++ b/drivers/staging/winbond/mds.c @@ -6,7 +6,7 @@ #include "wblinux_f.h" unsigned char -Mds_initial(struct wbsoft_priv * adapter) +Mds_initial(struct wbsoft_priv *adapter) { struct wb35_mds *pMds = &adapter->Mds; @@ -18,7 +18,7 @@ Mds_initial(struct wbsoft_priv * adapter) } void -Mds_Destroy(struct wbsoft_priv * adapter) +Mds_Destroy(struct wbsoft_priv *adapter) { } @@ -43,53 +43,53 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor pT01 = (PT01_DESCRIPTOR)(buffer+4); pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize); - if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) // +8 for USB hdr + if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) /* +8 for USB hdr */ boGroupAddr = true; - //======================================== - // Set RTS/CTS mechanism - //======================================== + /****************************************** + * Set RTS/CTS mechanism + ******************************************/ if (!boGroupAddr) { - //NOTE : If the protection mode is enabled and the MSDU will be fragmented, - // the tx rates of MPDUs will all be DSSS rates. So it will not use - // CTS-to-self in this case. CTS-To-self will only be used when without - // fragmentation. -- 20050112 - BodyLen = (u16)pT00->T00_frame_length; //include 802.11 header - BodyLen += 4; //CRC + /* NOTE : If the protection mode is enabled and the MSDU will be fragmented, + * the tx rates of MPDUs will all be DSSS rates. So it will not use + * CTS-to-self in this case. CTS-To-self will only be used when without + * fragmentation. -- 20050112 */ + BodyLen = (u16)pT00->T00_frame_length; /* include 802.11 header */ + BodyLen += 4; /* CRC */ if( BodyLen >= CURRENT_RTS_THRESHOLD ) - RTS_on = true; // Using RTS + RTS_on = true; /* Using RTS */ else { - if( pT01->T01_modulation_type ) // Is using OFDM + if( pT01->T01_modulation_type ) /* Is using OFDM */ { - if( CURRENT_PROTECT_MECHANISM ) // Is using protect - CTS_on = true; // Using CTS + if( CURRENT_PROTECT_MECHANISM ) /* Is using protect */ + CTS_on = true; /* Using CTS */ } } } if( RTS_on || CTS_on ) { - if( pT01->T01_modulation_type) // Is using OFDM + if( pT01->T01_modulation_type) /* Is using OFDM */ { - //CTS duration - // 2 SIFS + DATA transmit time + 1 ACK - // ACK Rate : 24 Mega bps - // ACK frame length = 14 bytes + /* CTS duration + * 2 SIFS + DATA transmit time + 1 ACK + * ACK Rate : 24 Mega bps + * ACK frame length = 14 bytes */ Duration = 2*DEFAULT_SIFSTIME + 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym + ((112 + 22 + 95)/96)*Tsym; } - else //DSSS + else /* DSSS */ { - //CTS duration - // 2 SIFS + DATA transmit time + 1 ACK - // Rate : ?? Mega bps - // ACK frame length = 14 bytes - if( pT01->T01_plcp_header_length ) //long preamble + /* CTS duration + * 2 SIFS + DATA transmit time + 1 ACK + * Rate : ?? Mega bps + * ACK frame length = 14 bytes */ + if( pT01->T01_plcp_header_length ) /* long preamble */ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2; else Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2; @@ -100,21 +100,21 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor if( RTS_on ) { - if( pT01->T01_modulation_type ) // Is using OFDM + if( pT01->T01_modulation_type ) /* Is using OFDM */ { - //CTS + 1 SIFS + CTS duration - //CTS Rate : 24 Mega bps - //CTS frame length = 14 bytes + /* CTS + 1 SIFS + CTS duration + * CTS Rate : 24 Mega bps + * CTS frame length = 14 bytes */ Duration += (DEFAULT_SIFSTIME + PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + ((112 + 22 + 95)/96)*Tsym); } else { - //CTS + 1 SIFS + CTS duration - //CTS Rate : ?? Mega bps - //CTS frame length = 14 bytes - if( pT01->T01_plcp_header_length ) //long preamble + /* CTS + 1 SIFS + CTS duration + * CTS Rate : ?? Mega bps + * CTS frame length = 14 bytes */ + if( pT01->T01_plcp_header_length ) /* long preamble */ Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; else Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; @@ -123,15 +123,15 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor } } - // Set the value into USB descriptor + /* Set the value into USB descriptor */ pT01->T01_add_rts = RTS_on ? 1 : 0; pT01->T01_add_cts = CTS_on ? 1 : 0; pT01->T01_rts_cts_duration = Duration; } - //===================================== - // Fill the more fragment descriptor - //===================================== + /****************************************** + * Fill the more fragment descriptor + ******************************************/ if( boGroupAddr ) Duration = 0; else @@ -139,14 +139,14 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor for( i=pDes->FragmentCount-1; i>0; i-- ) { NextBodyLen = (u16)pNextT00->T00_frame_length; - NextBodyLen += 4; //CRC + NextBodyLen += 4; /* CRC */ if( pT01->T01_modulation_type ) { - //OFDM - // data transmit time + 3 SIFS + 2 ACK - // Rate : ??Mega bps - // ACK frame length = 14 bytes, tx rate = 24M + /* OFDM + * data transmit time + 3 SIFS + 2 ACK + * Rate : ??Mega bps + * ACK frame length = 14 bytes, tx rate = 24M */ Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3; Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym + (((2*14)*8 + 22 + 95)/96)*Tsym + @@ -154,12 +154,12 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor } else { - //DSSS - // data transmit time + 2 ACK + 3 SIFS - // Rate : ??Mega bps - // ACK frame length = 14 bytes - //TODO : - if( pT01->T01_plcp_header_length ) //long preamble + /* DSSS + * data transmit time + 2 ACK + 3 SIFS + * Rate : ??Mega bps + * ACK frame length = 14 bytes + * TODO : */ + if( pT01->T01_plcp_header_length ) /* long preamble */ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3; else Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3; @@ -168,39 +168,39 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor DEFAULT_SIFSTIME*3 ); } - ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration + ((u16 *)buffer)[5] = cpu_to_le16(Duration); /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ - //----20061009 add by anson's endian + /* ----20061009 add by anson's endian */ pNextT00->value = cpu_to_le32(pNextT00->value); pT01->value = cpu_to_le32( pT01->value ); - //----end 20061009 add by anson's endian + /* ----end 20061009 add by anson's endian */ buffer += OffsetSize; pT01 = (PT01_DESCRIPTOR)(buffer+4); - if (i != 1) //The last fragment will not have the next fragment + if (i != 1) /* The last fragment will not have the next fragment */ pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize); } - //===================================== - // Fill the last fragment descriptor - //===================================== + /******************************************* + * Fill the last fragment descriptor + *******************************************/ if( pT01->T01_modulation_type ) { - //OFDM - // 1 SIFS + 1 ACK - // Rate : 24 Mega bps - // ACK frame length = 14 bytes + /* OFDM + * 1 SIFS + 1 ACK + * Rate : 24 Mega bps + * ACK frame length = 14 bytes */ Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION; - //The Tx rate of ACK use 24M + /* The Tx rate of ACK use 24M */ Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME ); } else { - // DSSS - // 1 ACK + 1 SIFS - // Rate : ?? Mega bps - // ACK frame length = 14 bytes(112 bits) - if( pT01->T01_plcp_header_length ) //long preamble + /* DSSS + * 1 ACK + 1 SIFS + * Rate : ?? Mega bps + * ACK frame length = 14 bytes(112 bits) */ + if( pT01->T01_plcp_header_length ) /* long preamble */ Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; else Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; @@ -209,14 +209,14 @@ static void Mds_DurationSet(struct wbsoft_priv *adapter, struct wb35_descriptor } } - ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration + ((u16 *)buffer)[5] = cpu_to_le16(Duration); /* 4 USHOR for skip 8B USB, 2USHORT=FC + Duration */ pT00->value = cpu_to_le32(pT00->value); pT01->value = cpu_to_le32(pT01->value); - //--end 20061009 add + /* --end 20061009 add */ } -// The function return the 4n size of usb pk +/* The function return the 4n size of usb pk */ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes, u8 *TargetBuffer) { PT00_DESCRIPTOR pT00; @@ -229,8 +229,8 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe u8 buf_index, FragmentCount = 0; - // Copy fragment body - buffer = TargetBuffer; // shift 8B usb + 24B 802.11 + /* Copy fragment body */ + buffer = TargetBuffer; /* shift 8B usb + 24B 802.11 */ SizeLeft = pDes->buffer_total_size; buf_index = pDes->buffer_start_index; @@ -240,35 +240,35 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe CopySize = SizeLeft; if (SizeLeft > pDes->FragmentThreshold) { CopySize = pDes->FragmentThreshold; - pT00->T00_frame_length = 24 + CopySize;//Set USB length + pT00->T00_frame_length = 24 + CopySize; /* Set USB length */ } else - pT00->T00_frame_length = 24 + SizeLeft;//Set USB length + pT00->T00_frame_length = 24 + SizeLeft; /* Set USB length */ SizeLeft -= CopySize; - // 1 Byte operation + /* 1 Byte operation */ pctmp = (u8 *)( buffer + 8 + DOT_11_SEQUENCE_OFFSET ); *pctmp &= 0xf0; - *pctmp |= FragmentCount;//931130.5.m + *pctmp |= FragmentCount; /* 931130.5.m */ if( !FragmentCount ) pT00->T00_first_mpdu = 1; - buffer += 32; // 8B usb + 24B 802.11 header + buffer += 32; /* 8B usb + 24B 802.11 header */ Size += 32; - // Copy into buffer + /* Copy into buffer */ stmp = CopySize + 3; - stmp &= ~0x03;//4n Alignment - Size += stmp;// Current 4n offset of mpdu + stmp &= ~0x03; /* 4n Alignment */ + Size += stmp; /* Current 4n offset of mpdu */ while (CopySize) { - // Copy body + /* Copy body */ src_buffer = pDes->buffer_address[buf_index]; CopyLeft = CopySize; if (CopySize >= pDes->buffer_size[buf_index]) { CopyLeft = pDes->buffer_size[buf_index]; - // Get the next buffer of descriptor + /* Get the next buffer of descriptor */ buf_index++; buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX; } else { @@ -283,14 +283,14 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe CopySize -= CopyLeft; } - // 931130.5.n + /* 931130.5.n */ if (pMds->MicAdd) { if (!SizeLeft) { pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd; pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd; pMds->MicAdd = 0; } - else if( SizeLeft < 8 ) //931130.5.p + else if( SizeLeft < 8 ) /* 931130.5.p */ { pMds->MicAdd = SizeLeft; pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft ); @@ -299,10 +299,10 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe } } - // Does it need to generate the new header for next mpdu? + /* Does it need to generate the new header for next mpdu? */ if (SizeLeft) { - buffer = TargetBuffer + Size; // Get the next 4n start address - memcpy( buffer, TargetBuffer, 32 );//Copy 8B USB +24B 802.11 + buffer = TargetBuffer + Size; /* Get the next 4n start address */ + memcpy( buffer, TargetBuffer, 32 ); /* Copy 8B USB +24B 802.11 */ pT00 = (PT00_DESCRIPTOR)buffer; pT00->T00_first_mpdu = 0; } @@ -312,16 +312,16 @@ static u16 Mds_BodyCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDe pT00->T00_last_mpdu = 1; pT00->T00_IsLastMpdu = 1; - buffer = (u8 *)pT00 + 8; // +8 for USB hdr - buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control - pDes->FragmentCount = FragmentCount; // Update the correct fragment number + buffer = (u8 *)pT00 + 8; /* +8 for USB hdr */ + buffer[1] &= ~0x04; /* Clear more frag bit of 802.11 frame control */ + pDes->FragmentCount = FragmentCount; /* Update the correct fragment number */ return Size; } -static void Mds_HeaderCopy(struct wbsoft_priv * adapter, struct wb35_descriptor *pDes, u8 *TargetBuffer) +static void Mds_HeaderCopy(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes, u8 *TargetBuffer) { struct wb35_mds *pMds = &adapter->Mds; - u8 *src_buffer = pDes->buffer_address[0];//931130.5.g + u8 *src_buffer = pDes->buffer_address[0]; /* 931130.5.g */ PT00_DESCRIPTOR pT00; PT01_DESCRIPTOR pT01; u16 stmp; @@ -330,44 +330,44 @@ static void Mds_HeaderCopy(struct wbsoft_priv * adapter, struct wb35_descriptor stmp = pDes->buffer_total_size; - // - // Set USB header 8 byte - // + /* + * Set USB header 8 byte + */ pT00 = (PT00_DESCRIPTOR)TargetBuffer; TargetBuffer += 4; pT01 = (PT01_DESCRIPTOR)TargetBuffer; TargetBuffer += 4; - pT00->value = 0;// Clear - pT01->value = 0;// Clear + pT00->value = 0; /* Clear */ + pT01->value = 0; /* Clear */ - pT00->T00_tx_packet_id = pDes->Descriptor_ID;// Set packet ID - pT00->T00_header_length = 24;// Set header length - pT01->T01_retry_abort_ebable = 1;//921013 931130.5.h + pT00->T00_tx_packet_id = pDes->Descriptor_ID; /* Set packet ID */ + pT00->T00_header_length = 24; /* Set header length */ + pT01->T01_retry_abort_ebable = 1; /* 921013 931130.5.h */ - // Key ID setup + /* Key ID setup */ pT01->T01_wep_id = 0; - FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; //Do not fragment - // Copy full data, the 1'st buffer contain all the data 931130.5.j - memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE );// Copy header + FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; /* Do not fragment */ + /* Copy full data, the 1'st buffer contain all the data 931130.5.j */ + memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE ); /* Copy header */ pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE; pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE; pDes->buffer_size[0] = pDes->buffer_total_size; - // Set fragment threshold + /* Set fragment threshold */ FragmentThreshold -= (DOT_11_MAC_HEADER_SIZE + 4); pDes->FragmentThreshold = FragmentThreshold; - // Set more frag bit - TargetBuffer[1] |= 0x04;// Set more frag bit + /* Set more frag bit */ + TargetBuffer[1] |= 0x04; /* Set more frag bit */ - // - // Set tx rate - // - stmp = *(u16 *)(TargetBuffer+30); // 2n alignment address + /* + * Set tx rate + */ + stmp = *(u16 *)(TargetBuffer+30); /* 2n alignment address */ - //Use basic rate + /* Use basic rate */ ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG; pDes->TxRate = ctmp1; @@ -381,10 +381,10 @@ static void Mds_HeaderCopy(struct wbsoft_priv * adapter, struct wb35_descriptor if( i == 1 ) ctmp1 = ctmpf; - pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; // backup the ta rate and fall back rate + pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; /* backup the ta rate and fall back rate */ if( ctmp1 == 108) ctmp2 = 7; - else if( ctmp1 == 96 ) ctmp2 = 6; // Rate convert for USB + else if( ctmp1 == 96 ) ctmp2 = 6; /* Rate convert for USB */ else if( ctmp1 == 72 ) ctmp2 = 5; else if( ctmp1 == 48 ) ctmp2 = 4; else if( ctmp1 == 36 ) ctmp2 = 3; @@ -394,7 +394,7 @@ static void Mds_HeaderCopy(struct wbsoft_priv * adapter, struct wb35_descriptor else if( ctmp1 == 22 ) ctmp2 = 3; else if( ctmp1 == 11 ) ctmp2 = 2; else if( ctmp1 == 4 ) ctmp2 = 1; - else ctmp2 = 0; // if( ctmp1 == 2 ) or default + else ctmp2 = 0; /* if( ctmp1 == 2 ) or default */ if( i == 0 ) pT01->T01_transmit_rate = ctmp2; @@ -402,21 +402,21 @@ static void Mds_HeaderCopy(struct wbsoft_priv * adapter, struct wb35_descriptor pT01->T01_fall_back_rate = ctmp2; } - // - // Set preamble type - // - if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) // RATE_1M + /* + * Set preamble type + */ + if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) /* RATE_1M */ pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG; else pDes->PreambleMode = CURRENT_PREAMBLE_MODE; - pT01->T01_plcp_header_length = pDes->PreambleMode; // Set preamble + pT01->T01_plcp_header_length = pDes->PreambleMode; /* Set preamble */ } void -Mds_Tx(struct wbsoft_priv * adapter) +Mds_Tx(struct wbsoft_priv *adapter) { - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; struct wb35_mds *pMds = &adapter->Mds; struct wb35_descriptor TxDes; struct wb35_descriptor *pTxDes = &TxDes; @@ -431,21 +431,21 @@ Mds_Tx(struct wbsoft_priv * adapter) if (!hal_driver_init_OK(pHwData)) return; - //Only one thread can be run here + /* Only one thread can be run here */ if (atomic_inc_return(&pMds->TxThreadCount) != 1) goto cleanup; - // Start to fill the data + /* Start to fill the data */ do { FillIndex = pMds->TxFillIndex; - if (pMds->TxOwner[FillIndex]) { // Is owned by software 0:Yes 1:No + if (pMds->TxOwner[FillIndex]) { /* Is owned by software 0:Yes 1:No */ #ifdef _PE_TX_DUMP_ printk("[Mds_Tx] Tx Owner is H/W.\n"); #endif break; } - XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); //Get buffer + XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); /* Get buffer */ XmitBufSize = 0; FillCount = 0; do { @@ -453,37 +453,37 @@ Mds_Tx(struct wbsoft_priv * adapter) if (!PacketSize) break; - //For Check the buffer resource + /* For Check the buffer resource */ FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; - //931130.5.b + /* 931130.5.b */ FragmentCount = PacketSize/FragmentThreshold + 1; - stmp = PacketSize + FragmentCount*32 + 8;//931130.5.c 8:MIC + stmp = PacketSize + FragmentCount*32 + 8; /* 931130.5.c 8:MIC */ if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) { printk("[Mds_Tx] Excess max tx buffer.\n"); - break; // buffer is not enough + break; /* buffer is not enough */ } - // - // Start transmitting - // + /* + * Start transmitting + */ BufferFilled = true; /* Leaves first u8 intact */ memset((u8 *)pTxDes + 1, 0, sizeof(struct wb35_descriptor) - 1); - TxDesIndex = pMds->TxDesIndex;//Get the current ID + TxDesIndex = pMds->TxDesIndex; /* Get the current ID */ pTxDes->Descriptor_ID = TxDesIndex; - pMds->TxDesFrom[ TxDesIndex ] = 2;//Storing the information of source comming from + pMds->TxDesFrom[ TxDesIndex ] = 2; /* Storing the information of source comming from */ pMds->TxDesIndex++; pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR; MLME_GetNextPacket( adapter, pTxDes ); - // Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type + /* Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type */ Mds_HeaderCopy( adapter, pTxDes, XmitBufAddress ); - // For speed up Key setting + /* For speed up Key setting */ if (pTxDes->EapFix) { #ifdef _PE_TX_DUMP_ printk("35: EPA 4th frame detected. Size = %d\n", PacketSize); @@ -491,41 +491,41 @@ Mds_Tx(struct wbsoft_priv * adapter) pHwData->IsKeyPreSet = 1; } - // Copy (fragment) frame body, and set USB, 802.11 hdr flag + /* Copy (fragment) frame body, and set USB, 802.11 hdr flag */ CurrentSize = Mds_BodyCopy(adapter, pTxDes, XmitBufAddress); - // Set RTS/CTS and Normal duration field into buffer + /* Set RTS/CTS and Normal duration field into buffer */ Mds_DurationSet(adapter, pTxDes, XmitBufAddress); - //Shift to the next address + /* Shift to the next address */ XmitBufSize += CurrentSize; XmitBufAddress += CurrentSize; #ifdef _IBSS_BEACON_SEQ_STICK_ - if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) // +8 for USB hdr + if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) /* +8 for USB hdr */ #endif pMds->TxToggle = true; - // Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data + /* Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data */ MLME_SendComplete(adapter, 0, true); - // Software TSC count 20060214 + /* Software TSC count 20060214 */ pMds->TxTsc++; if (pMds->TxTsc == 0) pMds->TxTsc_2++; - FillCount++; // 20060928 - } while (HAL_USB_MODE_BURST(pHwData)); // End of multiple MSDU copy loop. false = single true = multiple sending + FillCount++; /* 20060928 */ + } while (HAL_USB_MODE_BURST(pHwData)); /* End of multiple MSDU copy loop. false = single true = multiple sending */ - // Move to the next one, if necessary + /* Move to the next one, if necessary */ if (BufferFilled) { - // size setting + /* size setting */ pMds->TxBufferSize[ FillIndex ] = XmitBufSize; - // 20060928 set Tx count + /* 20060928 set Tx count */ pMds->TxCountInBuffer[FillIndex] = FillCount; - // Set owner flag + /* Set owner flag */ pMds->TxOwner[FillIndex] = 1; pMds->TxFillIndex++; @@ -534,14 +534,14 @@ Mds_Tx(struct wbsoft_priv * adapter) } else break; - if (!PacketSize) // No more pk for transmitting + if (!PacketSize) /* No more pk for transmitting */ break; } while(true); - // - // Start to send by lower module - // + /* + * Start to send by lower module + */ if (!pHwData->IsKeyPreSet) Wb35Tx_start(adapter); @@ -550,28 +550,28 @@ Mds_Tx(struct wbsoft_priv * adapter) } void -Mds_SendComplete(struct wbsoft_priv * adapter, PT02_DESCRIPTOR pT02) +Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02) { struct wb35_mds *pMds = &adapter->Mds; - struct hw_data * pHwData = &adapter->sHwData; + struct hw_data *pHwData = &adapter->sHwData; u8 PacketId = (u8)pT02->T02_Tx_PktID; unsigned char SendOK = true; u8 RetryCount, TxRate; - if (pT02->T02_IgnoreResult) // Don't care the result + if (pT02->T02_IgnoreResult) /* Don't care the result */ return; if (pT02->T02_IsLastMpdu) { - //TODO: DTO -- get the retry count and fragment count - // Tx rate + /* TODO: DTO -- get the retry count and fragment count */ + /* Tx rate */ TxRate = pMds->TxRate[ PacketId ][ 0 ]; RetryCount = (u8)pT02->T02_MPDU_Cnt; if (pT02->value & FLAG_ERROR_TX_MASK) { SendOK = false; if (pT02->T02_transmit_abort || pT02->T02_out_of_MaxTxMSDULiftTime) { - //retry error + /* retry error */ pHwData->dto_tx_retry_count += (RetryCount+1); - //[for tx debug] + /* [for tx debug] */ if (RetryCount<7) pHwData->tx_retry_count[RetryCount] += RetryCount; else @@ -583,7 +583,7 @@ Mds_SendComplete(struct wbsoft_priv * adapter, PT02_DESCRIPTOR pT02) } pHwData->dto_tx_frag_count += (RetryCount+1); - //[for tx debug] + /* [for tx debug] */ if (pT02->T02_transmit_abort_due_to_TBTT) pHwData->tx_TBTT_start_count++; if (pT02->T02_transmit_without_encryption_due_to_wep_on_false) @@ -596,7 +596,7 @@ Mds_SendComplete(struct wbsoft_priv * adapter, PT02_DESCRIPTOR pT02) MTO_SetTxCount(adapter, TxRate, RetryCount); } - // Clear send result buffer + /* Clear send result buffer */ pMds->TxResult[ PacketId ] = 0; } else pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff)); diff --git a/drivers/staging/winbond/mds_f.h b/drivers/staging/winbond/mds_f.h index e09dd4b879d..20e97bfe01e 100644 --- a/drivers/staging/winbond/mds_f.h +++ b/drivers/staging/winbond/mds_f.h @@ -4,17 +4,17 @@ #include "wbhal_s.h" #include "core.h" -unsigned char Mds_initial( struct wbsoft_priv *adapter ); -void Mds_Destroy( struct wbsoft_priv *adapter ); -void Mds_Tx( struct wbsoft_priv *adapter ); -void Mds_SendComplete( struct wbsoft_priv *adapter, PT02_DESCRIPTOR pT02 ); -void Mds_MpduProcess( struct wbsoft_priv *adapter, struct wb35_descriptor *pRxDes ); +unsigned char Mds_initial(struct wbsoft_priv *adapter); +void Mds_Destroy(struct wbsoft_priv *adapter); +void Mds_Tx(struct wbsoft_priv *adapter); +void Mds_SendComplete(struct wbsoft_priv *adapter, PT02_DESCRIPTOR pt02); +void Mds_MpduProcess(struct wbsoft_priv *adapter, struct wb35_descriptor *prxdes); extern void DataDmp(u8 *pdata, u32 len, u32 offset); -// For data frame sending 20060802 -u16 MDS_GetPacketSize( struct wbsoft_priv *adapter ); -void MDS_GetNextPacket( struct wbsoft_priv *adapter, struct wb35_descriptor *pDes ); -void MDS_GetNextPacketComplete( struct wbsoft_priv *adapter, struct wb35_descriptor *pDes ); -void MDS_SendResult( struct wbsoft_priv *adapter, u8 PacketId, unsigned char SendOK ); +/* For data frame sending */ +u16 MDS_GetPacketSize(struct wbsoft_priv *adapter); +void MDS_GetNextPacket(struct wbsoft_priv *adapter, struct wb35_descriptor *pdes); +void MDS_GetNextPacketComplete(struct wbsoft_priv *adapter, struct wb35_descriptor *pdes); +void MDS_SendResult(struct wbsoft_priv *adapter, u8 packetid, unsigned char sendok); #endif diff --git a/drivers/staging/winbond/mds_s.h b/drivers/staging/winbond/mds_s.h index 217ff0819a9..89328c5dbda 100644 --- a/drivers/staging/winbond/mds_s.h +++ b/drivers/staging/winbond/mds_s.h @@ -15,122 +15,121 @@ enum { WLAN_PREAMBLE_TYPE_LONG, }; -//////////////////////////////////////////////////////////////////////////////////////////////////////// -#define MAX_USB_TX_DESCRIPTOR 15 // IS89C35 ability -#define MAX_USB_TX_BUFFER_NUMBER 4 // Virtual pre-buffer number of MAX_USB_TX_BUFFER -#define MAX_USB_TX_BUFFER 4096 // IS89C35 ability 4n alignment is required for hardware +/*****************************************************************************/ +#define MAX_USB_TX_DESCRIPTOR 15 /* IS89C35 ability */ +#define MAX_USB_TX_BUFFER_NUMBER 4 /* Virtual pre-buffer number of MAX_USB_TX_BUFFER */ +#define MAX_USB_TX_BUFFER 4096 /* IS89C35 ability 4n alignment is required for hardware */ -#define AUTH_REQUEST_PAIRWISE_ERROR 0 // _F flag setting -#define AUTH_REQUEST_GROUP_ERROR 1 // _F flag setting +#define AUTH_REQUEST_PAIRWISE_ERROR 0 /* _F flag setting */ +#define AUTH_REQUEST_GROUP_ERROR 1 /* _F flag setting */ -#define CURRENT_FRAGMENT_THRESHOLD (adapter->Mds.TxFragmentThreshold & ~0x1) -#define CURRENT_PREAMBLE_MODE psLOCAL->boShortPreamble?WLAN_PREAMBLE_TYPE_SHORT:WLAN_PREAMBLE_TYPE_LONG -#define CURRENT_TX_RATE_FOR_MNG adapter->sLocalPara.CurrentTxRateForMng -#define CURRENT_PROTECT_MECHANISM psLOCAL->boProtectMechanism -#define CURRENT_RTS_THRESHOLD adapter->Mds.TxRTSThreshold +#define CURRENT_FRAGMENT_THRESHOLD (adapter->Mds.TxFragmentThreshold & ~0x1) +#define CURRENT_PREAMBLE_MODE (psLOCAL->boShortPreamble ? WLAN_PREAMBLE_TYPE_SHORT : WLAN_PREAMBLE_TYPE_LONG) +#define CURRENT_TX_RATE_FOR_MNG (adapter->sLocalPara.CurrentTxRateForMng) +#define CURRENT_PROTECT_MECHANISM (psLOCAL->boProtectMechanism) +#define CURRENT_RTS_THRESHOLD (adapter->Mds.TxRTSThreshold) -#define MIB_GS_XMIT_OK_INC adapter->sLocalPara.GS_XMIT_OK++ -#define MIB_GS_RCV_OK_INC adapter->sLocalPara.GS_RCV_OK++ -#define MIB_GS_XMIT_ERROR_INC adapter->sLocalPara.GS_XMIT_ERROR +#define MIB_GS_XMIT_OK_INC (adapter->sLocalPara.GS_XMIT_OK++) +#define MIB_GS_RCV_OK_INC (adapter->sLocalPara.GS_RCV_OK++) +#define MIB_GS_XMIT_ERROR_INC (adapter->sLocalPara.GS_XMIT_ERROR) -//---------- TX ----------------------------------- +/* ---------- TX ----------------------------------- */ #define ETHERNET_TX_DESCRIPTORS MAX_USB_TX_BUFFER_NUMBER -//---------- RX ------------------------------------ -#define ETHERNET_RX_DESCRIPTORS 8 //It's not necessary to allocate more than 2 in sync indicate - -//================================================================ -// Configration default value -//================================================================ -#define DEFAULT_MULTICASTLISTMAX 32 // standard -#define DEFAULT_TX_BURSTLENGTH 3 // 32 Longwords -#define DEFAULT_RX_BURSTLENGTH 3 // 32 Longwords -#define DEFAULT_TX_THRESHOLD 0 // Full Packet -#define DEFAULT_RX_THRESHOLD 0 // Full Packet -#define DEFAULT_MAXTXRATE 6 // 11 Mbps (Long) -#define DEFAULT_CHANNEL 3 // Chennel 3 -#define DEFAULT_RTSThreshold 2347 // Disable RTS -//#define DEFAULT_PME 1 // Enable -#define DEFAULT_PME 0 // Disable -#define DEFAULT_SIFSTIME 10 -#define DEFAULT_ACKTIME_1ML 304 // 148+44+112 911220 by LCC -#define DEFAULT_ACKTIME_2ML 248 // 148+44+56 911220 by LCC -#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment -#define DEFAULT_PREAMBLE_LENGTH 72 +/* ---------- RX ----------------------------------- */ +#define ETHERNET_RX_DESCRIPTORS 8 /* It's not necessary to allocate more than 2 in sync indicate */ + +/* + * ================================================================ + * Configration default value + * ================================================================ + */ +#define DEFAULT_MULTICASTLISTMAX 32 /* standard */ +#define DEFAULT_TX_BURSTLENGTH 3 /* 32 Longwords */ +#define DEFAULT_RX_BURSTLENGTH 3 /* 32 Longwords */ +#define DEFAULT_TX_THRESHOLD 0 /* Full Packet */ +#define DEFAULT_RX_THRESHOLD 0 /* Full Packet */ +#define DEFAULT_MAXTXRATE 6 /* 11 Mbps (Long) */ +#define DEFAULT_CHANNEL 3 /* Chennel 3 */ +#define DEFAULT_RTSThreshold 2347 /* Disable RTS */ +#define DEFAULT_PME 0 /* Disable */ +#define DEFAULT_SIFSTIME 10 +#define DEFAULT_ACKTIME_1ML 304 /* 148 + 44 + 112 */ +#define DEFAULT_ACKTIME_2ML 248 /* 148 + 44 + 56 */ +#define DEFAULT_FRAGMENT_THRESHOLD 2346 /* No fragment */ +#define DEFAULT_PREAMBLE_LENGTH 72 #define DEFAULT_PLCPHEADERTIME_LENGTH 24 -/*------------------------------------------------------------------------ - 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns - instead of 960 ns. This shall be fixed in the future W89C32 - -------------------------------------------------------------------------*/ -#define DEFAULT_MAX_RECEIVE_TIME 16440000 +/* + * ------------------------------------------------------------------------ + * 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns + * instead of 960 ns. This shall be fixed in the future W89C32 + * ------------------------------------------------------------------------- + */ +#define DEFAULT_MAX_RECEIVE_TIME 16440000 -#define RX_BUF_SIZE 2352 // 600 // For 301 must be multiple of 8 -#define MAX_RX_DESCRIPTORS 18 // Rx Layer 2 +#define RX_BUF_SIZE 2352 /* 600 - For 301 must be multiple of 8 */ +#define MAX_RX_DESCRIPTORS 18 /* Rx Layer 2 */ +/* For brand-new rx system */ +#define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS -// For brand-new rx system -#define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS - -// For Tx Packet status classify -#define PACKET_FREE_TO_USE 0 -#define PACKET_COME_FROM_NDIS 0x08 -#define PACKET_COME_FROM_MLME 0x80 -#define PACKET_SEND_COMPLETE 0xff +/* For Tx Packet status classify */ +#define PACKET_FREE_TO_USE 0 +#define PACKET_COME_FROM_NDIS 0x08 +#define PACKET_COME_FROM_MLME 0x80 +#define PACKET_SEND_COMPLETE 0xff struct wb35_mds { - // For Tx usage - u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ]; + /* For Tx usage */ + u8 TxOwner[((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03)]; u8 *pTxBuffer; - u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ]; - u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data - u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928 + u16 TxBufferSize[((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01)]; + u8 TxDesFrom[((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03)];/* 1: MLME 2: NDIS control 3: NDIS data */ + u8 TxCountInBuffer[((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03)]; - u8 TxFillIndex;//the next index of TxBuffer can be used - u8 TxDesIndex;//The next index of TxDes can be used - u8 ScanTxPause; //data Tx pause because the scanning is progressing, but probe request Tx won't. - u8 TxPause;//For pause the Mds_Tx modult + u8 TxFillIndex; /* the next index of TxBuffer can be used */ + u8 TxDesIndex; /* The next index of TxDes can be used */ + u8 ScanTxPause; /* data Tx pause because the scanning is progressing, but probe request Tx won't. */ + u8 TxPause; /*For pause the Mds_Tx modult */ - atomic_t TxThreadCount;//For thread counting 931130.4.v -//950301 delete due to HW -// atomic_t TxConcurrentCount;//931130.4.w + atomic_t TxThreadCount; /* For thread counting */ - u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu + u16 TxResult[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)];/* Collect the sending result of Mpdu */ - u8 MicRedundant[8]; // For tmp use - u8 *MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment + u8 MicRedundant[8]; /* For tmp use */ + u8 *MicWriteAddress[2]; /* The start address to fill the Mic, use 2 point due to Mic maybe fragment */ - u16 MicWriteSize[2]; //931130.4.x + u16 MicWriteSize[2]; - u16 MicAdd; // If want to add the Mic, this variable equal to 8 - u16 MicWriteIndex;//The number of MicWriteAddress 931130.4.y + u16 MicAdd; /* If want to add the Mic, this variable equal to 8 */ + u16 MicWriteIndex; /* The number of MicWriteAddress */ - u8 TxRate[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ][2]; // [0] current tx rate, [1] fall back rate - u8 TxInfo[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ]; //Store information for callback function + u8 TxRate[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)][2]; /* [0] current tx rate, [1] fall back rate */ + u8 TxInfo[((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01)]; /*Store information for callback function */ - //WKCHEN added for scanning mechanism - u8 TxToggle; //It is TRUE if there are tx activities in some time interval + /* for scanning mechanism */ + u8 TxToggle; /* It is TRUE if there are tx activities in some time interval */ u8 Reserved_[3]; - //---------- for Tx Parameter - u16 TxFragmentThreshold; // For frame body only + /* ---- for Tx Parameter */ + u16 TxFragmentThreshold; /* For frame body only */ u16 TxRTSThreshold; - u32 MaxReceiveTime;//911220.3 Add - - // depend on OS, - u32 MulticastListNo; - u32 PacketFilter; // Setting by NDIS, the current packet filter in use. - u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH]; + u32 MaxReceiveTime; - //COUNTERMEASURE - u8 bMICfailCount; - u8 boCounterMeasureBlock; - u8 reserved_4[2]; + /* depend on OS, */ + u32 MulticastListNo; + u32 PacketFilter; /* Setting by NDIS, the current packet filter in use. */ + u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH]; - u32 TxTsc; // 20060214 - u32 TxTsc_2; // 20060214 + /* COUNTERMEASURE */ + u8 bMICfailCount; + u8 boCounterMeasureBlock; + u8 reserved_4[2]; + u32 TxTsc; + u32 TxTsc_2; }; #endif diff --git a/drivers/staging/winbond/mlme_s.h b/drivers/staging/winbond/mlme_s.h index 1217a1c025e..a7ef3c78022 100644 --- a/drivers/staging/winbond/mlme_s.h +++ b/drivers/staging/winbond/mlme_s.h @@ -7,28 +7,29 @@ #include "mac_structures.h" #include "mds_s.h" -//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -// Mlme.h -// Define the related definitions of MLME module -// history -- 01/14/03' created -// -//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -#define AUTH_REJECT_REASON_CHALLENGE_FAIL 1 - -//====== the state of MLME module -#define INACTIVE 0x0 -#define IDLE_SCAN 0x1 - -//====== the state of MLME/ESS module -#define STATE_1 0x2 -#define AUTH_REQ 0x3 -#define AUTH_WEP 0x4 -#define STATE_2 0x5 -#define ASSOC_REQ 0x6 -#define STATE_3 0x7 - -//====== the state of MLME/IBSS module +/* + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * Mlme.h + * Define the related definitions of MLME module + * + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + */ + +#define AUTH_REJECT_REASON_CHALLENGE_FAIL 1 + +/* the state of MLME module */ +#define INACTIVE 0x0 +#define IDLE_SCAN 0x1 + +/* the state of MLME/ESS module */ +#define STATE_1 0x2 +#define AUTH_REQ 0x3 +#define AUTH_WEP 0x4 +#define STATE_2 0x5 +#define ASSOC_REQ 0x6 +#define STATE_3 0x7 + +/* the state of MLME/IBSS module */ #define IBSS_JOIN_SYNC 0x8 #define IBSS_AUTH_REQ 0x9 #define IBSS_AUTH_CHANLGE 0xa @@ -38,159 +39,150 @@ -//========================================= -//depend on D5C(MAC timing control 03 register): MaxTxMSDULifeTime default 0x80000us -#define AUTH_FAIL_TIMEOUT 550 -#define ASSOC_FAIL_TIMEOUT 550 +/* + * ========================================= + * depend on D5C(MAC timing control 03 register): + * MaxTxMSDULifeTime default 0x80000us + */ +#define AUTH_FAIL_TIMEOUT 550 +#define ASSOC_FAIL_TIMEOUT 550 #define REASSOC_FAIL_TIMEOUT 550 - - -// -// MLME task global CONSTANTS, STRUCTURE, variables -// - - -///////////////////////////////////////////////////////////// -// enum_ResultCode -- -// Result code returned from MLME to SME. -// -///////////////////////////////////////////////////////////// -// PD43 20030829 Modifiled -//#define SUCCESS 0 -#define MLME_SUCCESS 0 //follow spec. -#define INVALID_PARAMETERS 1 //Not following spec. -#define NOT_SUPPPORTED 2 -#define TIMEOUT 3 -#define TOO_MANY_SIMULTANEOUS_REQUESTS 4 -#define REFUSED 5 -#define BSS_ALREADY_STARTED_OR_JOINED 6 -#define TRANSMIT_FRAME_FAIL 7 -#define NO_BSS_FOUND 8 -#define RETRY 9 -#define GIVE_UP 10 - - -#define OPEN_AUTH 0 -#define SHARE_AUTH 1 -#define ANY_AUTH 2 -#define WPA_AUTH 3 //for WPA -#define WPAPSK_AUTH 4 -#define WPANONE_AUTH 5 -///////////////////////////////////////////// added by ws 04/19/04 +/* MLME task global CONSTANTS, STRUCTURE, variables */ + +/* ========================================= + * enum_ResultCode -- + * Result code returned from MLME to SME. + * ========================================= + */ +#define MLME_SUCCESS 0 /* follow spec. */ +#define INVALID_PARAMETERS 1 /* Not following spec. */ +#define NOT_SUPPPORTED 2 +#define TIMEOUT 3 +#define TOO_MANY_SIMULTANEOUS_REQUESTS 4 +#define REFUSED 5 +#define BSS_ALREADY_STARTED_OR_JOINED 6 +#define TRANSMIT_FRAME_FAIL 7 +#define NO_BSS_FOUND 8 +#define RETRY 9 +#define GIVE_UP 10 + + +#define OPEN_AUTH 0 +#define SHARE_AUTH 1 +#define ANY_AUTH 2 +#define WPA_AUTH 3 /* for WPA */ +#define WPAPSK_AUTH 4 +#define WPANONE_AUTH 5 #ifdef _WPA2_ -#define WPA2_AUTH 6//for WPA2 -#define WPA2PSK_AUTH 7 -#endif //end def _WPA2_ - -////////////////////////////////////////////////////////////////// -//define the msg type of MLME module -////////////////////////////////////////////////////////////////// -//-------------------------------------------------------- -//from SME - -#define MLMEMSG_AUTH_REQ 0x0b -#define MLMEMSG_DEAUTH_REQ 0x0c -#define MLMEMSG_ASSOC_REQ 0x0d -#define MLMEMSG_REASSOC_REQ 0x0e -#define MLMEMSG_DISASSOC_REQ 0x0f -#define MLMEMSG_START_IBSS_REQ 0x10 -#define MLMEMSG_IBSS_NET_CFM 0x11 - -//from RX : -#define MLMEMSG_RCV_MLMEFRAME 0x20 -#define MLMEMSG_RCV_ASSOCRSP 0x22 -#define MLMEMSG_RCV_REASSOCRSP 0x24 -#define MLMEMSG_RCV_DISASSOC 0x2b -#define MLMEMSG_RCV_AUTH 0x2c -#define MLMEMSG_RCV_DEAUTH 0x2d - - -//from TX callback -#define MLMEMSG_TX_CALLBACK 0x40 -#define MLMEMSG_ASSOCREQ_CALLBACK 0x41 -#define MLMEMSG_REASSOCREQ_CALLBACK 0x43 -#define MLMEMSG_DISASSOC_CALLBACK 0x4a -#define MLMEMSG_AUTH_CALLBACK 0x4c -#define MLMEMSG_DEAUTH_CALLBACK 0x4d - -//#define MLMEMSG_JOIN_FAIL 4 -//#define MLMEMSG_AUTHEN_FAIL 18 -#define MLMEMSG_TIMEOUT 0x50 - -/////////////////////////////////////////////////////////////////////////// -//Global data structures -#define MAX_NUM_TX_MMPDU 2 -#define MAX_MMPDU_SIZE 1512 -#define MAX_NUM_RX_MMPDU 6 - - -/////////////////////////////////////////////////////////////////////////// -//MACRO -#define boMLME_InactiveState(_AA_) (_AA_->wState==INACTIVE) -#define boMLME_IdleScanState(_BB_) (_BB_->wState==IDLE_SCAN) -#define boMLME_FoundSTAinfo(_CC_) (_CC_->wState>=IDLE_SCAN) - -typedef struct _MLME_FRAME -{ - //NDIS_PACKET MLME_Packet; - s8 * pMMPDU; - u16 len; - u8 DataType; - u8 IsInUsed; +#define WPA2_AUTH 6 /* for WPA2 */ +#define WPA2PSK_AUTH 7 +#endif /* end def _WPA2_ */ + +/* + * ========================================= + * define the msg type of MLME module + * ========================================= + */ + +/* from SME */ +#define MLMEMSG_AUTH_REQ 0x0b +#define MLMEMSG_DEAUTH_REQ 0x0c +#define MLMEMSG_ASSOC_REQ 0x0d +#define MLMEMSG_REASSOC_REQ 0x0e +#define MLMEMSG_DISASSOC_REQ 0x0f +#define MLMEMSG_START_IBSS_REQ 0x10 +#define MLMEMSG_IBSS_NET_CFM 0x11 + +/* from RX */ +#define MLMEMSG_RCV_MLMEFRAME 0x20 +#define MLMEMSG_RCV_ASSOCRSP 0x22 +#define MLMEMSG_RCV_REASSOCRSP 0x24 +#define MLMEMSG_RCV_DISASSOC 0x2b +#define MLMEMSG_RCV_AUTH 0x2c +#define MLMEMSG_RCV_DEAUTH 0x2d + + +/* from TX callback */ +#define MLMEMSG_TX_CALLBACK 0x40 +#define MLMEMSG_ASSOCREQ_CALLBACK 0x41 +#define MLMEMSG_REASSOCREQ_CALLBACK 0x43 +#define MLMEMSG_DISASSOC_CALLBACK 0x4a +#define MLMEMSG_AUTH_CALLBACK 0x4c +#define MLMEMSG_DEAUTH_CALLBACK 0x4d + +#define MLMEMSG_TIMEOUT 0x50 + +/* + * ============================================== + * Global data structures + * ============================================== + */ +#define MAX_NUM_TX_MMPDU 2 +#define MAX_MMPDU_SIZE 1512 +#define MAX_NUM_RX_MMPDU 6 + + +/* + * ============================================== + * MACRO + * ============================================== + */ +#define boMLME_InactiveState(_AA_) (_AA_->wState == INACTIVE) +#define boMLME_IdleScanState(_BB_) (_BB_->wState == IDLE_SCAN) +#define boMLME_FoundSTAinfo(_CC_) (_CC_->wState >= IDLE_SCAN) + +typedef struct _MLME_FRAME { + s8 *pMMPDU; + u16 len; + u8 DataType; + u8 IsInUsed; spinlock_t MLMESpinLock; - u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; - u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ]; + u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; + u8 TxMMPDUInUse[(MAX_NUM_TX_MMPDU + 3) & ~0x03]; u16 wNumTxMMPDU; u16 wNumTxMMPDUDiscarded; - u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE]; - u8 SaveRxBufSlotInUse[ (MAX_NUM_RX_MMPDU+3) & ~0x03 ]; + u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE]; + u8 SaveRxBufSlotInUse[(MAX_NUM_RX_MMPDU + 3) & ~0x03]; u16 wNumRxMMPDU; u16 wNumRxMMPDUDiscarded; - u16 wNumRxMMPDUInMLME; // Number of the Rx MMPDU - u16 reserved_1; // in MLME. - // excluding the discarded + u16 wNumRxMMPDUInMLME; /* Number of the Rx MMPDU */ + u16 reserved_1; /* in MLME. */ + /* excluding the discarded */ } MLME_FRAME, *psMLME_FRAME; typedef struct _AUTHREQ { - u8 peerMACaddr[MAC_ADDR_LENGTH]; - u16 wAuthAlgorithm; - + u8 peerMACaddr[MAC_ADDR_LENGTH]; + u16 wAuthAlgorithm; } MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA; typedef struct _ASSOCREQ { - u8 PeerSTAAddr[MAC_ADDR_LENGTH]; - u16 CapabilityInfo; - u16 ListenInterval; - -}__attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA; + u8 PeerSTAAddr[MAC_ADDR_LENGTH]; + u16 CapabilityInfo; + u16 ListenInterval; +} __attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA; typedef struct _REASSOCREQ { - u8 NewAPAddr[MAC_ADDR_LENGTH]; - u16 CapabilityInfo; - u16 ListenInterval; - -}__attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA; + u8 NewAPAddr[MAC_ADDR_LENGTH]; + u16 CapabilityInfo; + u16 ListenInterval; +} __attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA; typedef struct _MLMECALLBACK { - - u8 *psFramePtr; - u8 bResult; - + u8 *psFramePtr; + u8 bResult; } MLME_TXCALLBACK, *psMLME_TXCALLBACK; -typedef struct _RXDATA -{ +typedef struct _RXDATA { s32 FrameLength; - u8 __attribute__ ((packed)) *pbFramePtr; - -}__attribute__ ((packed)) RXDATA, *psRXDATA; + u8 __attribute__ ((packed)) *pbFramePtr; +} __attribute__ ((packed)) RXDATA, *psRXDATA; #endif diff --git a/drivers/staging/winbond/mlmetxrx.c b/drivers/staging/winbond/mlmetxrx.c index f856b94a781..dcd8a11b5d0 100644 --- a/drivers/staging/winbond/mlmetxrx.c +++ b/drivers/staging/winbond/mlmetxrx.c @@ -1,26 +1,26 @@ -//============================================================================ -// Module Name: -// MLMETxRx.C -// -// Description: -// The interface between MDS (MAC Data Service) and MLME. -// -// Revision History: -// -------------------------------------------------------------------------- -// 200209 UN20 Jennifer Xu -// Initial Release -// 20021108 PD43 Austin Liu -// 20030117 PD43 Austin Liu -// Deleted MLMEReturnPacket and MLMEProcThread() -// -// Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved. -//============================================================================ +/* ============================================================================ + Module Name: + MLMETxRx.C + + Description: + The interface between MDS (MAC Data Service) and MLME. + + Revision History: + -------------------------------------------------------------------------- + 200209 UN20 Jennifer Xu + Initial Release + 20021108 PD43 Austin Liu + 20030117 PD43 Austin Liu + Deleted MLMEReturnPacket and MLMEProcThread() + + Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved. +============================================================================ */ #include "sysdef.h" #include "mds_f.h" -//============================================================================= -u8 MLMESendFrame(struct wbsoft_priv * adapter, u8 *pMMPDU, u16 len, u8 DataType) +/* ============================================================================= */ +u8 MLMESendFrame(struct wbsoft_priv *adapter, u8 *pMMPDU, u16 len, u8 DataType) /* DataType : FRAME_TYPE_802_11_MANAGEMENT, FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE, FRAME_TYPE_802_11_DATA */ { @@ -30,17 +30,17 @@ u8 MLMESendFrame(struct wbsoft_priv * adapter, u8 *pMMPDU, u16 len, u8 DataType) } adapter->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME; - // Keep information for sending + /* Keep information for sending */ adapter->sMlmeFrame.pMMPDU = pMMPDU; adapter->sMlmeFrame.DataType = DataType; - // len must be the last setting due to QUERY_SIZE_SECOND of Mds + /* len must be the last setting due to QUERY_SIZE_SECOND of Mds */ adapter->sMlmeFrame.len = len; adapter->sMlmeFrame.wNumTxMMPDU++; - // H/W will enter power save by set the register. S/W don't send null frame - //with PWRMgt bit enbled to enter power save now. + /* H/W will enter power save by set the register. S/W don't send null frame + with PWRMgt bit enbled to enter power save now. */ - // Transmit NDIS packet + /* Transmit NDIS packet */ Mds_Tx(adapter); return true; } @@ -60,7 +60,7 @@ static void MLMEfreeMMPDUBuffer(struct wbsoft_priv *adapter, s8 *pData) { int i; - // Reclaim the data buffer + /* Reclaim the data buffer */ for (i = 0; i < MAX_NUM_TX_MMPDU; i++) { if (pData == (s8 *)&(adapter->sMlmeFrame.TxMMPDU[i])) break; @@ -68,24 +68,24 @@ static void MLMEfreeMMPDUBuffer(struct wbsoft_priv *adapter, s8 *pData) if (adapter->sMlmeFrame.TxMMPDUInUse[i]) adapter->sMlmeFrame.TxMMPDUInUse[i] = false; else { - // Something wrong - // PD43 Add debug code here??? + /* Something wrong + PD43 Add debug code here??? */ } } void -MLME_SendComplete(struct wbsoft_priv * adapter, u8 PacketID, unsigned char SendOK) +MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID, unsigned char SendOK) { MLME_TXCALLBACK TxCallback; - // Reclaim the data buffer + /* Reclaim the data buffer */ adapter->sMlmeFrame.len = 0; - MLMEfreeMMPDUBuffer( adapter, adapter->sMlmeFrame.pMMPDU ); + MLMEfreeMMPDUBuffer(adapter, adapter->sMlmeFrame.pMMPDU); TxCallback.bResult = MLME_SUCCESS; - // Return resource + /* Return resource */ adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE; } diff --git a/drivers/staging/winbond/mlmetxrx_f.h b/drivers/staging/winbond/mlmetxrx_f.h index 6c04e3e03e3..d1aa2617d24 100644 --- a/drivers/staging/winbond/mlmetxrx_f.h +++ b/drivers/staging/winbond/mlmetxrx_f.h @@ -1,10 +1,10 @@ -//================================================================ +/* ================================================================ // MLMETxRx.H -- // // Functions defined in MLMETxRx.c. // // Copyright (c) 2002 Winbond Electrics Corp. All Rights Reserved. -//================================================================ +//================================================================ */ #ifndef _MLMETXRX_H #define _MLMETXRX_H @@ -12,7 +12,7 @@ void MLME_GetNextPacket(struct wbsoft_priv *adapter, struct wb35_descriptor *pDes); u8 MLMESendFrame(struct wbsoft_priv *adapter, - u8 * pMMPDU, u16 len, u8 DataType); + u8 *pMMPDU, u16 len, u8 DataType); void MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID, diff --git a/drivers/staging/winbond/mto.c b/drivers/staging/winbond/mto.c index 5e7fa1cd0ae..9cd212783d6 100644 --- a/drivers/staging/winbond/mto.c +++ b/drivers/staging/winbond/mto.c @@ -1,222 +1,181 @@ -//============================================================================ -// MTO.C - -// -// Description: -// MAC Throughput Optimization for W89C33 802.11g WLAN STA. -// -// The following MIB attributes or internal variables will be affected -// while the MTO is being executed: -// dot11FragmentationThreshold, -// dot11RTSThreshold, -// transmission rate and PLCP preamble type, -// CCA mode, -// antenna diversity. -// -// Revision history: -// -------------------------------------------------------------------------- -// 20031227 UN20 Pete Chao -// First draft -// 20031229 Turbo copy from PD43 -// 20040210 Kevin revised -// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. -//============================================================================ - -// LA20040210_DTO kevin +/* + * ============================================================================ + * MTO.C - + * + * Description: + * MAC Throughput Optimization for W89C33 802.11g WLAN STA. + * + * The following MIB attributes or internal variables will be affected + * while the MTO is being executed: + * dot11FragmentationThreshold, + * dot11RTSThreshold, + * transmission rate and PLCP preamble type, + * CCA mode, + * antenna diversity. + * + * Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. + * ============================================================================ + */ + #include "sysdef.h" #include "sme_api.h" #include "wbhal_f.h" -// Declare SQ3 to rate and fragmentation threshold table -// Declare fragmentation thresholds table -#define MTO_MAX_FRAG_TH_LEVELS 5 -#define MTO_MAX_DATA_RATE_LEVELS 12 +/* Declare SQ3 to rate and fragmentation threshold table */ +/* Declare fragmentation thresholds table */ +#define MTO_MAX_FRAG_TH_LEVELS 5 +#define MTO_MAX_DATA_RATE_LEVELS 12 -u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] = -{ - 256, 384, 512, 768, 1536 +u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] = { + 256, 384, 512, 768, 1536 }; -// Declare data rate table -//The following table will be changed at anytime if the opration rate supported by AP don't -//match the table +/* + * Declare data rate table: + * The following table will be changed at anytime if the opration rate + * supported by AP don't match the table + */ static u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] = { - 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 + 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; -static int TotalTxPkt = 0; -static int TotalTxPktRetry = 0; -static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];//this record the retry rate at different data rate +static int TotalTxPkt; +static int TotalTxPktRetry; +/* this record the retry rate at different data rate */ +static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS]; -static int PeriodTotalTxPkt = 0; -static int PeriodTotalTxPktRetry = 0; +static int PeriodTotalTxPkt; +static int PeriodTotalTxPktRetry; -static u8 boSparseTxTraffic = false; +static u8 boSparseTxTraffic; void MTO_Init(struct wbsoft_priv *adapter); void TxRateReductionCtrl(struct wbsoft_priv *adapter); -/** 1.1.31.1000 Turbo modify */ void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index); void MTO_TxFailed(struct wbsoft_priv *adapter); void hal_get_dto_para(struct wbsoft_priv *adapter, char *buffer); -//=========================================================================== -// MTO_Init -- -// -// Description: -// Initialize MTO parameters. -// -// This function should be invoked during system initialization. -// -// Arguments: -// adapter - The pointer to the Miniport adapter Context -// -// Return Value: -// None -//============================================================================ +/* + * =========================================================================== + * MTO_Init -- + * + * Description: + * Initialize MTO parameters. + * + * This function should be invoked during system initialization. + * + * Arguments: + * adapter - The pointer to the Miniport adapter Context + * =========================================================================== + */ void MTO_Init(struct wbsoft_priv *adapter) { - int i; - - //[WKCHEN]MTO_CCA_MODE_SETUP()= (u8) hal_get_cca_mode(MTO_HAL()); - //[WKCHEN]MTO_CCA_MODE() = MTO_CCA_MODE_SETUP(); - - //MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_LONG; - MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; // for test - - MTO_CNT_ANT(0) = 0; - MTO_CNT_ANT(1) = 0; - MTO_SQ_ANT(0) = 0; - MTO_SQ_ANT(1) = 0; - - MTO_AGING_TIMEOUT() = 0; - - // The following parameters should be initialized to the values set by user - // - //MTO_RATE_LEVEL() = 10; - MTO_RATE_LEVEL() = 0; - MTO_FRAG_TH_LEVEL() = 4; - /** 1.1.23.1000 Turbo modify from -1 to +1 - MTO_RTS_THRESHOLD() = MTO_FRAG_TH() - 1; - MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() - 1; - */ - MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1; - MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1; - // 1.1.23.1000 Turbo add for mto change preamble from 0 to 1 - MTO_RATE_CHANGE_ENABLE() = 1; - MTO_FRAG_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag - //The default valud of ANTDIV_DEFAULT_ON will be decided by EEPROM - //#ifdef ANTDIV_DEFAULT_ON - //#else - //#endif - MTO_POWER_CHANGE_ENABLE() = 1; - MTO_PREAMBLE_CHANGE_ENABLE()= 1; - MTO_RTS_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag - // 20040512 Turbo add - //old_antenna[0] = 1; - //old_antenna[1] = 0; - //old_antenna[2] = 1; - //old_antenna[3] = 0; - for (i=0;i<MTO_MAX_DATA_RATE_LEVELS;i++) - retryrate_rec[i]=5; + int i; + + MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; /* for test */ + + MTO_CNT_ANT(0) = 0; + MTO_CNT_ANT(1) = 0; + MTO_SQ_ANT(0) = 0; + MTO_SQ_ANT(1) = 0; + + MTO_AGING_TIMEOUT() = 0; + + /* The following parameters should be initialized to the values set by user */ + MTO_RATE_LEVEL() = 0; + MTO_FRAG_TH_LEVEL() = 4; + MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1; + MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1; + MTO_RATE_CHANGE_ENABLE() = 1; + MTO_FRAG_CHANGE_ENABLE() = 0; + MTO_POWER_CHANGE_ENABLE() = 1; + MTO_PREAMBLE_CHANGE_ENABLE() = 1; + MTO_RTS_CHANGE_ENABLE() = 0; + + for (i = 0; i < MTO_MAX_DATA_RATE_LEVELS; i++) + retryrate_rec[i] = 5; MTO_TXFLOWCOUNT() = 0; - //--------- DTO threshold parameters ------------- - //MTOPARA_PERIODIC_CHECK_CYCLE() = 50; - MTOPARA_PERIODIC_CHECK_CYCLE() = 10; - MTOPARA_RSSI_TH_FOR_ANTDIV() = 10; - MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50; - MTOPARA_TXRATE_INC_TH() = 10; - MTOPARA_TXRATE_DEC_TH() = 30; - MTOPARA_TXRATE_EQ_TH() = 40; - MTOPARA_TXRATE_BACKOFF() = 12; - MTOPARA_TXRETRYRATE_REDUCE() = 6; - if ( MTO_TXPOWER_FROM_EEPROM == 0xff) - { - switch( MTO_HAL()->phy_type) - { - case RF_AIROHA_2230: - case RF_AIROHA_2230S: // 20060420 Add this - MTOPARA_TXPOWER_INDEX() = 46; // MAX-8 // @@ Only for AL 2230 - break; - case RF_AIROHA_7230: - MTOPARA_TXPOWER_INDEX() = 49; - break; - case RF_WB_242: - MTOPARA_TXPOWER_INDEX() = 10; - break; - case RF_WB_242_1: - MTOPARA_TXPOWER_INDEX() = 24; // ->10 20060316.1 modify - break; + /* --------- DTO threshold parameters ------------- */ + MTOPARA_PERIODIC_CHECK_CYCLE() = 10; + MTOPARA_RSSI_TH_FOR_ANTDIV() = 10; + MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50; + MTOPARA_TXRATE_INC_TH() = 10; + MTOPARA_TXRATE_DEC_TH() = 30; + MTOPARA_TXRATE_EQ_TH() = 40; + MTOPARA_TXRATE_BACKOFF() = 12; + MTOPARA_TXRETRYRATE_REDUCE() = 6; + if (MTO_TXPOWER_FROM_EEPROM == 0xff) { + switch (MTO_HAL()->phy_type) { + case RF_AIROHA_2230: + case RF_AIROHA_2230S: + MTOPARA_TXPOWER_INDEX() = 46; /* MAX-8 @@ Only for AL 2230 */ + break; + case RF_AIROHA_7230: + MTOPARA_TXPOWER_INDEX() = 49; + break; + case RF_WB_242: + MTOPARA_TXPOWER_INDEX() = 10; + break; + case RF_WB_242_1: + MTOPARA_TXPOWER_INDEX() = 24; + break; } - } - else //follow the setting from EEPROM + } else { /* follow the setting from EEPROM */ MTOPARA_TXPOWER_INDEX() = MTO_TXPOWER_FROM_EEPROM; - RFSynthesizer_SetPowerIndex(MTO_HAL(), (u8)MTOPARA_TXPOWER_INDEX()); - //------------------------------------------------ + } + RFSynthesizer_SetPowerIndex(MTO_HAL(), (u8) MTOPARA_TXPOWER_INDEX()); + /* ------------------------------------------------ */ - // For RSSI turning 20060808.4 Cancel load from EEPROM + /* For RSSI turning -- Cancel load from EEPROM */ MTO_DATA().RSSI_high = -41; MTO_DATA().RSSI_low = -60; } -//=========================================================================== -// Description: -// If we enable DTO, we will ignore the tx count with different tx rate from -// DTO rate. This is because when we adjust DTO tx rate, there could be some -// packets in the tx queue with previous tx rate +/* =========================================================================== + * Description: + * If we enable DTO, we will ignore the tx count with different tx rate + * from DTO rate. This is because when we adjust DTO tx rate, there could + * be some packets in the tx queue with previous tx rate + */ + void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 tx_rate, u8 index) { MTO_TXFLOWCOUNT()++; - if ((MTO_ENABLE==1) && (MTO_RATE_CHANGE_ENABLE()==1)) - { - if(tx_rate == MTO_DATA_RATE()) - { - if (index == 0) - { + if ((MTO_ENABLE == 1) && (MTO_RATE_CHANGE_ENABLE() == 1)) { + if (tx_rate == MTO_DATA_RATE()) { + if (index == 0) { if (boSparseTxTraffic) MTO_HAL()->dto_tx_frag_count += MTOPARA_PERIODIC_CHECK_CYCLE(); else MTO_HAL()->dto_tx_frag_count += 1; - } - else - { - if (index<8) - { + } else { + if (index < 8) { MTO_HAL()->dto_tx_retry_count += index; - MTO_HAL()->dto_tx_frag_count += (index+1); - } - else - { + MTO_HAL()->dto_tx_frag_count += (index + 1); + } else { MTO_HAL()->dto_tx_retry_count += 7; MTO_HAL()->dto_tx_frag_count += 7; } } - } - else if(MTO_DATA_RATE()>48 && tx_rate ==48) - {//ALFRED - if (index<3) //for reduciing data rate scheme , - //do not calcu different data rate - //3 is the reducing data rate at retry - { + } else if (MTO_DATA_RATE() > 48 && tx_rate == 48) { + /* for reducing data rate scheme, do not calculate different data rate. 3 is the reducing data rate at retry. */ + if (index < 3) { MTO_HAL()->dto_tx_retry_count += index; - MTO_HAL()->dto_tx_frag_count += (index+1); - } - else - { + MTO_HAL()->dto_tx_frag_count += (index + 1); + } else { MTO_HAL()->dto_tx_retry_count += 3; MTO_HAL()->dto_tx_frag_count += 3; } } - } - else - { + } else { MTO_HAL()->dto_tx_retry_count += index; - MTO_HAL()->dto_tx_frag_count += (index+1); + MTO_HAL()->dto_tx_frag_count += (index + 1); } - TotalTxPkt ++; - TotalTxPktRetry += (index+1); + TotalTxPkt++; + TotalTxPktRetry += (index + 1); - PeriodTotalTxPkt ++; - PeriodTotalTxPktRetry += (index+1); + PeriodTotalTxPkt++; + PeriodTotalTxPktRetry += (index + 1); } diff --git a/drivers/staging/winbond/mto.h b/drivers/staging/winbond/mto.h index fb4781d5781..a0f659cf99f 100644 --- a/drivers/staging/winbond/mto.h +++ b/drivers/staging/winbond/mto.h @@ -1,13 +1,10 @@ -//================================================================== -// MTO.H -// -// Revision history -//================================= -// 20030110 UN20 Pete Chao -// Initial Release -// -// Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. -//================================================================== +/* + * ================================================================== + * MTO.H + * + * Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. + * ================================================================== + */ #ifndef __MTO_H__ #define __MTO_H__ @@ -15,115 +12,104 @@ struct wbsoft_priv; -// LA20040210_DTO kevin -//#define MTO_PREAMBLE_LONG 0 -//#define MTO_PREAMBLE_SHORT 1 #define MTO_PREAMBLE_LONG WLAN_PREAMBLE_TYPE_LONG #define MTO_PREAMBLE_SHORT WLAN_PREAMBLE_TYPE_SHORT -//============================================================================ -// struct _MTOParameters -- -// -// Defines the parameters used in the MAC Throughput Optimization algorithm -//============================================================================ +/* Defines the parameters used in the MAC Throughput Optimization algorithm */ struct wb35_mto_params { - //--------- wkchen added ------------- - u32 TxFlowCount; //to judge what kind the tx flow(sparse or busy) is - //------------------------------------------------ + u32 TxFlowCount; /* to judge what kind the tx flow(sparse or busy) is */ - //--------- DTO threshold parameters ------------- - u16 DTO_PeriodicCheckCycle; - u16 DTO_RssiThForAntDiv; + /* --------- DTO threshold parameters ------------- */ + u16 DTO_PeriodicCheckCycle; + u16 DTO_RssiThForAntDiv; - u16 DTO_TxCountThForCalcNewRate; - u16 DTO_TxRateIncTh; + u16 DTO_TxCountThForCalcNewRate; + u16 DTO_TxRateIncTh; - u16 DTO_TxRateDecTh; - u16 DTO_TxRateEqTh; + u16 DTO_TxRateDecTh; + u16 DTO_TxRateEqTh; - u16 DTO_TxRateBackOff; - u16 DTO_TxRetryRateReduce; + u16 DTO_TxRateBackOff; + u16 DTO_TxRetryRateReduce; - u16 DTO_TxPowerIndex; //0 ~ 31 - u16 reserved_1; - //------------------------------------------------ + u16 DTO_TxPowerIndex; /* 0 ~ 31 */ + u16 reserved_1; + /* ------------------------------------------------ */ - u8 PowerChangeEnable; - u8 AntDiversityEnable; - u8 CCA_Mode; - u8 CCA_Mode_Setup; - u8 Preamble_Type; - u8 PreambleChangeEnable; + u8 PowerChangeEnable; + u8 AntDiversityEnable; + u8 CCA_Mode; + u8 CCA_Mode_Setup; + u8 Preamble_Type; + u8 PreambleChangeEnable; - u8 DataRateLevel; - u8 DataRateChangeEnable; - u8 FragThresholdLevel; - u8 FragThresholdChangeEnable; + u8 DataRateLevel; + u8 DataRateChangeEnable; + u8 FragThresholdLevel; + u8 FragThresholdChangeEnable; - u16 RTSThreshold; - u16 RTSThreshold_Setup; + u16 RTSThreshold; + u16 RTSThreshold_Setup; - u32 AvgIdleSlot; - u32 Pr_Interf; - u32 AvgGapBtwnInterf; + u32 AvgIdleSlot; + u32 Pr_Interf; + u32 AvgGapBtwnInterf; - u8 RTSChangeEnable; - u8 Ant_sel; - u8 aging_timeout; - u8 reserved_2; + u8 RTSChangeEnable; + u8 Ant_sel; + u8 aging_timeout; + u8 reserved_2; - u32 Cnt_Ant[2]; - u32 SQ_Ant[2]; + u32 Cnt_Ant[2]; + u32 SQ_Ant[2]; -// 20040510 remove from globe vairable - u8 FallbackRateLevel; - u8 OfdmRateLevel; + u8 FallbackRateLevel; + u8 OfdmRateLevel; - u8 RatePolicy; - u8 reserved_3[3]; - - // For RSSI turning - s32 RSSI_high; - s32 RSSI_low; + u8 RatePolicy; + u8 reserved_3[3]; + /* For RSSI turning */ + s32 RSSI_high; + s32 RSSI_low; }; -#define MTO_DATA() (adapter->sMtoPara) -#define MTO_HAL() (&adapter->sHwData) -#define MTO_SET_PREAMBLE_TYPE(x) // 20040511 Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x) -#define MTO_ENABLE (adapter->sLocalPara.TxRateMode == RATE_AUTO) -#define MTO_TXPOWER_FROM_EEPROM (adapter->sHwData.PowerIndexFromEEPROM) -#define LOCAL_ANTENNA_NO() (adapter->sLocalPara.bAntennaNo) -#define LOCAL_IS_CONNECTED() (adapter->sLocalPara.wConnectedSTAindex != 0) -#define MTO_INITTXRATE_MODE (adapter->sHwData.SoftwareSet&0x2) //bit 1 +#define MTO_DATA() (adapter->sMtoPara) +#define MTO_HAL() (&adapter->sHwData) +#define MTO_SET_PREAMBLE_TYPE(x) /* Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x) */ +#define MTO_ENABLE (adapter->sLocalPara.TxRateMode == RATE_AUTO) +#define MTO_TXPOWER_FROM_EEPROM (adapter->sHwData.PowerIndexFromEEPROM) +#define LOCAL_ANTENNA_NO() (adapter->sLocalPara.bAntennaNo) +#define LOCAL_IS_CONNECTED() (adapter->sLocalPara.wConnectedSTAindex != 0) +#define MTO_INITTXRATE_MODE (adapter->sHwData.SoftwareSet&0x2) /* bit 1 */ -#define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable -#define MTO_CCA_MODE() MTO_DATA().CCA_Mode -#define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup -#define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type -#define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable +#define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable +#define MTO_CCA_MODE() MTO_DATA().CCA_Mode +#define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup +#define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type +#define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable -#define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel +#define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel #define MTO_OFDM_RATE_LEVEL() MTO_DATA().OfdmRateLevel -#define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable -#define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel -#define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable -#define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold -#define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable -#define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup +#define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable +#define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel +#define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable +#define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold +#define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable +#define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup -#define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot -#define MTO_PR_INTERF() MTO_DATA().Pr_Interf -#define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf +#define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot +#define MTO_PR_INTERF() MTO_DATA().Pr_Interf +#define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf -#define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)] -#define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)] -#define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout +#define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)] +#define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)] +#define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout +#define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount -#define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount -//--------- DTO threshold parameters ------------- +/* --------- DTO threshold parameters ------------- */ #define MTOPARA_PERIODIC_CHECK_CYCLE() MTO_DATA().DTO_PeriodicCheckCycle #define MTOPARA_RSSI_TH_FOR_ANTDIV() MTO_DATA().DTO_RssiThForAntDiv #define MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() MTO_DATA().DTO_TxCountThForCalcNewRate @@ -133,13 +119,13 @@ struct wb35_mto_params { #define MTOPARA_TXRATE_BACKOFF() MTO_DATA().DTO_TxRateBackOff #define MTOPARA_TXRETRYRATE_REDUCE() MTO_DATA().DTO_TxRetryRateReduce #define MTOPARA_TXPOWER_INDEX() MTO_DATA().DTO_TxPowerIndex -//------------------------------------------------ +/* ------------------------------------------------ */ -extern u16 MTO_Frag_Th_Tbl[]; +extern u16 MTO_Frag_Th_Tbl[]; -#define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()] -#define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()] +#define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()] +#define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()] extern void MTO_Init(struct wbsoft_priv *); extern void MTO_PeriodicTimerExpired(struct wbsoft_priv *); @@ -148,6 +134,5 @@ extern u8 MTO_GetTxRate(struct wbsoft_priv *adapter, u32 fpdu_len); extern u8 MTO_GetTxFallbackRate(struct wbsoft_priv *adapter); extern void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index); -#endif //__MTO_H__ - +#endif /* __MTO_H__ */ diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c index 8c56962ab80..78935865df1 100644 --- a/drivers/staging/winbond/phy_calibration.c +++ b/drivers/staging/winbond/phy_calibration.c @@ -25,10 +25,7 @@ #define FIXED(X) ((s32)((X) * 32768.0)) #define DEG2RAD(X) 0.017453 * (X) -/****************** LOCAL TYPE DEFINITION SECTION ***************************/ -typedef s32 fixed; /* 16.16 fixed-point */ - -static const fixed Angles[]= +static const s32 Angles[] = { FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)), FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), @@ -300,7 +297,7 @@ u32 _sqrt(u32 sqsum) /****************************************************************************/ void _sin_cos(s32 angle, s32 *sin, s32 *cos) { - fixed X, Y, TargetAngle, CurrAngle; + s32 X, Y, TargetAngle, CurrAngle; unsigned Step; X=FIXED(AG_CONST); // AG_CONST * cos(0) @@ -310,7 +307,7 @@ void _sin_cos(s32 angle, s32 *sin, s32 *cos) for (Step=0; Step < 12; Step++) { - fixed NewX; + s32 NewX; if(TargetAngle > CurrAngle) { diff --git a/drivers/staging/winbond/phy_calibration.h b/drivers/staging/winbond/phy_calibration.h index 51c8fde81e2..30320314883 100644 --- a/drivers/staging/winbond/phy_calibration.h +++ b/drivers/staging/winbond/phy_calibration.h @@ -3,105 +3,82 @@ #include "wbhal_f.h" -// 20031229 Turbo add -#define REG_AGC_CTRL1 0x1000 -#define REG_AGC_CTRL2 0x1004 -#define REG_AGC_CTRL3 0x1008 -#define REG_AGC_CTRL4 0x100C -#define REG_AGC_CTRL5 0x1010 -#define REG_AGC_CTRL6 0x1014 -#define REG_AGC_CTRL7 0x1018 -#define REG_AGC_CTRL8 0x101C -#define REG_AGC_CTRL9 0x1020 -#define REG_AGC_CTRL10 0x1024 -#define REG_CCA_CTRL 0x1028 -#define REG_A_ACQ_CTRL 0x102C -#define REG_B_ACQ_CTRL 0x1030 -#define REG_A_TXRX_CTRL 0x1034 -#define REG_B_TXRX_CTRL 0x1038 -#define REG_A_TX_COEF3 0x103C -#define REG_A_TX_COEF2 0x1040 -#define REG_A_TX_COEF1 0x1044 -#define REG_B_TX_COEF2 0x1048 -#define REG_B_TX_COEF1 0x104C -#define REG_MODE_CTRL 0x1050 -#define REG_CALIB_DATA 0x1054 -#define REG_IQ_ALPHA 0x1058 -#define REG_DC_CANCEL 0x105C -#define REG_WTO_READ 0x1060 -#define REG_OFFSET_READ 0x1064 -#define REG_CALIB_READ1 0x1068 -#define REG_CALIB_READ2 0x106C -#define REG_A_FREQ_EST 0x1070 - - - - -// 20031101 Turbo add -#define MASK_AMER_OFF_REG BIT(31) - -#define MASK_BMER_OFF_REG BIT(31) - -#define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4)) -#define MASK_AGC_FIX BIT(1) - -#define MASK_AGC_FIX_GAIN 0xFF00 - -#define MASK_ADC_DC_CAL_STR BIT(10) -#define MASK_CALIB_START BIT(4) -#define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2)) -#define MASK_IQCAL_MODE (BIT(1)|BIT(0)) - -#define MASK_TX_CAL_0 0xF0000000 -#define TX_CAL_0_SHIFT 28 -#define MASK_TX_CAL_1 0x0F000000 -#define TX_CAL_1_SHIFT 24 -#define MASK_TX_CAL_2 0x00F00000 -#define TX_CAL_2_SHIFT 20 -#define MASK_TX_CAL_3 0x000F0000 -#define TX_CAL_3_SHIFT 16 -#define MASK_RX_CAL_0 0x0000F000 -#define RX_CAL_0_SHIFT 12 -#define MASK_RX_CAL_1 0x00000F00 -#define RX_CAL_1_SHIFT 8 -#define MASK_RX_CAL_2 0x000000F0 -#define RX_CAL_2_SHIFT 4 -#define MASK_RX_CAL_3 0x0000000F -#define RX_CAL_3_SHIFT 0 - -#define MASK_CANCEL_DC_I 0x3E0 -#define CANCEL_DC_I_SHIFT 5 -#define MASK_CANCEL_DC_Q 0x01F -#define CANCEL_DC_Q_SHIFT 0 - -// LA20040210 kevin -//#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9) -//#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF) -#define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9) -#define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF) - -// LA20040210 kevin (Turbo has wrong definition) -//#define MASK_IQCAL_TONE_I 0x7FFC000 -//#define SHIFT_IQCAL_TONE_I(x) ((x)>>13) -//#define MASK_IQCAL_TONE_Q 0x1FFF -//#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0) -#define MASK_IQCAL_TONE_I 0x00001FFF -#define SHIFT_IQCAL_TONE_I(x) ((x)>>0) -#define MASK_IQCAL_TONE_Q 0x03FFE000 -#define SHIFT_IQCAL_TONE_Q(x) ((x)>>13) - -// LA20040210 kevin (Turbo has wrong definition) -//#define MASK_IQCAL_IMAGE_I 0x7FFC000 -//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13) -//#define MASK_IQCAL_IMAGE_Q 0x1FFF -//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0) - -//#define MASK_IQCAL_IMAGE_I 0x00001FFF -//#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0) -//#define MASK_IQCAL_IMAGE_Q 0x03FFE000 -//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13) - -void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value ); -#define phy_init_rf( _A ) //RFSynthesizer_initial( _A ) +#define REG_AGC_CTRL1 0x1000 +#define REG_AGC_CTRL2 0x1004 +#define REG_AGC_CTRL3 0x1008 +#define REG_AGC_CTRL4 0x100C +#define REG_AGC_CTRL5 0x1010 +#define REG_AGC_CTRL6 0x1014 +#define REG_AGC_CTRL7 0x1018 +#define REG_AGC_CTRL8 0x101C +#define REG_AGC_CTRL9 0x1020 +#define REG_AGC_CTRL10 0x1024 +#define REG_CCA_CTRL 0x1028 +#define REG_A_ACQ_CTRL 0x102C +#define REG_B_ACQ_CTRL 0x1030 +#define REG_A_TXRX_CTRL 0x1034 +#define REG_B_TXRX_CTRL 0x1038 +#define REG_A_TX_COEF3 0x103C +#define REG_A_TX_COEF2 0x1040 +#define REG_A_TX_COEF1 0x1044 +#define REG_B_TX_COEF2 0x1048 +#define REG_B_TX_COEF1 0x104C +#define REG_MODE_CTRL 0x1050 +#define REG_CALIB_DATA 0x1054 +#define REG_IQ_ALPHA 0x1058 +#define REG_DC_CANCEL 0x105C +#define REG_WTO_READ 0x1060 +#define REG_OFFSET_READ 0x1064 +#define REG_CALIB_READ1 0x1068 +#define REG_CALIB_READ2 0x106C +#define REG_A_FREQ_EST 0x1070 + + +#define MASK_AMER_OFF_REG BIT(31) + +#define MASK_BMER_OFF_REG BIT(31) + +#define MASK_LNA_FIX_GAIN (BIT(3) | BIT(4)) +#define MASK_AGC_FIX BIT(1) + +#define MASK_AGC_FIX_GAIN 0xFF00 + +#define MASK_ADC_DC_CAL_STR BIT(10) +#define MASK_CALIB_START BIT(4) +#define MASK_IQCAL_TONE_SEL (BIT(3) | BIT(2)) +#define MASK_IQCAL_MODE (BIT(1) | BIT(0)) + +#define MASK_TX_CAL_0 0xF0000000 +#define TX_CAL_0_SHIFT 28 +#define MASK_TX_CAL_1 0x0F000000 +#define TX_CAL_1_SHIFT 24 +#define MASK_TX_CAL_2 0x00F00000 +#define TX_CAL_2_SHIFT 20 +#define MASK_TX_CAL_3 0x000F0000 +#define TX_CAL_3_SHIFT 16 +#define MASK_RX_CAL_0 0x0000F000 +#define RX_CAL_0_SHIFT 12 +#define MASK_RX_CAL_1 0x00000F00 +#define RX_CAL_1_SHIFT 8 +#define MASK_RX_CAL_2 0x000000F0 +#define RX_CAL_2_SHIFT 4 +#define MASK_RX_CAL_3 0x0000000F +#define RX_CAL_3_SHIFT 0 + +#define MASK_CANCEL_DC_I 0x3E0 +#define CANCEL_DC_I_SHIFT 5 +#define MASK_CANCEL_DC_Q 0x01F +#define CANCEL_DC_Q_SHIFT 0 + +#define MASK_ADC_DC_CAL_I(x) (((x) & 0x0003FE00) >> 9) +#define MASK_ADC_DC_CAL_Q(x) ((x) & 0x000001FF) + +#define MASK_IQCAL_TONE_I 0x00001FFF +#define SHIFT_IQCAL_TONE_I(x) ((x) >> 0) +#define MASK_IQCAL_TONE_Q 0x03FFE000 +#define SHIFT_IQCAL_TONE_Q(x) ((x) >> 13) + +void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value); +#define phy_init_rf(_A) /* RFSynthesizer_initial(_A) */ #endif diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c index 5f5048af26a..d9a8128b21f 100644 --- a/drivers/staging/winbond/reg.c +++ b/drivers/staging/winbond/reg.c @@ -1,514 +1,452 @@ #include "sysdef.h" #include "wbhal_f.h" -/////////////////////////////////////////////////////////////////////////////////////////////////// -// Original Phy.h -//***************************************************************************** - -/***************************************************************************** -; For MAXIM2825/6/7 Ver. 331 or more -; Edited by Tiger, Sep-17-2003 -; revised by Ben, Sep-18-2003 - -0x00 0x000a2 -0x01 0x21cc0 -;0x02 0x13802 -0x02 0x1383a - -;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333; -;channe1 02 ;0x03 0x32141 ;0x04 0x08444; -;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee; -;channe1 04 ;0x03 0x32142 ;0x04 0x0b333; -;channe1 05 ;0x03 0x31141 ;0x04 0x08444; -;channe1 06 ; -0x03 0x31143; -0x04 0x0aeee; -;channe1 07 ;0x03 0x31142 ;0x04 0x0b333; -;channe1 08 ;0x03 0x33141 ;0x04 0x08444; -;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee; -;channe1 10 ;0x03 0x33142 ;0x04 0x0b333; -;channe1 11 ;0x03 0x30941 ;0x04 0x08444; -;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee; -;channe1 13 ;0x03 0x30942 ;0x04 0x0b333; - -0x05 0x28986 -0x06 0x18008 -0x07 0x38400 -0x08 0x05100; 100 Hz DC -;0x08 0x05900; 30 KHz DC -0x09 0x24f08 -0x0a 0x17e00, 0x17ea0 -0x0b 0x37d80 -0x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000 -*****************************************************************************/ -// MAX2825 (pure b/g) -u32 max2825_rf_data[] = -{ - (0x00<<18)|0x000a2, - (0x01<<18)|0x21cc0, - (0x02<<18)|0x13806, - (0x03<<18)|0x30142, - (0x04<<18)|0x0b333, - (0x05<<18)|0x289A6, - (0x06<<18)|0x18008, - (0x07<<18)|0x38000, - (0x08<<18)|0x05100, - (0x09<<18)|0x24f08, - (0x0A<<18)|0x14000, - (0x0B<<18)|0x37d80, - (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 -}; +/* + * ==================================================== + * Original Phy.h + * ==================================================== + */ -u32 max2825_channel_data_24[][3] = -{ - {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 - {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 - {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 - {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 - {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 - {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 - {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 - {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 - {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 - {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 - {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 - {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 - {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 - {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify +/* + * ==================================================== + * For MAXIM2825/6/7 Ver. 331 or more + * + * 0x00 0x000a2 + * 0x01 0x21cc0 + * 0x02 0x13802 + * 0x02 0x1383a + * + * channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333; + * channe1 02 ; 0x03 0x32141 ; 0x04 0x08444; + * channe1 03 ; 0x03 0x32143 ; 0x04 0x0aeee; + * channe1 04 ; 0x03 0x32142 ; 0x04 0x0b333; + * channe1 05 ; 0x03 0x31141 ; 0x04 0x08444; + * channe1 06 ; 0x03 0x31143 ; 0x04 0x0aeee; + * channe1 07 ; 0x03 0x31142 ; 0x04 0x0b333; + * channe1 08 ; 0x03 0x33141 ; 0x04 0x08444; + * channe1 09 ; 0x03 0x33143 ; 0x04 0x0aeee; + * channe1 10 ; 0x03 0x33142 ; 0x04 0x0b333; + * channe1 11 ; 0x03 0x30941 ; 0x04 0x08444; + * channe1 12 ; 0x03 0x30943 ; 0x04 0x0aeee; + * channe1 13 ; 0x03 0x30942 ; 0x04 0x0b333; + * + * 0x05 0x28986 + * 0x06 0x18008 + * 0x07 0x38400 + * 0x08 0x05100; 100 Hz DC + * 0x08 0x05900; 30 KHz DC + * 0x09 0x24f08 + * 0x0a 0x17e00, 0x17ea0 + * 0x0b 0x37d80 + * 0x0c 0x0c900 -- 0x0ca00 (lager power 9db than 0x0c000), 0x0c000 + */ + +/* MAX2825 (pure b/g) */ +u32 max2825_rf_data[] = { + (0x00<<18) | 0x000a2, + (0x01<<18) | 0x21cc0, + (0x02<<18) | 0x13806, + (0x03<<18) | 0x30142, + (0x04<<18) | 0x0b333, + (0x05<<18) | 0x289A6, + (0x06<<18) | 0x18008, + (0x07<<18) | 0x38000, + (0x08<<18) | 0x05100, + (0x09<<18) | 0x24f08, + (0x0A<<18) | 0x14000, + (0x0B<<18) | 0x37d80, + (0x0C<<18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ }; -u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; - -/****************************************************************************/ -// MAX2827 (a/b/g) -u32 max2827_rf_data[] = -{ - (0x00<<18)|0x000a2, - (0x01<<18)|0x21cc0, - (0x02<<18)|0x13806, - (0x03<<18)|0x30142, - (0x04<<18)|0x0b333, - (0x05<<18)|0x289A6, - (0x06<<18)|0x18008, - (0x07<<18)|0x38000, - (0x08<<18)|0x05100, - (0x09<<18)|0x24f08, - (0x0A<<18)|0x14000, - (0x0B<<18)|0x37d80, - (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 +u32 max2825_channel_data_24[][3] = { + {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */ + {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */ + {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */ + {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 04 */ + {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 05 */ + {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 06 */ + {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 07 */ + {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 08 */ + {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 09 */ + {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 10 */ + {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 11 */ + {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 12 */ + {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 13 */ + {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ }; -u32 max2827_channel_data_24[][3] = -{ - {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 - {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 - {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 - {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 - {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 - {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 - {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 - {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 - {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 - {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 - {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 - {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 - {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 - {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify +u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; + +/* ========================================== */ +/* MAX2827 (a/b/g) */ +u32 max2827_rf_data[] = { + (0x00 << 18) | 0x000a2, + (0x01 << 18) | 0x21cc0, + (0x02 << 18) | 0x13806, + (0x03 << 18) | 0x30142, + (0x04 << 18) | 0x0b333, + (0x05 << 18) | 0x289A6, + (0x06 << 18) | 0x18008, + (0x07 << 18) | 0x38000, + (0x08 << 18) | 0x05100, + (0x09 << 18) | 0x24f08, + (0x0A << 18) | 0x14000, + (0x0B << 18) | 0x37d80, + (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ }; -u32 max2827_channel_data_50[][3] = -{ - {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36 - {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40 - {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44 - {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48 - {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52 - {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56 - {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60 - {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64 +u32 max2827_channel_data_24[][3] = { + {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */ + {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */ + {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */ + {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */ + {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */ + {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */ + {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */ + {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */ + {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */ + {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */ + {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */ + {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */ + {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */ + {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ }; -u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100}; -u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300}; - -/****************************************************************************/ -// MAX2828 (a/b/g) -u32 max2828_rf_data[] = -{ - (0x00<<18)|0x000a2, - (0x01<<18)|0x21cc0, - (0x02<<18)|0x13806, - (0x03<<18)|0x30142, - (0x04<<18)|0x0b333, - (0x05<<18)|0x289A6, - (0x06<<18)|0x18008, - (0x07<<18)|0x38000, - (0x08<<18)|0x05100, - (0x09<<18)|0x24f08, - (0x0A<<18)|0x14000, - (0x0B<<18)|0x37d80, - (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 +u32 max2827_channel_data_50[][3] = { + {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */ + {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */ + {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */ + {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2A9A6}, /* channel 48 */ + {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x2A9A6}, /* channel 52 */ + {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 56 */ + {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 60 */ + {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6} /* channel 64 */ }; -u32 max2828_channel_data_24[][3] = -{ - {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 - {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 - {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 - {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 - {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 - {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 - {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 - {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 - {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 - {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 - {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 - {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 - {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 - {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify +u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100}; +u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300}; + +/* ======================================================= */ +/* MAX2828 (a/b/g) */ +u32 max2828_rf_data[] = { + (0x00 << 18) | 0x000a2, + (0x01 << 18) | 0x21cc0, + (0x02 << 18) | 0x13806, + (0x03 << 18) | 0x30142, + (0x04 << 18) | 0x0b333, + (0x05 << 18) | 0x289A6, + (0x06 << 18) | 0x18008, + (0x07 << 18) | 0x38000, + (0x08 << 18) | 0x05100, + (0x09 << 18) | 0x24f08, + (0x0A << 18) | 0x14000, + (0x0B << 18) | 0x37d80, + (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */ }; -u32 max2828_channel_data_50[][3] = -{ - {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36 - {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40 - {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44 - {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48 - {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52 - {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56 - {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60 - {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64 +u32 max2828_channel_data_24[][3] = { + {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */ + {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */ + {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */ + {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */ + {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */ + {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */ + {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */ + {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */ + {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */ + {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */ + {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */ + {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */ + {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */ + {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */ }; -u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; -u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; - -/****************************************************************************/ -// LA20040728 kevin -// MAX2829 (a/b/g) -u32 max2829_rf_data[] = -{ - (0x00<<18)|0x000a2, - (0x01<<18)|0x23520, - (0x02<<18)|0x13802, - (0x03<<18)|0x30142, - (0x04<<18)|0x0b333, - (0x05<<18)|0x28906, - (0x06<<18)|0x18008, - (0x07<<18)|0x3B500, - (0x08<<18)|0x05100, - (0x09<<18)|0x24f08, - (0x0A<<18)|0x14000, - (0x0B<<18)|0x37d80, - (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB) +u32 max2828_channel_data_50[][3] = { + {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */ + {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */ + {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */ + {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}, /* channel 48 */ + {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x289A6}, /* channel 52 */ + {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 56 */ + {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 60 */ + {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6} /* channel 64 */ }; -u32 max2829_channel_data_24[][3] = -{ - {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz) - {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz) - {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz) - {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz) - {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz) - {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz) - {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz) - {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz) - {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz) - {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz) - {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz) - {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz) - {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz) - {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify +u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; +u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; + +/* ========================================================== */ +/* MAX2829 (a/b/g) */ +u32 max2829_rf_data[] = { + (0x00 << 18) | 0x000a2, + (0x01 << 18) | 0x23520, + (0x02 << 18) | 0x13802, + (0x03 << 18) | 0x30142, + (0x04 << 18) | 0x0b333, + (0x05 << 18) | 0x28906, + (0x06 << 18) | 0x18008, + (0x07 << 18) | 0x3B500, + (0x08 << 18) | 0x05100, + (0x09 << 18) | 0x24f08, + (0x0A << 18) | 0x14000, + (0x0B << 18) | 0x37d80, + (0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */ }; -u32 max2829_channel_data_50[][4] = -{ - {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz) - {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz) - {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz) - {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz) - {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz) - {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz) - {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz) - {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz) - - {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz) - {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz) - {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz) - {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz) - {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz) - {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz) - {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz) - {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz) - {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz) - {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz) - {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz) - - {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz) - {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz) - {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz) - {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz) - - // Japan - { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz) - { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz) - { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz) - { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz) - { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz) - { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz) - { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz) - { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz) - { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz) - { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz) - { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz) +u32 max2829_channel_data_24[][3] = { + {(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 01 (2412MHz) */ + {(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 02 (2417MHz) */ + {(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 03 (2422MHz) */ + {(3 << 18) | 0x32142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 04 (2427MHz) */ + {(3 << 18) | 0x31141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 05 (2432MHz) */ + {(3 << 18) | 0x31143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 06 (2437MHz) */ + {(3 << 18) | 0x31142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 07 (2442MHz) */ + {(3 << 18) | 0x33141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 08 (2447MHz) */ + {(3 << 18) | 0x33143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 09 (2452MHz) */ + {(3 << 18) | 0x33142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 10 (2457MHz) */ + {(3 << 18) | 0x30941, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 11 (2462MHz) */ + {(3 << 18) | 0x30943, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 12 (2467MHz) */ + {(3 << 18) | 0x30942, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 13 (2472MHz) */ + {(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6}, /* 14 (2484MHz) */ }; -/***************************************************************************** -; For MAXIM2825/6/7 Ver. 317 or less -; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels -; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels -; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels - -0x00 0x00080 -0x01 0x214c0 -0x02 0x13802 - -;2.4GHz Channels -;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc -;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111 -;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb -;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc -;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111 -;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb -;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc -;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111 -;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb -;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc -;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111 -;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb -;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc - -;5.0Ghz Channels -;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333 -;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000 -;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333 -;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999 -;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666 -;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc -;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000 -;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333 - -;2.4GHz band ;0x05 0x28986; -;5.0GHz band -0x05 0x2a986 - -0x06 0x18008 -0x07 0x38400 -0x08 0x05108 -0x09 0x27ff8 -0x0a 0x14000 -0x0b 0x37f99 -0x0c 0x0c000 -*****************************************************************************/ -u32 maxim_317_rf_data[] = -{ - (0x00<<18)|0x000a2, - (0x01<<18)|0x214c0, - (0x02<<18)|0x13802, - (0x03<<18)|0x30143, - (0x04<<18)|0x0accc, - (0x05<<18)|0x28986, - (0x06<<18)|0x18008, - (0x07<<18)|0x38400, - (0x08<<18)|0x05108, - (0x09<<18)|0x27ff8, - (0x0A<<18)|0x14000, - (0x0B<<18)|0x37f99, - (0x0C<<18)|0x0c000 +u32 max2829_channel_data_50[][4] = { + {36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */ + {40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */ + {44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */ + {48, (3 << 18) | 0x322c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 48 (5.240GHz) */ + {52, (3 << 18) | 0x312c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 52 (5.260GHz) */ + {56, (3 << 18) | 0x332c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 56 (5.280GHz) */ + {60, (3 << 18) | 0x30ac0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 60 (5.300GHz) */ + {64, (3 << 18) | 0x30ac2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 64 (5.320GHz) */ + + {100, (3 << 18) | 0x30ec0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 100 (5.500GHz) */ + {104, (3 << 18) | 0x30ec2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 104 (5.520GHz) */ + {108, (3 << 18) | 0x32ec1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 108 (5.540GHz) */ + {112, (3 << 18) | 0x31ec1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 112 (5.560GHz) */ + {116, (3 << 18) | 0x33ec3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 116 (5.580GHz) */ + {120, (3 << 18) | 0x301c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 120 (5.600GHz) */ + {124, (3 << 18) | 0x301c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 124 (5.620GHz) */ + {128, (3 << 18) | 0x321c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 128 (5.640GHz) */ + {132, (3 << 18) | 0x311c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 132 (5.660GHz) */ + {136, (3 << 18) | 0x331c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 136 (5.680GHz) */ + {140, (3 << 18) | 0x309c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 140 (5.700GHz) */ + + {149, (3 << 18) | 0x329c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 149 (5.745GHz) */ + {153, (3 << 18) | 0x319c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 153 (5.765GHz) */ + {157, (3 << 18) | 0x339c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 157 (5.785GHz) */ + {161, (3 << 18) | 0x305c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 161 (5.805GHz) */ + + /* Japan */ + { 184, (3 << 18) | 0x308c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 184 (4.920GHz) */ + { 188, (3 << 18) | 0x328c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 188 (4.940GHz) */ + { 192, (3 << 18) | 0x318c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 192 (4.960GHz) */ + { 196, (3 << 18) | 0x338c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 196 (4.980GHz) */ + { 8, (3 << 18) | 0x324c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 8 (5.040GHz) */ + { 12, (3 << 18) | 0x314c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 12 (5.060GHz) */ + { 16, (3 << 18) | 0x334c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 16 (5.080GHz) */ + { 34, (3 << 18) | 0x31cc2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 34 (5.170GHz) */ + { 38, (3 << 18) | 0x33cc1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 38 (5.190GHz) */ + { 42, (3 << 18) | 0x302c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 42 (5.210GHz) */ + { 46, (3 << 18) | 0x322c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 46 (5.230GHz) */ }; -u32 maxim_317_channel_data_24[][3] = -{ - {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01 - {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02 - {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03 - {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04 - {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05 - {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06 - {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07 - {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08 - {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09 - {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10 - {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11 - {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12 - {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13 +/* + * ==================================================================== + * For MAXIM2825/6/7 Ver. 317 or less + * + * 0x00 0x00080 + * 0x01 0x214c0 + * 0x02 0x13802 + * + * 2.4GHz Channels + * channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc + * channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111 + * channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb + * channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc + * channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111 + * channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb + * channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc + * channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111 + * channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb + * channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc + * channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111 + * channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb + * channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc + * + * 5.0Ghz Channels + * channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333 + * channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000 + * channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333 + * channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999 + * channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666 + * channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc + * channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000 + * channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333 + * + * 2.4GHz band ; 0x05 0x28986; + * 5.0GHz band ; 0x05 0x2a986 + * 0x06 0x18008 + * 0x07 0x38400 + * 0x08 0x05108 + * 0x09 0x27ff8 + * 0x0a 0x14000 + * 0x0b 0x37f99 + * 0x0c 0x0c000 + * ==================================================================== + */ +u32 maxim_317_rf_data[] = { + (0x00 << 18) | 0x000a2, + (0x01 << 18) | 0x214c0, + (0x02 << 18) | 0x13802, + (0x03 << 18) | 0x30143, + (0x04 << 18) | 0x0accc, + (0x05 << 18) | 0x28986, + (0x06 << 18) | 0x18008, + (0x07 << 18) | 0x38400, + (0x08 << 18) | 0x05108, + (0x09 << 18) | 0x27ff8, + (0x0A << 18) | 0x14000, + (0x0B << 18) | 0x37f99, + (0x0C << 18) | 0x0c000 }; -u32 maxim_317_channel_data_50[][3] = -{ - {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36 - {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40 - {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44 - {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48 - {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52 - {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56 - {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60 - {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64 +u32 maxim_317_channel_data_24[][3] = { + {(0x03 << 18) | 0x30143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 01 */ + {(0x03 << 18) | 0x32140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 02 */ + {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 03 */ + {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 04 */ + {(0x03 << 18) | 0x31140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 05 */ + {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 06 */ + {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 07 */ + {(0x03 << 18) | 0x33140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 08 */ + {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 09 */ + {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 10 */ + {(0x03 << 18) | 0x30940, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 11 */ + {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 12 */ + {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986} /* channe1 13 */ }; -u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; -u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; - -/***************************************************************************** -;;AL2230 MP (Mass Production Version) -;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004 -;;Updated by Tiger Huang (June 1st, 2004) -;;20-bit length and LSB first - -;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC; -;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD; -;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC; -;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD; -;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC; -;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD; -;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC; -;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD; -;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC; -;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD; -;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC; -;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD; -;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC; -;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666; - -0x02 0x401D8; RXDCOC BW 100Hz for RXHP low -;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low - -0x03 0xCFFF0 -0x04 0x23800 -0x05 0xA3B72 -0x06 0x6DA01 -0x07 0xE1688 -0x08 0x11600 -0x09 0x99E02 -0x0A 0x5DDB0 -0x0B 0xD9900 -0x0C 0x3FFBD -0x0D 0xB0000 -0x0F 0xF00A0 - -;RF Calibration for Airoha AL2230 -;Edit by Ben Chang (01/30/04) -;Updated by Tiger Huang (03/03/04) -0x0f 0xf00a0 ; Initial Setting -0x0f 0xf00b0 ; Activate TX DCC -0x0f 0xf02a0 ; Activate Phase Calibration -0x0f 0xf00e0 ; Activate Filter RC Calibration -0x0f 0xf00a0 ; Restore Initial Setting -*****************************************************************************/ - -u32 al2230_rf_data[] = -{ - (0x00<<20)|0x09EFC, - (0x01<<20)|0x8CCCC, - (0x02<<20)|0x40058,// 20060627 Anson 0x401D8, - (0x03<<20)|0xCFFF0, - (0x04<<20)|0x24100,// 20060627 Anson 0x23800, - (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72 - (0x06<<20)|0x6DA01, - (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688, - (0x08<<20)|0x11600, - (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02 - (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth - (0x0B<<20)|0xD9900, - (0x0C<<20)|0x3FFBD, - (0x0D<<20)|0xB0000, - (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0 +u32 maxim_317_channel_data_50[][3] = { + {(0x03 << 18) | 0x33cc0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a986}, /* channel 36 */ + {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a986}, /* channel 40 */ + {(0x03 << 18) | 0x302c3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a986}, /* channel 44 */ + {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09666, (0x05 << 18) | 0x2a986}, /* channel 48 */ + {(0x03 << 18) | 0x312c2, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2a986}, /* channel 52 */ + {(0x03 << 18) | 0x332c0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a99e}, /* channel 56 */ + {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a99e}, /* channel 60 */ + {(0x03 << 18) | 0x30ac3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a99e} /* channel 64 */ }; -u32 al2230s_rf_data[] = -{ - (0x00<<20)|0x09EFC, - (0x01<<20)|0x8CCCC, - (0x02<<20)|0x40058,// 20060419 0x401D8, - (0x03<<20)|0xCFFF0, - (0x04<<20)|0x24100,// 20060419 0x23800, - (0x05<<20)|0xA3B2F,// 20060419 0xA3B72, - (0x06<<20)|0x6DA01, - (0x07<<20)|0xE3628,// 20060419 0xE1688, - (0x08<<20)|0x11600, - (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02 - (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth - (0x0B<<20)|0xD9900, - (0x0C<<20)|0x3FFBD, - (0x0D<<20)|0xB0000, - (0x0F<<20)|0xF01A0 // 20060419 0xF00A0 +u32 maxim_317_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; +u32 maxim_317_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100}; + +/* + * =================================================================== + * AL2230 MP (Mass Production Version) + * RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004 + * 20-bit length and LSB first + * + * Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC; + * Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD; + * Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC; + * Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD; + * Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC; + * Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD; + * Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC; + * Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD; + * Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC; + * Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD; + * Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC; + * Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD; + * Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC; + * Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666; + * + * 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low + * 0x02 0x481DC; RXDCOC BW 30Khz for RXHP low + * + * 0x03 0xCFFF0 + * 0x04 0x23800 + * 0x05 0xA3B72 + * 0x06 0x6DA01 + * 0x07 0xE1688 + * 0x08 0x11600 + * 0x09 0x99E02 + * 0x0A 0x5DDB0 + * 0x0B 0xD9900 + * 0x0C 0x3FFBD + * 0x0D 0xB0000 + * 0x0F 0xF00A0 + * + * RF Calibration for Airoha AL2230 + * + * 0x0f 0xf00a0 ; Initial Setting + * 0x0f 0xf00b0 ; Activate TX DCC + * 0x0f 0xf02a0 ; Activate Phase Calibration + * 0x0f 0xf00e0 ; Activate Filter RC Calibration + * 0x0f 0xf00a0 ; Restore Initial Setting + * ================================================================== + */ +u32 al2230_rf_data[] = { + (0x00 << 20) | 0x09EFC, + (0x01 << 20) | 0x8CCCC, + (0x02 << 20) | 0x40058, + (0x03 << 20) | 0xCFFF0, + (0x04 << 20) | 0x24100, + (0x05 << 20) | 0xA3B2F, + (0x06 << 20) | 0x6DA01, + (0x07 << 20) | 0xE3628, + (0x08 << 20) | 0x11600, + (0x09 << 20) | 0x9DC02, + (0x0A << 20) | 0x5ddb0, + (0x0B << 20) | 0xD9900, + (0x0C << 20) | 0x3FFBD, + (0x0D << 20) | 0xB0000, + (0x0F << 20) | 0xF01A0 }; -u32 al2230_channel_data_24[][2] = -{ - {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01 - {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02 - {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03 - {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04 - {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05 - {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06 - {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07 - {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08 - {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09 - {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10 - {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11 - {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12 - {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13 - {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14 +u32 al2230s_rf_data[] = { + (0x00 << 20) | 0x09EFC, + (0x01 << 20) | 0x8CCCC, + (0x02 << 20) | 0x40058, + (0x03 << 20) | 0xCFFF0, + (0x04 << 20) | 0x24100, + (0x05 << 20) | 0xA3B2F, + (0x06 << 20) | 0x6DA01, + (0x07 << 20) | 0xE3628, + (0x08 << 20) | 0x11600, + (0x09 << 20) | 0x9DC02, + (0x0A << 20) | 0x5DDB0, + (0x0B << 20) | 0xD9900, + (0x0C << 20) | 0x3FFBD, + (0x0D << 20) | 0xB0000, + (0x0F << 20) | 0xF01A0 }; -// Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602}; -#define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202 -#define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602 -#define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0 -/* -u32 airoha_power_data_24[] = -{ - 0x9FE02, // Max - 0 dB - 0x9BE02, // Max - 1 dB - 0x9DE02, // Max - 2 dB - 0x99E02, // Max - 3 dB - 0x9EE02, // Max - 4 dB - 0x9AE02, // Max - 5 dB - 0x9CE02, // Max - 6 dB - 0x98E02, // Max - 7 dB - 0x97602, // Max - 8 dB - 0x93602, // Max - 9 dB - 0x95602, // Max - 10 dB - 0x91602, // Max - 11 dB - 0x96602, // Max - 12 dB - 0x92602, // Max - 13 dB - 0x94602, // Max - 14 dB - 0x90602, // Max - 15 dB - 0x97A02, // Max - 16 dB - 0x93A02, // Max - 17 dB - 0x95A02, // Max - 18 dB - 0x91A02, // Max - 19 dB - 0x96A02, // Max - 20 dB - 0x92A02, // Max - 21 dB - 0x94A02, // Max - 22 dB - 0x90A02, // Max - 23 dB - 0x97202, // Max - 24 dB - 0x93202, // Max - 25 dB - 0x95202, // Max - 26 dB - 0x91202, // Max - 27 dB - 0x96202, // Max - 28 dB - 0x92202, // Max - 29 dB - 0x94202, // Max - 30 dB - 0x90202 // Max - 31 dB +u32 al2230_channel_data_24[][2] = { + {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */ + {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */ + {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */ + {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 04 */ + {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 05 */ + {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 06 */ + {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 07 */ + {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 08 */ + {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCC}, /* channe1 09 */ + {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCD}, /* channe1 10 */ + {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCC}, /* channe1 11 */ + {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCD}, /* channe1 12 */ + {(0x00 << 20) | 0x03EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 13 */ + {(0x00 << 20) | 0x03E7C, (0x01 << 20) | 0x86666} /* channe1 14 */ }; -*/ -// 20040927 1.1.69.1000 ybjiang -// from John -u32 al2230_txvga_data[][2] = -{ - //value , index +/* Current setting. u32 airoha_power_data_24[] = {(0x09 << 20) | 0x90202, (0x09 << 20) | 0x96602, (0x09 << 20) | 0x97602}; */ +#define AIROHA_TXVGA_LOW_INDEX 31 /* Index for 0x90202 */ +#define AIROHA_TXVGA_MIDDLE_INDEX 12 /* Index for 0x96602 */ +#define AIROHA_TXVGA_HIGH_INDEX 8 /* Index for 0x97602 1.0.24.0 1.0.28.0 */ + +u32 al2230_txvga_data[][2] = { + /* value , index */ {0x090202, 0}, {0x094202, 2}, {0x092202, 4}, @@ -551,263 +489,242 @@ u32 al2230_txvga_data[][2] = {0x09FE02, 63} }; -//-------------------------------- -// For Airoha AL7230, 2.4Ghz band -// Edit by Tiger, (March, 9, 2005) -// 24bit, MSB first - -//channel independent registers: -u32 al7230_rf_data_24[] = -{ - (0x00<<24)|0x003790, - (0x01<<24)|0x133331, - (0x02<<24)|0x841FF2, - (0x03<<24)|0x3FDFA3, - (0x04<<24)|0x7FD784, - (0x05<<24)|0x802B55, - (0x06<<24)|0x56AF36, - (0x07<<24)|0xCE0207, - (0x08<<24)|0x6EBC08, - (0x09<<24)|0x221BB9, - (0x0A<<24)|0xE0000A, - (0x0B<<24)|0x08071B, - (0x0C<<24)|0x000A3C, - (0x0D<<24)|0xFFFFFD, - (0x0E<<24)|0x00000E, - (0x0F<<24)|0x1ABA8F +/* + * ========================================== + * For Airoha AL7230, 2.4Ghz band + * 24bit, MSB first + */ + +/* channel independent registers: */ +u32 al7230_rf_data_24[] = { + (0x00 << 24) | 0x003790, + (0x01 << 24) | 0x133331, + (0x02 << 24) | 0x841FF2, + (0x03 << 24) | 0x3FDFA3, + (0x04 << 24) | 0x7FD784, + (0x05 << 24) | 0x802B55, + (0x06 << 24) | 0x56AF36, + (0x07 << 24) | 0xCE0207, + (0x08 << 24) | 0x6EBC08, + (0x09 << 24) | 0x221BB9, + (0x0A << 24) | 0xE0000A, + (0x0B << 24) | 0x08071B, + (0x0C << 24) | 0x000A3C, + (0x0D << 24) | 0xFFFFFD, + (0x0E << 24) | 0x00000E, + (0x0F << 24) | 0x1ABA8F }; -u32 al7230_channel_data_24[][2] = -{ - {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01 - {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02 - {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03 - {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04 - {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05 - {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06 - {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07 - {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08 - {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09 - {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10 - {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11 - {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12 - {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13 - {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14 +u32 al7230_channel_data_24[][2] = { + {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */ + {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */ + {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */ + {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x0B3331}, /* channe1 04 */ + {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x133331}, /* channe1 05 */ + {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x1B3331}, /* channe1 06 */ + {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x033331}, /* channe1 07 */ + {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x0B3331}, /* channe1 08 */ + {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x133331}, /* channe1 09 */ + {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x1B3331}, /* channe1 10 */ + {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x033331}, /* channe1 11 */ + {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x0B3331}, /* channe1 12 */ + {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x133331}, /* channe1 13 */ + {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x066661} /* channel 14 */ }; -//channel independent registers: -u32 al7230_rf_data_50[] = -{ - (0x00<<24)|0x0FF520, - (0x01<<24)|0x000001, - (0x02<<24)|0x451FE2, - (0x03<<24)|0x5FDFA3, - (0x04<<24)|0x6FD784, - (0x05<<24)|0x853F55, - (0x06<<24)|0x56AF36, - (0x07<<24)|0xCE0207, - (0x08<<24)|0x6EBC08, - (0x09<<24)|0x221BB9, - (0x0A<<24)|0xE0600A, - (0x0B<<24)|0x08044B, - (0x0C<<24)|0x00143C, - (0x0D<<24)|0xFFFFFD, - (0x0E<<24)|0x00000E, - (0x0F<<24)|0x12BACF //5Ghz default state +/* channel independent registers: */ +u32 al7230_rf_data_50[] = { + (0x00 << 24) | 0x0FF520, + (0x01 << 24) | 0x000001, + (0x02 << 24) | 0x451FE2, + (0x03 << 24) | 0x5FDFA3, + (0x04 << 24) | 0x6FD784, + (0x05 << 24) | 0x853F55, + (0x06 << 24) | 0x56AF36, + (0x07 << 24) | 0xCE0207, + (0x08 << 24) | 0x6EBC08, + (0x09 << 24) | 0x221BB9, + (0x0A << 24) | 0xE0600A, + (0x0B << 24) | 0x08044B, + (0x0C << 24) | 0x00143C, + (0x0D << 24) | 0xFFFFFD, + (0x0E << 24) | 0x00000E, + (0x0F << 24) | 0x12BACF /* 5Ghz default state */ }; -u32 al7230_channel_data_5[][4] = -{ - //channel dependent registers: 0x00, 0x01 and 0x04 - //11J =========== - {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184 - {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188 - {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192 - {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196 - {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008 - {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012 - {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016 - {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034 - {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038 - {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042 - {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046 - //11 A/H ========= - {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036 - {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040 - {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044 - {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048 - {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052 - {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056 - {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060 - {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064 - {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100 - {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104 - {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108 - {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112 - {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116 - {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120 - {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124 - {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128 - {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132 - {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136 - {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140 - {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149 - {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153 - {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157 - {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161 - {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165 +u32 al7230_channel_data_5[][4] = { + /* channel dependent registers: 0x00, 0x01 and 0x04 */ + /* 11J =========== */ + {184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */ + {188, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 188 */ + {192, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 192 */ + {196, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 196 */ + {8, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 008 */ + {12, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 012 */ + {16, (0x00 << 24) | 0x0FF550, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 016 */ + {34, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 034 */ + {38, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x100001, (0x04 << 24) | 0x77F784}, /* channel 038 */ + {42, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x1AAAA1, (0x04 << 24) | 0x77F784}, /* channel 042 */ + {46, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 046 */ + /* 11 A/H ========= */ + {36, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 036 */ + {40, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 040 */ + {44, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 044 */ + {48, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 048 */ + {52, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 052 */ + {56, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 056 */ + {60, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 060 */ + {64, (0x00 << 24) | 0x0FF590, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 064 */ + {100, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 100 */ + {104, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 104 */ + {108, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 108 */ + {112, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 112 */ + {116, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 116 */ + {120, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 120 */ + {124, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 124 */ + {128, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 128 */ + {132, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 132 */ + {136, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 136 */ + {140, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 140 */ + {149, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 149 */ + {153, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784}, /* channel 153 */ + {157, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x0D5551, (0x04 << 24) | 0x77F784}, /* channel 157 */ + {161, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 161 */ + {165, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784} /* channel 165 */ }; -//; RF Calibration <=== Register 0x0F -//0x0F 0x1ABA8F; start from 2.4Ghz default state -//0x0F 0x9ABA8F; TXDC compensation -//0x0F 0x3ABA8F; RXFIL adjustment -//0x0F 0x1ABA8F; restore 2.4Ghz default state - -//;TXVGA Mapping Table <=== Register 0x0B -u32 al7230_txvga_data[][2] = -{ - {0x08040B, 0}, //TXVGA=0; - {0x08041B, 1}, //TXVGA=1; - {0x08042B, 2}, //TXVGA=2; - {0x08043B, 3}, //TXVGA=3; - {0x08044B, 4}, //TXVGA=4; - {0x08045B, 5}, //TXVGA=5; - {0x08046B, 6}, //TXVGA=6; - {0x08047B, 7}, //TXVGA=7; - {0x08048B, 8}, //TXVGA=8; - {0x08049B, 9}, //TXVGA=9; - {0x0804AB, 10}, //TXVGA=10; - {0x0804BB, 11}, //TXVGA=11; - {0x0804CB, 12}, //TXVGA=12; - {0x0804DB, 13}, //TXVGA=13; - {0x0804EB, 14}, //TXVGA=14; - {0x0804FB, 15}, //TXVGA=15; - {0x08050B, 16}, //TXVGA=16; - {0x08051B, 17}, //TXVGA=17; - {0x08052B, 18}, //TXVGA=18; - {0x08053B, 19}, //TXVGA=19; - {0x08054B, 20}, //TXVGA=20; - {0x08055B, 21}, //TXVGA=21; - {0x08056B, 22}, //TXVGA=22; - {0x08057B, 23}, //TXVGA=23; - {0x08058B, 24}, //TXVGA=24; - {0x08059B, 25}, //TXVGA=25; - {0x0805AB, 26}, //TXVGA=26; - {0x0805BB, 27}, //TXVGA=27; - {0x0805CB, 28}, //TXVGA=28; - {0x0805DB, 29}, //TXVGA=29; - {0x0805EB, 30}, //TXVGA=30; - {0x0805FB, 31}, //TXVGA=31; - {0x08060B, 32}, //TXVGA=32; - {0x08061B, 33}, //TXVGA=33; - {0x08062B, 34}, //TXVGA=34; - {0x08063B, 35}, //TXVGA=35; - {0x08064B, 36}, //TXVGA=36; - {0x08065B, 37}, //TXVGA=37; - {0x08066B, 38}, //TXVGA=38; - {0x08067B, 39}, //TXVGA=39; - {0x08068B, 40}, //TXVGA=40; - {0x08069B, 41}, //TXVGA=41; - {0x0806AB, 42}, //TXVGA=42; - {0x0806BB, 43}, //TXVGA=43; - {0x0806CB, 44}, //TXVGA=44; - {0x0806DB, 45}, //TXVGA=45; - {0x0806EB, 46}, //TXVGA=46; - {0x0806FB, 47}, //TXVGA=47; - {0x08070B, 48}, //TXVGA=48; - {0x08071B, 49}, //TXVGA=49; - {0x08072B, 50}, //TXVGA=50; - {0x08073B, 51}, //TXVGA=51; - {0x08074B, 52}, //TXVGA=52; - {0x08075B, 53}, //TXVGA=53; - {0x08076B, 54}, //TXVGA=54; - {0x08077B, 55}, //TXVGA=55; - {0x08078B, 56}, //TXVGA=56; - {0x08079B, 57}, //TXVGA=57; - {0x0807AB, 58}, //TXVGA=58; - {0x0807BB, 59}, //TXVGA=59; - {0x0807CB, 60}, //TXVGA=60; - {0x0807DB, 61}, //TXVGA=61; - {0x0807EB, 62}, //TXVGA=62; - {0x0807FB, 63}, //TXVGA=63; +/* + * RF Calibration <=== Register 0x0F + * 0x0F 0x1ABA8F; start from 2.4Ghz default state + * 0x0F 0x9ABA8F; TXDC compensation + * 0x0F 0x3ABA8F; RXFIL adjustment + * 0x0F 0x1ABA8F; restore 2.4Ghz default state + */ + +/* TXVGA Mapping Table <=== Register 0x0B */ +u32 al7230_txvga_data[][2] = { + {0x08040B, 0}, /* TXVGA = 0; */ + {0x08041B, 1}, /* TXVGA = 1; */ + {0x08042B, 2}, /* TXVGA = 2; */ + {0x08043B, 3}, /* TXVGA = 3; */ + {0x08044B, 4}, /* TXVGA = 4; */ + {0x08045B, 5}, /* TXVGA = 5; */ + {0x08046B, 6}, /* TXVGA = 6; */ + {0x08047B, 7}, /* TXVGA = 7; */ + {0x08048B, 8}, /* TXVGA = 8; */ + {0x08049B, 9}, /* TXVGA = 9; */ + {0x0804AB, 10}, /* TXVGA = 10; */ + {0x0804BB, 11}, /* TXVGA = 11; */ + {0x0804CB, 12}, /* TXVGA = 12; */ + {0x0804DB, 13}, /* TXVGA = 13; */ + {0x0804EB, 14}, /* TXVGA = 14; */ + {0x0804FB, 15}, /* TXVGA = 15; */ + {0x08050B, 16}, /* TXVGA = 16; */ + {0x08051B, 17}, /* TXVGA = 17; */ + {0x08052B, 18}, /* TXVGA = 18; */ + {0x08053B, 19}, /* TXVGA = 19; */ + {0x08054B, 20}, /* TXVGA = 20; */ + {0x08055B, 21}, /* TXVGA = 21; */ + {0x08056B, 22}, /* TXVGA = 22; */ + {0x08057B, 23}, /* TXVGA = 23; */ + {0x08058B, 24}, /* TXVGA = 24; */ + {0x08059B, 25}, /* TXVGA = 25; */ + {0x0805AB, 26}, /* TXVGA = 26; */ + {0x0805BB, 27}, /* TXVGA = 27; */ + {0x0805CB, 28}, /* TXVGA = 28; */ + {0x0805DB, 29}, /* TXVGA = 29; */ + {0x0805EB, 30}, /* TXVGA = 30; */ + {0x0805FB, 31}, /* TXVGA = 31; */ + {0x08060B, 32}, /* TXVGA = 32; */ + {0x08061B, 33}, /* TXVGA = 33; */ + {0x08062B, 34}, /* TXVGA = 34; */ + {0x08063B, 35}, /* TXVGA = 35; */ + {0x08064B, 36}, /* TXVGA = 36; */ + {0x08065B, 37}, /* TXVGA = 37; */ + {0x08066B, 38}, /* TXVGA = 38; */ + {0x08067B, 39}, /* TXVGA = 39; */ + {0x08068B, 40}, /* TXVGA = 40; */ + {0x08069B, 41}, /* TXVGA = 41; */ + {0x0806AB, 42}, /* TXVGA = 42; */ + {0x0806BB, 43}, /* TXVGA = 43; */ + {0x0806CB, 44}, /* TXVGA = 44; */ + {0x0806DB, 45}, /* TXVGA = 45; */ + {0x0806EB, 46}, /* TXVGA = 46; */ + {0x0806FB, 47}, /* TXVGA = 47; */ + {0x08070B, 48}, /* TXVGA = 48; */ + {0x08071B, 49}, /* TXVGA = 49; */ + {0x08072B, 50}, /* TXVGA = 50; */ + {0x08073B, 51}, /* TXVGA = 51; */ + {0x08074B, 52}, /* TXVGA = 52; */ + {0x08075B, 53}, /* TXVGA = 53; */ + {0x08076B, 54}, /* TXVGA = 54; */ + {0x08077B, 55}, /* TXVGA = 55; */ + {0x08078B, 56}, /* TXVGA = 56; */ + {0x08079B, 57}, /* TXVGA = 57; */ + {0x0807AB, 58}, /* TXVGA = 58; */ + {0x0807BB, 59}, /* TXVGA = 59; */ + {0x0807CB, 60}, /* TXVGA = 60; */ + {0x0807DB, 61}, /* TXVGA = 61; */ + {0x0807EB, 62}, /* TXVGA = 62; */ + {0x0807FB, 63}, /* TXVGA = 63; */ }; -//-------------------------------- - +/* ============================================= */ -//; W89RF242 RFIC SPI programming initial data -//; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b -//; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho -//; -//; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A -u32 w89rf242_rf_data[] = -{ - (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off - (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on - (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA - (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz - (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388 - //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C - (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A - //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D - (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C - //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input - (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE - //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 - (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO - (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012, - //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) - (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A) - (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6 - //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29) - (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558 - //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner - (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A, - //; 15555 ; IBSB (0x0D) - (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC, - //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25) - (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818 - //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB - (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022 - //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) - (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add - //; TMODC (0x12) -- Turn OFF Tempearure sensor +/* + * W89RF242 RFIC SPI programming initial data + * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b + */ +u32 w89rf242_rf_data[] = { + (0x00 << 24) | 0xF86100, /* 3E184; MODA (0x00) -- Normal mode ; calibration off */ + (0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on */ + (0x02 << 24) | 0x102504, /* 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA */ + (0x03 << 24) | 0x026286, /* 0098A; FCHN (0x03) -- default CH7, 2442MHz */ + (0x04 << 24) | 0x000208, /* 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C */ + (0x05 << 24) | 0x24C60A, /* 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D */ + (0x06 << 24) | 0x3432CC, /* 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input */ + (0x07 << 24) | 0x0C68CE, /* 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 */ + (0x08 << 24) | 0x100010, /* 04000; TCAL (0x08) -- for LO */ + (0x09 << 24) | 0x004012, /* 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) */ + (0x0A << 24) | 0x704014, /* 1C100; RCALB (0x0A) */ + (0x0B << 24) | 0x18BDD6, /* 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B */ + (0x0C << 24) | 0x575558, /* 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner */ + (0x0D << 24) | 0x55545A, /* 15555 ; IBSB (0x0D) */ + (0x0E << 24) | 0x5557DC, /* 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F */ + (0x10 << 24) | 0x000C20, /* 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB */ + (0x11 << 24) | 0x0C0022, /* 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) */ + (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Tempearure sensor */ }; -u32 w89rf242_channel_data_24[][2] = -{ - {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01 - {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02 - {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03 - {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04 - {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05 - {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06 - {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07 - {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08 - {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09 - {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10 - {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11 - {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12 - {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13 - {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14 +u32 w89rf242_channel_data_24[][2] = { + {(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */ + {(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */ + {(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */ + {(0x03 << 24) | 0x025EC6, (0x04 << 24) | 0x080408}, /* channe1 04 */ + {(0x03 << 24) | 0x026006, (0x04 << 24) | 0x080408}, /* channe1 05 */ + {(0x03 << 24) | 0x026146, (0x04 << 24) | 0x080408}, /* channe1 06 */ + {(0x03 << 24) | 0x026286, (0x04 << 24) | 0x080408}, /* channe1 07 */ + {(0x03 << 24) | 0x0263C6, (0x04 << 24) | 0x080408}, /* channe1 08 */ + {(0x03 << 24) | 0x026506, (0x04 << 24) | 0x080408}, /* channe1 09 */ + {(0x03 << 24) | 0x026646, (0x04 << 24) | 0x080408}, /* channe1 10 */ + {(0x03 << 24) | 0x026786, (0x04 << 24) | 0x080408}, /* channe1 11 */ + {(0x03 << 24) | 0x0268C6, (0x04 << 24) | 0x080408}, /* channe1 12 */ + {(0x03 << 24) | 0x026A06, (0x04 << 24) | 0x080408}, /* channe1 13 */ + {(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408} /* channe1 14 */ }; -u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A}; +u32 w89rf242_power_data_24[] = {(0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A}; -// 20060315.6 Enlarge for new scale -// 20060316.6 20060619.2.a add mapping array -u32 w89rf242_txvga_old_mapping[][2] = -{ - {0, 0} , // New <-> Old +u32 w89rf242_txvga_old_mapping[][2] = { + {0, 0} , /* New <-> Old */ {1, 1} , {2, 2} , {3, 3} , {4, 4} , {6, 5} , - {8, 6 }, - {10, 7 }, - {12, 8 }, - {14, 9 }, + {8, 6}, + {10, 7}, + {12, 8}, + {14, 9}, {16, 10}, {18, 11}, {20, 12}, @@ -818,1704 +735,1514 @@ u32 w89rf242_txvga_old_mapping[][2] = {30, 17}, {32, 18}, {34, 19}, +}; +u32 w89rf242_txvga_data[][5] = { + /* low gain mode */ + {(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */ + {(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131}, + {(0x05 << 24) | 0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131}, /* (default) +14dBm (ANT) */ + {(0x05 << 24) | 0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131}, -}; + /* TXVGA=0x10 */ + {(0x05 << 24) | 0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838}, + {(0x05 << 24) | 0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B}, -// 20060619.3 modify from Bruce's mail -u32 w89rf242_txvga_data[][5] = -{ - //low gain mode - { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain - { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 }, - { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT) - { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 }, - - //TXVGA=0x10 - { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 }, - { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B }, - - //TXVGA=0x11 - { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 }, - { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 }, - - //TXVGA=0x12 - { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 }, - { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 }, - - //TXVGA=0x13 - { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 }, - { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 }, - - //TXVGA=0x14 - { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 }, - { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 }, - - //TXVGA=0x15 - { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 }, - { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 }, - - //TXVGA=0x16 - { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 }, - { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 }, - - //TXVGA=0x17 - { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F }, - { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 }, - - //TXVGA=0x18 - { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E }, - { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 }, - - //TXVGA=0x19 - { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D }, - { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 }, - - //TXVGA=0x1A - { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E }, - { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 }, - - //TXVGA=0x1B - { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 }, - { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 }, - - //TXVGA=0x1C - { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 }, - { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 }, - - //TXVGA=0x1D - { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 }, - { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B }, - - //TXVGA=0x1E - { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B }, - { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 }, - - //TXVGA=0x1F - { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 } + /* TXVGA=0x11 */ + { (0x05 << 24) | 0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333}, + { (0x05 << 24) | 0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737}, + + /* TXVGA=0x12 */ + {(0x05 << 24) | 0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030}, + {(0x05 << 24) | 0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434}, + + /* TXVGA=0x13 */ + {(0x05 << 24) | 0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030}, + {(0x05 << 24) | 0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232}, + + /* TXVGA=0x14 */ + {(0x05 << 24) | 0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131}, + {(0x05 << 24) | 0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434}, + + /* TXVGA=0x15 */ + {(0x05 << 24) | 0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131}, + {(0x05 << 24) | 0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434}, + + /* TXVGA=0x16 */ + {(0x05 << 24) | 0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131}, + {(0x05 << 24) | 0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535}, + + /* TXVGA=0x17 */ + {(0x05 << 24) | 0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F}, + {(0x05 << 24) | 0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131}, + + /* TXVGA=0x18 */ + {(0x05 << 24) | 0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E}, + {(0x05 << 24) | 0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030}, + + /* TXVGA=0x19 */ + {(0x05 << 24) | 0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D}, + {(0x05 << 24) | 0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030}, + + /* TXVGA=0x1A */ + {(0x05 << 24) | 0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E}, + {(0x05 << 24) | 0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131}, + + /* TXVGA=0x1B */ + {(0x05 << 24) | 0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030}, + {(0x05 << 24) | 0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434}, + + /* TXVGA=0x1C */ + {(0x05 << 24) | 0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131}, + {(0x05 << 24) | 0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636}, + + /* TXVGA=0x1D */ + {(0x05 << 24) | 0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737}, + {(0x05 << 24) | 0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B}, + + /* TXVGA=0x1E */ + {(0x05 << 24) | 0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B}, + {(0x05 << 24) | 0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141}, + + /* TXVGA=0x1F */ + {(0x05 << 24) | 0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242} }; -/////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////// - - - -//============================================================================================================= -// Uxx_ReadEthernetAddress -- -// -// Routine Description: -// Reads in the Ethernet address from the IC. -// -// Arguments: -// pHwData - The pHwData structure -// -// Return Value: -// -// The address is stored in EthernetIDAddr. -//============================================================================================================= -void -Uxx_ReadEthernetAddress( struct hw_data * pHwData ) +/* ================================================================================================== */ + + + +/* + * ============================================================================================================= + * Uxx_ReadEthernetAddress -- + * + * Routine Description: + * Reads in the Ethernet address from the IC. + * + * Arguments: + * pHwData - The pHwData structure + * + * Return Value: + * + * The address is stored in EthernetIDAddr. + * ============================================================================================================= + */ +void Uxx_ReadEthernetAddress(struct hw_data *pHwData) { u32 ltmp; - // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change. - // Only unplug and plug again can make hardware read EEPROM again. 20060727 - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d) - Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); - *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d) - Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); - *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d) - Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); - *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian + /* + * Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change. + * Only unplug and plug again can make hardware read EEPROM again. + */ + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08000000); /* Start EEPROM access + Read + address(0x0d) */ + Wb35Reg_ReadSync(pHwData, 0x03b4, <mp); + *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16) ltmp); + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08010000); /* Start EEPROM access + Read + address(0x0d) */ + Wb35Reg_ReadSync(pHwData, 0x03b4, <mp); + *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16) ltmp); + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08020000); /* Start EEPROM access + Read + address(0x0d) */ + Wb35Reg_ReadSync(pHwData, 0x03b4, <mp); + *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16) ltmp); *(u16 *)(pHwData->PermanentMacAddress + 6) = 0; - Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress) ); //20060926 anson's endian - Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian + Wb35Reg_WriteSync(pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress)); + Wb35Reg_WriteSync(pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress + 4))); } -//=============================================================================================================== -// CardGetMulticastBit -- -// Description: -// For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to. -// Calls CardComputeCrc() to determine the CRC value. -// Arguments: -// Address - the address -// Byte - the byte that it hashes to -// Value - will have a 1 in the relevant bit -// Return Value: -// None. -//============================================================================================================== -void CardGetMulticastBit( u8 Address[ETH_ALEN], u8 *Byte, u8 *Value ) +/* + * =============================================================================================================== + * CardGetMulticastBit -- + * Description: + * For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to. + * Calls CardComputeCrc() to determine the CRC value. + * Arguments: + * Address - the address + * Byte - the byte that it hashes to + * Value - will have a 1 in the relevant bit + * Return Value: + * None. + * ============================================================================================================== + */ +void CardGetMulticastBit(u8 Address[ETH_ALEN], u8 *Byte, u8 *Value) { - u32 Crc; - u32 BitNumber; + u32 Crc; + u32 BitNumber; - // First compute the CRC. - Crc = CardComputeCrc(Address, ETH_ALEN); + /* First compute the CRC. */ + Crc = CardComputeCrc(Address, ETH_ALEN); - // The computed CRC is bit0~31 from left to right - //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 + /* The computed CRC is bit0~31 from left to right */ + /* At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 */ BitNumber = (u32) ((Crc >> 26) & 0x3f); - *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8) - *Value = (u8) ((u8)1 << (BitNumber % 8)); + *Byte = (u8) (BitNumber >> 3); /* 900514 original (BitNumber / 8) */ + *Value = (u8) ((u8) 1 << (BitNumber % 8)); } -void Uxx_power_on_procedure( struct hw_data * pHwData ) +void Uxx_power_on_procedure(struct hw_data *pHwData) { u32 ltmp, loop; - if( pHwData->phy_type <= RF_MAXIM_V1 ) - Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 ); - else - { - Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF - - // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail - Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only - msleep(10); // Modify 20051221.1.b - Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and - msleep(10); // Modify 20051221.1.b - + if (pHwData->phy_type <= RF_MAXIM_V1) + Wb35Reg_WriteSync(pHwData, 0x03d4, 0xffffff38); + else { + Wb35Reg_WriteSync(pHwData, 0x03f4, 0xFF5807FF); + Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */ + msleep(10); + Wb35Reg_WriteSync(pHwData, 0x03d4, 0xb8); /* REG_ON RF_RSTN on, and */ + msleep(10); ltmp = 0x4968; - if( (pHwData->phy_type == RF_WB_242) || - (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add + if ((pHwData->phy_type == RF_WB_242) || + (RF_WB_242_1 == pHwData->phy_type)) ltmp = 0x4468; - Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp ); - Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0 + Wb35Reg_WriteSync(pHwData, 0x03d0, ltmp); + Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */ - msleep(20); // Modify 20051221.1.b - Wb35Reg_ReadSync( pHwData, 0x03d0, <mp ); - loop = 500; // Wait for 5 second 20061101 - while( !(ltmp & 0x20) && loop-- ) - { - msleep(10); // Modify 20051221.1.b - if( !Wb35Reg_ReadSync( pHwData, 0x03d0, <mp ) ) + msleep(20); + Wb35Reg_ReadSync(pHwData, 0x03d0, <mp); + loop = 500; /* Wait for 5 second */ + while (!(ltmp & 0x20) && loop--) { + msleep(10); + if (!Wb35Reg_ReadSync(pHwData, 0x03d0, <mp)) break; } - Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN + Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */ } - Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first - msleep(10); // Add this 20051221.1.b + Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */ + msleep(10); - // Set burst write delay - Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff ); + /* Set burst write delay */ + Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff); } -void Set_ChanIndep_RfData_al7230_24( struct hw_data * pHwData, u32 *pltmp ,char number) +void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp , char number) { u8 i; - for( i=0; i<number; i++ ) - { + for (i = 0; i < number; i++) { pHwData->phy_para[i] = al7230_rf_data_24[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff); + pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i] & 0xffffff); } } -void Set_ChanIndep_RfData_al7230_50( struct hw_data * pHwData, u32 *pltmp, char number) +void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, char number) { u8 i; - for( i=0; i<number; i++ ) - { + for (i = 0; i < number; i++) { pHwData->phy_para[i] = al7230_rf_data_50[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff); + pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i] & 0xffffff); } } -//============================================================================================================= -// RFSynthesizer_initial -- -//============================================================================================================= -void -RFSynthesizer_initial(struct hw_data * pHwData) +/* + * ============================================================================================================= + * RFSynthesizer_initial -- + * ============================================================================================================= + */ +void RFSynthesizer_initial(struct hw_data *pHwData) { u32 altmp[32]; - u32 * pltmp = altmp; + u32 *pltmp = altmp; u32 ltmp; - u8 number=0x00; // The number of register vale + u8 number = 0x00; /* The number of register vale */ u8 i; - // - // bit[31] SPI Enable. - // 1=perform synthesizer program operation. This bit will - // cleared automatically after the operation is completed. - // bit[30] SPI R/W Control - // 0=write, 1=read - // bit[29:24] SPI Data Format Length - // bit[17:4 ] RF Data bits. - // bit[3 :0 ] RF address. - switch( pHwData->phy_type ) - { + /* + * bit[31] SPI Enable. + * 1=perform synthesizer program operation. This bit will + * cleared automatically after the operation is completed. + * bit[30] SPI R/W Control + * 0=write, 1=read + * bit[29:24] SPI Data Format Length + * bit[17:4 ] RF Data bits. + * bit[3 :0 ] RF address. + */ + switch (pHwData->phy_type) { case RF_MAXIM_2825: - case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) - number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]); - for( i=0; i<number; i++ ) - { - pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18); + case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ + number = sizeof(max2825_rf_data) / sizeof(max2825_rf_data[0]); + for (i = 0; i < number; i++) { + pHwData->phy_para[i] = max2825_rf_data[i]; /* Backup Rf parameter */ + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_rf_data[i], 18); } break; - case RF_MAXIM_2827: - number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]); - for( i=0; i<number; i++ ) - { + number = sizeof(max2827_rf_data) / sizeof(max2827_rf_data[0]); + for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2827_rf_data[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18); + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_rf_data[i], 18); } break; - case RF_MAXIM_2828: - number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]); - for( i=0; i<number; i++ ) - { + number = sizeof(max2828_rf_data) / sizeof(max2828_rf_data[0]); + for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2828_rf_data[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18); + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_rf_data[i], 18); } break; - case RF_MAXIM_2829: - number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]); - for( i=0; i<number; i++ ) - { + number = sizeof(max2829_rf_data) / sizeof(max2829_rf_data[0]); + for (i = 0; i < number; i++) { pHwData->phy_para[i] = max2829_rf_data[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18); + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_rf_data[i], 18); } break; - case RF_AIROHA_2230: - number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]); - for( i=0; i<number; i++ ) - { + number = sizeof(al2230_rf_data) / sizeof(al2230_rf_data[0]); + for (i = 0; i < number; i++) { pHwData->phy_para[i] = al2230_rf_data[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20); + pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[i], 20); } break; - case RF_AIROHA_2230S: - number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]); - for( i=0; i<number; i++ ) - { + number = sizeof(al2230s_rf_data) / sizeof(al2230s_rf_data[0]); + for (i = 0; i < number; i++) { pHwData->phy_para[i] = al2230s_rf_data[i]; - pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20); + pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230s_rf_data[i], 20); } break; - case RF_AIROHA_7230: - - //Start to fill RF parameters, PLL_ON should be pulled low. - Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 ); -#ifdef _PE_STATE_DUMP_ + /* Start to fill RF parameters, PLL_ON should be pulled low. */ + Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000); + #ifdef _PE_STATE_DUMP_ printk("* PLL_ON low\n"); -#endif - - number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]); + #endif + number = sizeof(al7230_rf_data_24) / sizeof(al7230_rf_data_24[0]); Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); break; - case RF_WB_242: - case RF_WB_242_1: // 20060619.5 Add - number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]); - for( i=0; i<number; i++ ) - { + case RF_WB_242_1: + number = sizeof(w89rf242_rf_data) / sizeof(w89rf242_rf_data[0]); + for (i = 0; i < number; i++) { ltmp = w89rf242_rf_data[i]; - if( i == 4 ) // Update the VCO trim from EEPROM - { - ltmp &= ~0xff0; // Mask bit4 ~bit11 - ltmp |= pHwData->VCO_trim<<4; + if (i == 4) { /* Update the VCO trim from EEPROM */ + ltmp &= ~0xff0; /* Mask bit4 ~bit11 */ + ltmp |= pHwData->VCO_trim << 4; } pHwData->phy_para[i] = ltmp; - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24); + pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(ltmp, 24); } break; } pHwData->phy_number = number; - // The 16 is the maximum capability of hardware. Here use 12 - if( number > 12 ) { - //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT ); - for( i=0; i<12; i++ ) // For Al2230 - Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] ); + /* The 16 is the maximum capability of hardware. Here use 12 */ + if (number > 12) { + for (i = 0; i < 12; i++) /* For Al2230 */ + Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]); pltmp += 12; number -= 12; } - // Write to register. number must less and equal than 16 - for( i=0; i<number; i++ ) - Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] ); + /* Write to register. number must less and equal than 16 */ + for (i = 0; i < number; i++) + Wb35Reg_WriteSync(pHwData, 0x864, pltmp[i]); - // 20060630.1 Calibration only 1 time - if( pHwData->CalOneTime ) + /* Calibration only 1 time */ + if (pHwData->CalOneTime) return; pHwData->CalOneTime = 1; - switch( pHwData->phy_type ) - { - case RF_AIROHA_2230: - - // 20060511.1 --- Modifying the follow step for Rx issue----------------- - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(10); - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(10); - - case RF_AIROHA_2230S: // 20060420 Add this - - // 20060511.1 --- Modifying the follow step for Rx issue----------------- - Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only - msleep(10); // Modify 20051221.1.b - - Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0 - msleep(10); // Modify 20051221.1.b - - Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN - Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first - msleep(10); // Add this 20051221.1.b - //------------------------------------------------------------------------ - - // The follow code doesn't use the burst-write mode - //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - ltmp = pHwData->reg.BB5C & 0xfffff000; - Wb35Reg_WriteSync( pHwData, 0x105c, ltmp ); - pHwData->reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify - Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); - msleep(5); - - //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal. - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - - //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - - //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting - ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - -// //Force TXI(Q)P(N) to normal control - Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->reg.BB5C ); - pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); - Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->reg.BB50); - break; - - case RF_AIROHA_7230: - - //RF parameters have filled completely, PLL_ON should be - //pulled high - Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON high\n"); - #endif - - //2.4GHz - //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; - //Wb35Reg_WriteSync pHwData, 0x0864, ltmp ); - //msleep(1); // Sleep 1 ms - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - - //5GHz - Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 ); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON low\n"); - #endif - - number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]); - Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); - // Write to register. number must less and equal than 16 - for( i=0; i<number; i++ ) - Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] ); - msleep(5); - - Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); - #ifdef _PE_STATE_DUMP_ - printk("* PLL_ON high\n"); - #endif - - //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; - //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); - - //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); - //printk("* PLL_ON high\n"); - break; - - case RF_WB_242: - case RF_WB_242_1: // 20060619.5 Add - - // - // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo - // - ltmp = pHwData->reg.BB5C & 0xfffff000; - Wb35Reg_WriteSync( pHwData, 0x105c, ltmp ); - Wb35Reg_WriteSync( pHwData, 0x1058, 0 ); - pHwData->reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630 - Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); - - //----- Calibration (1). VCO frequency calibration - //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10) - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); // Sleep 5ms - //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(2); // Sleep 2ms - - //----- Calibration (2). TX baseband Gm-C filter auto-tuning - //Calibration (2a). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005) - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (2c). turn-on TX Gm-C filter auto-tuning - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - udelay(150); // Sleep 150 us - //turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //----- Calibration (3). RX baseband Gm-C filter auto-tuning - //Calibration (3a). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005) - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005) - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (3c). turn-on RX Gm-C filter auto-tuning - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - udelay(150); // Sleep 150 us - //Calibration (3e). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //----- Calibration (4). TX LO leakage calibration - //Calibration (4a). TX LO leakage calibration - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - udelay(150); // Sleep 150 us - - //----- Calibration (5). RX DC offset calibration - //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (5b). turn off AGC servo-loop & RSSI - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //; for LNA=11 -------- - //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(2); // Sleep 2ms - //Calibration (5f). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //; for LNA=10 -------- - //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(2); // Sleep 2ms - //Calibration (5f). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //; for LNA=01 -------- - //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(2); // Sleep 2ms - //Calibration (5f). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //; for LNA=00 -------- - //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(2); // Sleep 2ms - //Calibration (5f). turn off ENCAL signal - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - //Calibration (5g). turn on AGC servo-loop - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - - //; ----- Calibration (7). Switch RF chip to normal mode - //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode -// msleep(10); // @@ 20060721 - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24); - Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); - msleep(5); // Sleep 5 ms - -// //write back -// Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C); -// pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix -// Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); -// msleep(1); // Sleep 1 ms - break; + switch (pHwData->phy_type) { + case RF_AIROHA_2230: + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x07 << 20) | 0xE168E, 20); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(10); + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[7], 20); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(10); + case RF_AIROHA_2230S: + Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */ + msleep(10); + Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */ + msleep(10); + Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */ + Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */ + msleep(10); + /* ========================================================= */ + + /* The follow code doesn't use the burst-write mode */ + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F<<20) | 0xF01A0, 20); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + ltmp = pHwData->reg.BB5C & 0xfffff000; + Wb35Reg_WriteSync(pHwData, 0x105c, ltmp); + pHwData->reg.BB50 |= 0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START) */ + Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); + msleep(5); + + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01B0, 20); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01E0, 20); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + + ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp) ; + + Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C); + pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */ + Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); + break; + case RF_AIROHA_7230: + /* RF parameters have filled completely, PLL_ON should be pulled high */ + Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080); + #ifdef _PE_STATE_DUMP_ + printk("* PLL_ON high\n"); + #endif + + /* 2.4GHz */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + + /* 5GHz */ + Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000); + #ifdef _PE_STATE_DUMP_ + printk("* PLL_ON low\n"); + #endif + + number = sizeof(al7230_rf_data_50) / sizeof(al7230_rf_data_50[0]); + Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); + /* Write to register. number must less and equal than 16 */ + for (i = 0; i < number; i++) + Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]); + msleep(5); + + Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080); + #ifdef _PE_STATE_DUMP_ + printk("* PLL_ON high\n"); + #endif + + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + break; + case RF_WB_242: + case RF_WB_242_1: + /* for FA5976A */ + ltmp = pHwData->reg.BB5C & 0xfffff000; + Wb35Reg_WriteSync(pHwData, 0x105c, ltmp); + Wb35Reg_WriteSync(pHwData, 0x1058, 0); + pHwData->reg.BB50 |= 0x3; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */ + Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); + + /* ----- Calibration (1). VCO frequency calibration */ + /* Calibration (1a.0). Synthesizer reset */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00101E, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + /* Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFE69c0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(2); + + /* ----- Calibration (2). TX baseband Gm-C filter auto-tuning */ + /* Calibration (2a). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (2b). send TX reset signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00201E, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (2c). turn-on TX Gm-C filter auto-tuning */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFCEBC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + udelay(150); /* Sleep 150 us */ + /* turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* ----- Calibration (3). RX baseband Gm-C filter auto-tuning */ + /* Calibration (3a). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default;) */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (3b). send RX reset signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00401E, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (3c). turn-on RX Gm-C filter auto-tuning */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFEEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + udelay(150); /* Sleep 150 us */ + /* Calibration (3e). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* ----- Calibration (4). TX LO leakage calibration */ + /* Calibration (4a). TX LO leakage calibration */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFD6BC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + udelay(150); /* Sleep 150 us */ + + /* ----- Calibration (5). RX DC offset calibration */ + /* Calibration (5a). turn off ENCAL signal and set to RX SW DC calibration mode */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (5b). turn off AGC servo-loop & RSSI */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEBFFC2, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* for LNA=11 -------- */ + /* Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x343FCC, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(2); + /* Calibration (5f). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* for LNA=10 -------- */ + /* Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x342FCC, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(2); + /* Calibration (5f). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* for LNA=01 -------- */ + /* Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x341FCC, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(2); + /* Calibration (5f). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* for LNA=00 -------- */ + /* Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x340FCC, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(2); + /* Calibration (5f). turn off ENCAL signal */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + /* Calibration (5g). turn on AGC servo-loop */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEFFFC2, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + + /* ----- Calibration (7). Switch RF chip to normal mode */ + /* 0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF86100, 24); + Wb35Reg_WriteSync(pHwData, 0x0864, ltmp); + msleep(5); + break; } } -void BBProcessor_AL7230_2400( struct hw_data * pHwData) +void BBProcessor_AL7230_2400(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; u32 pltmp[12]; - pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4 + pltmp[0] = 0x16A8337A; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9AFF9AA6; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xFFF72031; /* 0x100c AGC_Ctrl4 */ reg->BB0C = 0xFFF72031; - pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7 - pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0x40000528; // 20050927 0x40000228 - pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl + pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0xF2211111; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x06443440; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0xA8002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0x40000528; + pltmp[11] = 0x232D7F30; /* 0x102c A_ACQ_Ctrl */ reg->BB2C = 0x232D7F30; - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); - pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl + pltmp[0] = 0x00002c54; /* 0x1030 B_ACQ_Ctrl */ reg->BB30 = 0x00002c54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter - pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter - pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */ + pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */ + pltmp[8] = 0x2B106208; /* 0x1050 MODE_Ctrl */ reg->BB50 = 0x2B106208; - pltmp[9] = 0; // 0x1054 + pltmp[9] = 0; /* 0x1054 */ reg->BB54 = 0x00000000; - pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha + pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */ reg->BB58 = 0x52524242; - pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - + pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); } -void BBProcessor_AL7230_5000( struct hw_data * pHwData) +void BBProcessor_AL7230_5000(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; u32 pltmp[12]; - pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4 + pltmp[0] = 0x16AA6678; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9AFFA0B2; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xEFFF233E; /* 0x100c AGC_Ctrl4 */ reg->BB0C = 0xEFFF233E; - pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7 - pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0x40000528; // 20050927 0x40000228 - pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl + pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0xF2432111; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x05C43440; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0x40000528; + pltmp[11] = 0x232FDF30;/* 0x102c A_ACQ_Ctrl */ reg->BB2C = 0x232FDF30; - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); - pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter + pltmp[0] = 0x80002C7C; /* 0x1030 B_ACQ_Ctrl */ + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter - pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter - pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */ + pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */ + pltmp[8] = 0x2B107208; /* 0x1050 MODE_Ctrl */ reg->BB50 = 0x2B107208; - pltmp[9] = 0; // 0x1054 + pltmp[9] = 0; /* 0x1054 */ reg->BB54 = 0x00000000; - pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha + pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */ reg->BB58 = 0x52524242; - pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - + pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); } -//============================================================================================================= -// BBProcessorPowerupInit -- -// -// Description: -// Initialize the Baseband processor. -// -// Arguments: -// pHwData - Handle of the USB Device. -// -// Return values: -// None. -//============================================================================================================= -void -BBProcessor_initial( struct hw_data * pHwData ) +/* + * =========================================================================== + * BBProcessorPowerupInit -- + * + * Description: + * Initialize the Baseband processor. + * + * Arguments: + * pHwData - Handle of the USB Device. + * + * Return values: + * None. + *============================================================================ + */ +void BBProcessor_initial(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; u32 i, pltmp[12]; - switch( pHwData->phy_type ) - { - case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) - - pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4 - reg->BB0C = 0xEFFF1A34; - pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5 - pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) - pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl - reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1 - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter - reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter - pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter - pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106208; - pltmp[9] = 0; // 0x1054 - reg->BB54 = 0x00000000; - pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha - reg->BB58 = 0x64646464; - pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; - - //------------------------------------------------------------------ - //[20040722 WK] - //Only for baseband version 2 -// case RF_MAXIM_317: - case RF_MAXIM_2825: - case RF_MAXIM_2827: - case RF_MAXIM_2828: - - pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4 - reg->BB0C = 0xefff1a34; - pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5 - pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95 - pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl - reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1 - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter - reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter - pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter - pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106208; - pltmp[9] = 0; // 0x1054 - reg->BB54 = 0x00000000; - pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha - reg->BB58 = 0x64646464; - pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; - - case RF_MAXIM_2829: - - pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95 - reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95 - pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5 - pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95 - pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl - reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1 - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95 - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter - reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95 - pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95 - pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106208; - pltmp[9] = 0; // 0x1054 - reg->BB54 = 0x00000000; - pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95 - reg->BB58 = 0x64646464; - pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; - - case RF_AIROHA_2230: - - pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77 - pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version - reg->BB0C = 0xFFFd203c; - pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version - pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version - pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0X40000528; //0x40000228 - pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730 - reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1 - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769 - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter - reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2 - reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2 - pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2 - reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2 - pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106200; - pltmp[9] = 0; // 0x1054 - reg->BB54 = 0x00000000; - pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha - reg->BB58 = 0x52524242; - pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; + switch (pHwData->phy_type) { + case RF_MAXIM_V1: /* Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ + pltmp[0] = 0x16F47E77; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9AFFAEA4; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xEFFF1A34; /* 0x100c AGC_Ctrl4 */ + reg->BB0C = 0xEFFF1A34; + pltmp[4] = 0x0FABE0B7; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00CAA332; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0xF6632111; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = (pHwData->phy_type == 3) ? 0x40000a28 : 0x40000228; /* 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) */ + pltmp[11] = 0x232FDF30; /* 0x102c A_ACQ_Ctrl */ + reg->BB2C = 0x232FDF30; /* Modify for 33's 1.0.95.xxx version, antenna 1 */ + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); + + pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ + reg->BB30 = 0x00002C54; + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ + reg->BB3C = 0x00000000; + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */ + pltmp[7] = 0x0E00FEFF; /* 0x104c 11b TX RC filter */ + pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ + reg->BB50 = 0x27106208; + pltmp[9] = 0; /* 0x1054 */ + reg->BB54 = 0x00000000; + pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */ + reg->BB58 = 0x64646464; + pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); + + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; - case RF_AIROHA_2230S: // 20060420 Add this - - pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77 - pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version - reg->BB0C = 0xFFFd203c; - pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version - pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version - pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0X40000528; //0x40000228 - pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730 - reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1 - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769 - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter - reg->BB3C = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2 - reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2 - pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2 - reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 - pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106200; - pltmp[9] = 0; // 0x1054 - reg->BB54 = 0x00000000; - pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha - reg->BB58 = 0x52523232; // 20060419 0x52524242; - pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; + case RF_MAXIM_2825: + case RF_MAXIM_2827: + case RF_MAXIM_2828: + pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xefff1a34; /* 0x100c AGC_Ctrl4 */ + reg->BB0C = 0xefff1a34; + pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0xf6632111; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0x40000528; + pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */ + reg->BB2C = 0x232fdf30; /* antenna 1 */ + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); + + pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ + reg->BB30 = 0x00002C54; + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ + reg->BB3C = 0x00000000; + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */ + pltmp[7] = 0x0D00FDFF; /* 0x104c 11b TX RC filter */ + pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ + reg->BB50 = 0x27106208; + pltmp[9] = 0; /* 0x1054 */ + reg->BB54 = 0x00000000; + pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */ + reg->BB58 = 0x64646464; + pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); + + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; - case RF_AIROHA_7230: -/* - pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4 - reg->BB0c = 0xFFFb203a; - pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5 - pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 - pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0x40000228; - pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl - reg->BB2c = 0x232A9F30; - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl - pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter - reg->BB3c = 0x00000000; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter - pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter - pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106200; - pltmp[9] = 0; // 0x1054 - reg->BB54 = 0x00000000; - pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha - reg->BB58 = 0x64645252; - pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); -*/ - BBProcessor_AL7230_2400( pHwData ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; + case RF_MAXIM_2829: + pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xf4ff1632; /* 0x100c AGC_Ctrl4 */ + reg->BB0C = 0xf4ff1632; + pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0xf8632112; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0x40000528; + pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */ + reg->BB2C = 0x232fdf30; /* antenna 1 */ + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); + + pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ + reg->BB30 = 0x00002C54; + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5b2c8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ + reg->BB3C = 0x00000000; + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = 0x002c2617; /* 0x1048 11b TX RC filter */ + pltmp[7] = 0x0800feff; /* 0x104c 11b TX RC filter */ + pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ + reg->BB50 = 0x27106208; + pltmp[9] = 0; /* 0x1054 */ + reg->BB54 = 0x00000000; + pltmp[10] = 0x64644a4a; /* 0x1058 IQ_Alpha */ + reg->BB58 = 0x64646464; + pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; + case RF_AIROHA_2230: + pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */ + reg->BB0C = 0xFFFd203c; + pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0X40000528; + pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */ + reg->BB2C = 0x232dfF30; /* antenna 1 */ + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); + + pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ + reg->BB30 = 0x00002C54; + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ + reg->BB3C = 0x00000000; + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */ + reg->BB48 = BB48_DEFAULT_AL2230_11G; /* 20051221 ch14 */ + pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */ + reg->BB4C = BB4C_DEFAULT_AL2230_11G; + pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */ + reg->BB50 = 0x27106200; + pltmp[9] = 0; /* 0x1054 */ + reg->BB54 = 0x00000000; + pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */ + reg->BB58 = 0x52524242; + pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); + + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; + case RF_AIROHA_2230S: + pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */ + reg->BB0C = 0xFFFd203c; + pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0X40000528; + pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */ + reg->BB2C = 0x232dfF30; /* antenna 1 */ + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); + + pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ + reg->BB30 = 0x00002C54; + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */ + reg->BB3C = 0x00000000; + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */ + reg->BB48 = BB48_DEFAULT_AL2230_11G; /* ch14 */ + pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */ + reg->BB4C = BB4C_DEFAULT_AL2230_11G; + pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */ + reg->BB50 = 0x27106200; + pltmp[9] = 0; /* 0x1054 */ + reg->BB54 = 0x00000000; + pltmp[10] = 0x52523232; /* 0x1058 IQ_Alpha */ + reg->BB58 = 0x52523232; + pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); + + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; + case RF_AIROHA_7230: + BBProcessor_AL7230_2400(pHwData); - case RF_WB_242: - case RF_WB_242_1: // 20060619.5 Add - - pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1 - pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2 - pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 - pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4 - reg->BB0C = 0xEEE91C32; - pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5 - pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6 - pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7 - pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 - pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440 - pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10 - pltmp[10] = 0x40000528; // 0x1028 - pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl - reg->BB2C = 0x23457F30; - Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); - - pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl - reg->BB30 = 0x00002C54; - pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl - pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl - pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter - reg->BB3C = pHwData->BB3c_cal; - pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter - pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter - pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2 - reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2 - pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2 - reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2 - pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl - reg->BB50 = 0x27106208; - pltmp[9] = pHwData->BB54_cal; // 0x1054 - reg->BB54 = pHwData->BB54_cal; - pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha - reg->BB58 = 0x52523131; - pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel - Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); - - Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); - break; - } + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; + case RF_WB_242: + case RF_WB_242_1: + pltmp[0] = 0x16A8525D; /* 0x1000 AGC_Ctrl1 */ + pltmp[1] = 0x9AFF9ABA; /* 0x1004 AGC_Ctrl2 */ + pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */ + pltmp[3] = 0xEEE91C32; /* 0x100c AGC_Ctrl4 */ + reg->BB0C = 0xEEE91C32; + pltmp[4] = 0x0FACDCC5; /* 0x1010 AGC_Ctrl5 */ + pltmp[5] = 0x000AA344; /* 0x1014 AGC_Ctrl6 */ + pltmp[6] = 0x22222221; /* 0x1018 AGC_Ctrl7 */ + pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */ + pltmp[8] = 0x04CC3440; /* 0x1020 AGC_Ctrl9 */ + pltmp[9] = 0xA9002A79; /* 0x1024 AGC_Ctrl10 */ + pltmp[10] = 0x40000528; /* 0x1028 */ + pltmp[11] = 0x23457F30; /* 0x102c A_ACQ_Ctrl */ + reg->BB2C = 0x23457F30; + Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT); + + pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */ + reg->BB30 = 0x00002C54; + pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */ + pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */ + pltmp[3] = pHwData->BB3c_cal; /* 0x103c 11a TX LS filter */ + reg->BB3C = pHwData->BB3c_cal; + pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */ + pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */ + pltmp[6] = BB48_DEFAULT_WB242_11G; /* 0x1048 11b TX RC filter */ + reg->BB48 = BB48_DEFAULT_WB242_11G; + pltmp[7] = BB4C_DEFAULT_WB242_11G; /* 0x104c 11b TX RC filter */ + reg->BB4C = BB4C_DEFAULT_WB242_11G; + pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */ + reg->BB50 = 0x27106208; + pltmp[9] = pHwData->BB54_cal; /* 0x1054 */ + reg->BB54 = pHwData->BB54_cal; + pltmp[10] = 0x52523131; /* 0x1058 IQ_Alpha */ + reg->BB58 = 0x52523131; + pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */ + Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT); + + Wb35Reg_Write(pHwData, 0x1070, 0x00000045); + break; + } - // Fill the LNA table - reg->LNAValue[0] = (u8)(reg->BB0C & 0xff); + /* Fill the LNA table */ + reg->LNAValue[0] = (u8) (reg->BB0C & 0xff); reg->LNAValue[1] = 0; - reg->LNAValue[2] = (u8)((reg->BB0C & 0xff00)>>8); + reg->LNAValue[2] = (u8) ((reg->BB0C & 0xff00) >> 8); reg->LNAValue[3] = 0; - // Fill SQ3 table - for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ ) - reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6 + /* Fill SQ3 table */ + for (i = 0; i < MAX_SQ3_FILTER_SIZE; i++) + reg->SQ3_filter[i] = 0x2f; /* half of Bit 0 ~ 6 */ } -void set_tx_power_per_channel_max2829( struct hw_data * pHwData, struct chan_info Channel) +void set_tx_power_per_channel_max2829(struct hw_data *pHwData, struct chan_info Channel) { - RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify + RFSynthesizer_SetPowerIndex(pHwData, 100); } -void set_tx_power_per_channel_al2230( struct hw_data * pHwData, struct chan_info Channel ) +void set_tx_power_per_channel_al2230(struct hw_data *pHwData, struct chan_info Channel) { u8 index = 100; - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add + if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; - RFSynthesizer_SetPowerIndex( pHwData, index ); + RFSynthesizer_SetPowerIndex(pHwData, index); } -void set_tx_power_per_channel_al7230( struct hw_data * pHwData, struct chan_info Channel) +void set_tx_power_per_channel_al7230(struct hw_data *pHwData, struct chan_info Channel) { u8 i, index = 100; - switch ( Channel.band ) - { - case BAND_TYPE_DSSS: - case BAND_TYPE_OFDM_24: - { - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) - index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; - } - break; - case BAND_TYPE_OFDM_5: - { - for (i =0; i<35; i++) - { - if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) - { - if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff) - index = pHwData->TxVgaFor50[i].TxVgaValue; - break; - } - } + switch (Channel.band) { + case BAND_TYPE_DSSS: + case BAND_TYPE_OFDM_24: + if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) + index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; + break; + case BAND_TYPE_OFDM_5: + for (i = 0; i < 35; i++) { + if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) { + if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff) + index = pHwData->TxVgaFor50[i].TxVgaValue; + break; } - break; + } + break; } - RFSynthesizer_SetPowerIndex( pHwData, index ); + RFSynthesizer_SetPowerIndex(pHwData, index); } -void set_tx_power_per_channel_wb242( struct hw_data * pHwData, struct chan_info Channel) +void set_tx_power_per_channel_wb242(struct hw_data *pHwData, struct chan_info Channel) { u8 index = 100; - switch ( Channel.band ) - { - case BAND_TYPE_DSSS: - case BAND_TYPE_OFDM_24: - { - if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) - index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; - } - break; - case BAND_TYPE_OFDM_5: - break; + switch (Channel.band) { + case BAND_TYPE_DSSS: + case BAND_TYPE_OFDM_24: + if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) + index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; + break; + case BAND_TYPE_OFDM_5: + break; } - RFSynthesizer_SetPowerIndex( pHwData, index ); + RFSynthesizer_SetPowerIndex(pHwData, index); } -//============================================================================================================= -// RFSynthesizer_SwitchingChannel -- -// -// Description: -// Swithch the RF channel. -// -// Arguments: -// pHwData - Handle of the USB Device. -// Channel - The channel no. -// -// Return values: -// None. -//============================================================================================================= -void -RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, struct chan_info Channel ) +/* + * ========================================================================== + * RFSynthesizer_SwitchingChannel -- + * + * Description: + * Swithch the RF channel. + * + * Arguments: + * pHwData - Handle of the USB Device. + * Channel - The channel no. + * + * Return values: + * None. + * =========================================================================== + */ +void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info Channel) { struct wb35_reg *reg = &pHwData->reg; - u32 pltmp[16]; // The 16 is the maximum capability of hardware + u32 pltmp[16]; /* The 16 is the maximum capability of hardware */ u32 count, ltmp; u8 i, j, number; u8 ChnlTmp; - switch( pHwData->phy_type ) - { - case RF_MAXIM_2825: - case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) - - if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 - { - for( i=0; i<3; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } - RFSynthesizer_SetPowerIndex( pHwData, 100 ); - break; - - case RF_MAXIM_2827: - - if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 - { - for( i=0; i<3; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } - else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64 - { - ChnlTmp = (Channel.ChanNo - 36) / 4; - for( i=0; i<3; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } - RFSynthesizer_SetPowerIndex( pHwData, 100 ); - break; - - case RF_MAXIM_2828: - - if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 - { - for( i=0; i<3; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } - else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64 - { - ChnlTmp = (Channel.ChanNo - 36) / 4; - for ( i = 0; i < 3; i++) - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } - RFSynthesizer_SetPowerIndex( pHwData, 100 ); - break; - - case RF_MAXIM_2829: + switch (pHwData->phy_type) { + case RF_MAXIM_2825: + case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */ - if( Channel.band <= BAND_TYPE_OFDM_24) - { - for( i=0; i<3; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } - else if( Channel.band == BAND_TYPE_OFDM_5 ) - { - count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]); - - for( i=0; i<count; i++ ) - { - if( max2829_channel_data_50[i][0] == Channel.ChanNo ) - { - for( j=0; j<3; j++ ) - pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - - if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 ) - { - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18); - Wb35Reg_Write( pHwData, 0x0864, ltmp ); - } - else // 0x2A9C6 - { - ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18); - Wb35Reg_Write( pHwData, 0x0864, ltmp ); - } + if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */ + for (i = 0; i < 3; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_channel_data_24[Channel.ChanNo-1][i], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + } + RFSynthesizer_SetPowerIndex(pHwData, 100); + break; + case RF_MAXIM_2827: + if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */ + for (i = 0; i < 3; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_24[Channel.ChanNo-1][i], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */ + ChnlTmp = (Channel.ChanNo - 36) / 4; + for (i = 0; i < 3; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_50[ChnlTmp][i], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + } + RFSynthesizer_SetPowerIndex(pHwData, 100); + break; + case RF_MAXIM_2828: + if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */ + for (i = 0; i < 3; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_24[Channel.ChanNo-1][i], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */ + ChnlTmp = (Channel.ChanNo - 36) / 4; + for (i = 0; i < 3; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_50[ChnlTmp][i], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + } + RFSynthesizer_SetPowerIndex(pHwData, 100); + break; + case RF_MAXIM_2829: + if (Channel.band <= BAND_TYPE_OFDM_24) { + for (i = 0; i < 3; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_24[Channel.ChanNo-1][i], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + } else if (Channel.band == BAND_TYPE_OFDM_5) { + count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]); + + for (i = 0; i < count; i++) { + if (max2829_channel_data_50[i][0] == Channel.ChanNo) { + for (j = 0; j < 3; j++) + pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_50[i][j+1], 18); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); + + if ((max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946) { + ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A906, 18); + Wb35Reg_Write(pHwData, 0x0864, ltmp); + } else { /* 0x2A9C6 */ + ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A986, 18); + Wb35Reg_Write(pHwData, 0x0864, ltmp); } } } - set_tx_power_per_channel_max2829( pHwData, Channel ); - break; - - case RF_AIROHA_2230: - case RF_AIROHA_2230S: // 20060420 Add this - - if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 - { - for( i=0; i<2; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT ); + } + set_tx_power_per_channel_max2829(pHwData, Channel); + break; + case RF_AIROHA_2230: + case RF_AIROHA_2230S: + if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ + for (i = 0; i < 2; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_channel_data_24[Channel.ChanNo-1][i], 20); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT); + } + set_tx_power_per_channel_al2230(pHwData, Channel); + break; + case RF_AIROHA_7230: + /* Channel independent registers */ + if (Channel.band != pHwData->band) { + if (Channel.band <= BAND_TYPE_OFDM_24) { + /* Update BB register */ + BBProcessor_AL7230_2400(pHwData); + + number = sizeof(al7230_rf_data_24) / sizeof(al7230_rf_data_24[0]); + Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); + } else { + /* Update BB register */ + BBProcessor_AL7230_5000(pHwData); + + number = sizeof(al7230_rf_data_50) / sizeof(al7230_rf_data_50[0]); + Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); } - set_tx_power_per_channel_al2230( pHwData, Channel ); - break; - case RF_AIROHA_7230: - - //Start to fill RF parameters, PLL_ON should be pulled low. - //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 ); - //printk("* PLL_ON low\n"); - - //Channel independent registers - if( Channel.band != pHwData->band) - { - if (Channel.band <= BAND_TYPE_OFDM_24) - { - //Update BB register - BBProcessor_AL7230_2400(pHwData); - - number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]); - Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); - } - else - { - //Update BB register - BBProcessor_AL7230_5000(pHwData); - - number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]); - Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); - } - - // Write to register. number must less and equal than 16 - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT ); - #ifdef _PE_STATE_DUMP_ - printk("Band changed\n"); - #endif - } + /* Write to register. number must less and equal than 16 */ + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT); + #ifdef _PE_STATE_DUMP_ + printk("Band changed\n"); + #endif + } - if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 - { - for( i=0; i<2; i++ ) - pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT ); + if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ + for (i = 0; i < 2; i++) + pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT); + } else if (Channel.band == BAND_TYPE_OFDM_5) { + /* Update Reg12 */ + if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) { + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c; + Wb35Reg_Write(pHwData, 0x0864, ltmp); + } else { /* reg12 = 0x00147c at Channel 4920 ~ 5320 */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c; + Wb35Reg_Write(pHwData, 0x0864, ltmp); } - else if( Channel.band == BAND_TYPE_OFDM_5 ) - { - //Update Reg12 - if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) - { - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c; - Wb35Reg_Write( pHwData, 0x0864, ltmp ); - } - else //reg12 = 0x00147c at Channel 4920 ~ 5320 - { - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c; - Wb35Reg_Write( pHwData, 0x0864, ltmp ); - } - count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]); + count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]); - for (i=0; i<count; i++) - { - if (al7230_channel_data_5[i][0] == Channel.ChanNo) - { - for( j=0; j<3; j++ ) - pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff); - Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); - } + for (i = 0; i < count; i++) { + if (al7230_channel_data_5[i][0] == Channel.ChanNo) { + for (j = 0; j < 3; j++) + pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_5[i][j+1] & 0xffffff); + Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT); } } - set_tx_power_per_channel_al7230(pHwData, Channel); - break; - - case RF_WB_242: - case RF_WB_242_1: // 20060619.5 Add + } + set_tx_power_per_channel_al7230(pHwData, Channel); + break; + case RF_WB_242: + case RF_WB_242_1: - if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 - { - ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24); - Wb35Reg_Write( pHwData, 0x864, ltmp ); - } - set_tx_power_per_channel_wb242(pHwData, Channel); - break; + if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */ + ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_channel_data_24[Channel.ChanNo-1][0], 24); + Wb35Reg_Write(pHwData, 0x864, ltmp); + } + set_tx_power_per_channel_wb242(pHwData, Channel); + break; } - if( Channel.band <= BAND_TYPE_OFDM_24 ) - { - // BB: select 2.4 GHz, bit[12-11]=00 - reg->BB50 &= ~(BIT(11)|BIT(12)); - Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl - // MAC: select 2.4 GHz, bit[5]=0 + if (Channel.band <= BAND_TYPE_OFDM_24) { + /* BB: select 2.4 GHz, bit[12-11]=00 */ + reg->BB50 &= ~(BIT(11) | BIT(12)); + Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */ + /* MAC: select 2.4 GHz, bit[5]=0 */ reg->M78_ERPInformation &= ~BIT(5); - Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation ); - // enable 11b Baseband + Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation); + /* enable 11b Baseband */ reg->BB30 &= ~BIT(31); - Wb35Reg_Write( pHwData, 0x1030, reg->BB30 ); - } - else if( (Channel.band == BAND_TYPE_OFDM_5) ) - { - // BB: select 5 GHz - reg->BB50 &= ~(BIT(11)|BIT(12)); - if (Channel.ChanNo <=64 ) - reg->BB50 |= BIT(12); // 10-5.25GHz + Wb35Reg_Write(pHwData, 0x1030, reg->BB30); + } else if (Channel.band == BAND_TYPE_OFDM_5) { + /* BB: select 5 GHz */ + reg->BB50 &= ~(BIT(11) | BIT(12)); + if (Channel.ChanNo <= 64) + reg->BB50 |= BIT(12); /* 10-5.25GHz */ else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124)) - reg->BB50 |= BIT(11); // 01-5.48GHz - else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161)) - reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz - else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 + reg->BB50 |= BIT(11); /* 01-5.48GHz */ + else if ((Channel.ChanNo >= 128) && (Channel.ChanNo <= 161)) + reg->BB50 |= (BIT(12) | BIT(11)); /* 11-5.775GHz */ + else /* Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 */ reg->BB50 |= BIT(12); - Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl + Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */ - //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 - //(2) BB30 has been updated previously. - if (pHwData->phy_type != RF_AIROHA_7230) - { - // MAC: select 5 GHz, bit[5]=1 + /* (1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 */ + /* (2) BB30 has been updated previously. */ + if (pHwData->phy_type != RF_AIROHA_7230) { + /* MAC: select 5 GHz, bit[5]=1 */ reg->M78_ERPInformation |= BIT(5); - Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation ); + Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation); - // disable 11b Baseband + /* disable 11b Baseband */ reg->BB30 |= BIT(31); - Wb35Reg_Write( pHwData, 0x1030, reg->BB30 ); + Wb35Reg_Write(pHwData, 0x1030, reg->BB30); } } } -//Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting -u8 RFSynthesizer_SetPowerIndex( struct hw_data * pHwData, u8 PowerIndex ) +/* + * Set the tx power directly from DUT GUI, not from the EEPROM. + * Return the current setting + */ +u8 RFSynthesizer_SetPowerIndex(struct hw_data *pHwData, u8 PowerIndex) { u32 Band = pHwData->band; - u8 index=0; + u8 index = 0; - if( pHwData->power_index == PowerIndex ) // 20060620.1 Add + if (pHwData->power_index == PowerIndex) return PowerIndex; - if (RF_MAXIM_2825 == pHwData->phy_type) - { - // Channel 1 - 13 - index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex ); - } - else if (RF_MAXIM_2827 == pHwData->phy_type) - { - if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13 - index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex ); - else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64 - index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex ); - } - else if (RF_MAXIM_2828 == pHwData->phy_type) - { - if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13 - index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex ); - else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64 - index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex ); - } - else if( RF_AIROHA_2230 == pHwData->phy_type ) - { - //Power index: 0 ~ 63 // Channel 1 - 14 - index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex ); - index = (u8)al2230_txvga_data[index][1]; - } - else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this - { - //Power index: 0 ~ 63 // Channel 1 - 14 - index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex ); - index = (u8)al2230_txvga_data[index][1]; - } - else if( RF_AIROHA_7230 == pHwData->phy_type ) - { - //Power index: 0 ~ 63 - index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex ); + if (RF_MAXIM_2825 == pHwData->phy_type) { + /* Channel 1 - 13 */ + index = RFSynthesizer_SetMaxim2825Power(pHwData, PowerIndex); + } else if (RF_MAXIM_2827 == pHwData->phy_type) { + if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */ + index = RFSynthesizer_SetMaxim2827_24Power(pHwData, PowerIndex); + else /* Channel 36 - 64 */ + index = RFSynthesizer_SetMaxim2827_50Power(pHwData, PowerIndex); + } else if (RF_MAXIM_2828 == pHwData->phy_type) { + if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */ + index = RFSynthesizer_SetMaxim2828_24Power(pHwData, PowerIndex); + else /* Channel 36 - 64 */ + index = RFSynthesizer_SetMaxim2828_50Power(pHwData, PowerIndex); + } else if (RF_AIROHA_2230 == pHwData->phy_type) { + /* Power index: 0 ~ 63 --- Channel 1 - 14 */ + index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex); + index = (u8) al2230_txvga_data[index][1]; + } else if (RF_AIROHA_2230S == pHwData->phy_type) { + /* Power index: 0 ~ 63 --- Channel 1 - 14 */ + index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex); + index = (u8) al2230_txvga_data[index][1]; + } else if (RF_AIROHA_7230 == pHwData->phy_type) { + /* Power index: 0 ~ 63 */ + index = RFSynthesizer_SetAiroha7230Power(pHwData, PowerIndex); index = (u8)al7230_txvga_data[index][1]; - } - else if( (RF_WB_242 == pHwData->phy_type) || - (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add - { - //Power index: 0 ~ 19 for original. New range is 0 ~ 33 - index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex ); + } else if ((RF_WB_242 == pHwData->phy_type) || + (RF_WB_242_1 == pHwData->phy_type)) { + /* Power index: 0 ~ 19 for original. New range is 0 ~ 33 */ + index = RFSynthesizer_SetWinbond242Power(pHwData, PowerIndex); index = (u8)w89rf242_txvga_data[index][1]; } - pHwData->power_index = index; // Backup current + pHwData->power_index = index; /* Backup current */ return index; } -//-- Sub function -u8 RFSynthesizer_SetMaxim2828_24Power( struct hw_data * pHwData, u8 index ) +/* -- Sub function */ +u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - if( index > 1 ) index = 1; - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + u32 PowerData; + if (index > 1) + index = 1; + PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_24[index], 18); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return index; } -//-- -u8 RFSynthesizer_SetMaxim2828_50Power( struct hw_data * pHwData, u8 index ) + +u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - if( index > 1 ) index = 1; - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + u32 PowerData; + if (index > 1) + index = 1; + PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_50[index], 18); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return index; } -//-- -u8 RFSynthesizer_SetMaxim2827_24Power( struct hw_data * pHwData, u8 index ) + +u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - if( index > 1 ) index = 1; - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + u32 PowerData; + if (index > 1) + index = 1; + PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_24[index], 18); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return index; } -//-- -u8 RFSynthesizer_SetMaxim2827_50Power( struct hw_data * pHwData, u8 index ) + +u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - if( index > 1 ) index = 1; - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + u32 PowerData; + if (index > 1) + index = 1; + PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_50[index], 18); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return index; } -//-- -u8 RFSynthesizer_SetMaxim2825Power( struct hw_data * pHwData, u8 index ) + +u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - if( index > 1 ) index = 1; - PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + u32 PowerData; + if (index > 1) + index = 1; + PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_power_data_24[index], 18); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return index; } -//-- -u8 RFSynthesizer_SetAiroha2230Power( struct hw_data * pHwData, u8 index ) + +u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - u8 i,count; + u32 PowerData; + u8 i, count; count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]); - for (i=0; i<count; i++) - { + for (i = 0; i < count; i++) { if (al2230_txvga_data[i][1] >= index) break; } if (i == count) i--; - PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_txvga_data[i][0], 20); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return i; } -//-- -u8 RFSynthesizer_SetAiroha7230Power( struct hw_data * pHwData, u8 index ) + +u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - u8 i,count; + u32 PowerData; + u8 i, count; - //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20); count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]); - for (i=0; i<count; i++) - { + for (i = 0; i < count; i++) { if (al7230_txvga_data[i][1] >= index) break; } if (i == count) i--; - PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); + PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0] & 0xffffff); + Wb35Reg_Write(pHwData, 0x0864, PowerData); return i; } -u8 RFSynthesizer_SetWinbond242Power( struct hw_data * pHwData, u8 index ) +u8 RFSynthesizer_SetWinbond242Power(struct hw_data *pHwData, u8 index) { - u32 PowerData; - u8 i,count; + u32 PowerData; + u8 i, count; count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]); - for (i=0; i<count; i++) - { + for (i = 0; i < count; i++) { if (w89rf242_txvga_data[i][1] >= index) break; } if (i == count) i--; - // Set TxVga into RF - PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24); - Wb35Reg_Write( pHwData, 0x0864, PowerData ); - - // Update BB48 BB4C BB58 for high precision txvga - Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] ); - Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] ); - Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] ); - -// Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss. -// The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register. -// if( i <= 3 ) -// PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 ); -// else -// PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 ); -// Wb35Reg_Write( pHwData, 0x0864, PowerData ); + /* Set TxVga into RF */ + PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_txvga_data[i][0], 24); + Wb35Reg_Write(pHwData, 0x0864, PowerData); + + /* Update BB48 BB4C BB58 for high precision txvga */ + Wb35Reg_Write(pHwData, 0x1048, w89rf242_txvga_data[i][2]); + Wb35Reg_Write(pHwData, 0x104c, w89rf242_txvga_data[i][3]); + Wb35Reg_Write(pHwData, 0x1058, w89rf242_txvga_data[i][4]); + return i; } -//=========================================================================================================== -// Dxx_initial -- -// Mxx_initial -- - // -// Routine Description: -// Initial the hardware setting and module variable - // -//=========================================================================================================== -void Dxx_initial( struct hw_data * pHwData ) +/* + * =========================================================================== + * Dxx_initial -- + * Mxx_initial -- + * + * Routine Description: + * Initial the hardware setting and module variable + * =========================================================================== + */ +void Dxx_initial(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; - // Old IC:Single mode only. - // New IC: operation decide by Software set bit[4]. 1:multiple 0: single - reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA - //Txon, Rxon, single Rx for old 8k ASIC - if( !HAL_USB_MODE_BURST( pHwData ) ) - reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA + /* + * Old IC: Single mode only. + * New IC: operation decide by Software set bit[4]. 1:multiple 0: single + */ + reg->D00_DmaControl = 0xc0000004; /* Txon, Rxon, multiple Rx for new 4k DMA */ + /* Txon, Rxon, single Rx for old 8k ASIC */ + if (!HAL_USB_MODE_BURST(pHwData)) + reg->D00_DmaControl = 0xc0000000; /* Txon, Rxon, single Rx for new 4k DMA */ - Wb35Reg_WriteSync( pHwData, 0x0400, reg->D00_DmaControl ); + Wb35Reg_WriteSync(pHwData, 0x0400, reg->D00_DmaControl); } -void Mxx_initial( struct hw_data * pHwData ) +void Mxx_initial(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; - u32 tmp; - u32 pltmp[11]; + u32 tmp; + u32 pltmp[11]; u16 i; - //====================================================== - // Initial Mxx register - //====================================================== + /* + * ====================================================== + * Initial Mxx register + * ====================================================== + */ - // M00 bit set -#ifdef _IBSS_BEACON_SEQ_STICK_ - reg->M00_MacControl = 0; // Solve beacon sequence number stop by software -#else - reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware -#endif + /* M00 bit set */ + #ifdef _IBSS_BEACON_SEQ_STICK_ + reg->M00_MacControl = 0; /* Solve beacon sequence number stop by software */ + #else + reg->M00_MacControl = 0x80000000; /* Solve beacon sequence number stop by hardware */ + #endif - // M24 disable enter power save, BB RxOn and enable NAV attack + /* M24 disable enter power save, BB RxOn and enable NAV attack */ reg->M24_MacControl = 0x08040042; pltmp[0] = reg->M24_MacControl; - pltmp[1] = 0; // Skip M28, because no initialize value is required. + pltmp[1] = 0; /* Skip M28, because no initialize value is required. */ - // M2C CWmin and CWmax setting + /* M2C CWmin and CWmax setting */ pHwData->cwmin = DEFAULT_CWMIN; pHwData->cwmax = DEFAULT_CWMAX; reg->M2C_MacControl = DEFAULT_CWMIN << 10; reg->M2C_MacControl |= DEFAULT_CWMAX; pltmp[2] = reg->M2C_MacControl; - // M30 BSSID + /* M30 BSSID */ pltmp[3] = *(u32 *)pHwData->bssid; - // M34 + /* M34 */ pHwData->AID = DEFAULT_AID; - tmp = *(u16 *)(pHwData->bssid+4); + tmp = *(u16 *) (pHwData->bssid + 4); tmp |= DEFAULT_AID << 16; pltmp[4] = tmp; - // M38 - reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT; + /* M38 */ + reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT << 8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT; pltmp[5] = reg->M38_MacControl; - // M3C + /* M3C */ tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ; reg->M3C_MacControl = tmp; pltmp[6] = tmp; - // M40 + /* M40 */ pHwData->slot_time_select = DEFAULT_SLOT_TIME; tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME; reg->M40_MacControl = tmp; pltmp[7] = tmp; - // M44 - tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024 + /* M44 */ + tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; /* *1024 */ reg->M44_MacControl = tmp; pltmp[8] = tmp; - // M48 + /* M48 */ pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL; pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME; tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME; reg->M48_MacControl = tmp; pltmp[9] = tmp; - //M4C + /* M4C */ reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24); pltmp[10] = reg->M4C_MacStatus; - // Burst write - //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT ); - for( i=0; i<11; i++ ) - Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] ); + for (i = 0; i < 11; i++) + Wb35Reg_WriteSync(pHwData, 0x0824 + i * 4, pltmp[i]); - // M60 - Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 ); + /* M60 */ + Wb35Reg_WriteSync(pHwData, 0x0860, 0x12481248); reg->M60_MacControl = 0x12481248; - // M68 - Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300 + /* M68 */ + Wb35Reg_WriteSync(pHwData, 0x0868, 0x00050900); reg->M68_MacControl = 0x00050900; - // M98 - Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 ); + /* M98 */ + Wb35Reg_WriteSync(pHwData, 0x0898, 0xffff8888); reg->M98_MacControl = 0xffff8888; } -void Uxx_power_off_procedure( struct hw_data * pHwData ) +void Uxx_power_off_procedure(struct hw_data *pHwData) { - // SW, PMU reset and turn off clock - Wb35Reg_WriteSync( pHwData, 0x03b0, 3 ); - Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 ); + /* SW, PMU reset and turn off clock */ + Wb35Reg_WriteSync(pHwData, 0x03b0, 3); + Wb35Reg_WriteSync(pHwData, 0x03f0, 0xf9); } -//Decide the TxVga of every channel -void GetTxVgaFromEEPROM( struct hw_data * pHwData ) +/*Decide the TxVga of every channel */ +void GetTxVgaFromEEPROM(struct hw_data *pHwData) { - u32 i, j, ltmp; - u16 Value[MAX_TXVGA_EEPROM]; - u8 *pctmp; - u8 ctmp=0; - - // Get the entire TxVga setting in EEPROM - for( i=0; i<MAX_TXVGA_EEPROM; i++ ) - { - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i ); - Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); - Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available - Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 .... + u32 i, j, ltmp; + u16 Value[MAX_TXVGA_EEPROM]; + u8 *pctmp; + u8 ctmp = 0; + + /* Get the entire TxVga setting in EEPROM */ + for (i = 0; i < MAX_TXVGA_EEPROM; i++) { + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000 + 0x00010000 * i); + Wb35Reg_ReadSync(pHwData, 0x03b4, <mp); + Value[i] = (u16) (ltmp & 0xffff); /* Get 16 bit available */ + Value[i] = cpu_to_le16(Value[i]); /* [7:0]2412 [7:0]2417 .... */ } - // Adjust the filed which fills with reserved value. - pctmp = (u8 *)Value; - for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ ) - { - if( pctmp[i] != 0xff ) + /* Adjust the filed which fills with reserved value. */ + pctmp = (u8 *) Value; + for (i = 0; i < (MAX_TXVGA_EEPROM * 2); i++) { + if (pctmp[i] != 0xff) ctmp = pctmp[i]; else pctmp[i] = ctmp; } - // Adjust WB_242 to WB_242_1 TxVga scale - if( pHwData->phy_type == RF_WB_242 ) - { - for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified - { - for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ ) - { - if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] ) - { - pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0]; + /* Adjust WB_242 to WB_242_1 TxVga scale */ + if (pHwData->phy_type == RF_WB_242) { + for (i = 0; i < 4; i++) { /* Only 2412 2437 2462 2484 case must be modified */ + for (j = 0; j < (sizeof(w89rf242_txvga_old_mapping) / sizeof(w89rf242_txvga_old_mapping[0])); j++) { + if (pctmp[i] < (u8) w89rf242_txvga_old_mapping[j][1]) { + pctmp[i] = (u8) w89rf242_txvga_old_mapping[j][0]; break; } } - if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) ) + if (j == (sizeof(w89rf242_txvga_old_mapping) / sizeof(w89rf242_txvga_old_mapping[0]))) pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0]; } } - // 20060621 Add - memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count - EEPROMTxVgaAdjust( pHwData ); + memcpy(pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM * 2); /* MAX_TXVGA_EEPROM is u16 count */ + EEPROMTxVgaAdjust(pHwData); } -// This function will affect the TxVga parameter in HAL. If hal_set_current_channel -// or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect. -// TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35 -// This function will use default TxVgaSettingInEEPROM data to calculate new TxVga. -void EEPROMTxVgaAdjust( struct hw_data * pHwData ) // 20060619.5 Add +/* + * This function will affect the TxVga parameter in HAL. If hal_set_current_channel + * or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect. + * TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35 + * This function will use default TxVgaSettingInEEPROM data to calculate new TxVga. + */ +void EEPROMTxVgaAdjust(struct hw_data *pHwData) { - u8 * pTxVga = pHwData->TxVgaSettingInEEPROM; - s16 i, stmp; + u8 *pTxVga = pHwData->TxVgaSettingInEEPROM; + s16 i, stmp; - //-- 2.4G -- 20060704.2 Request from Tiger - //channel 1 ~ 5 + /* -- 2.4G -- */ + /* channel 1 ~ 5 */ stmp = pTxVga[1] - pTxVga[0]; - for( i=0; i<5; i++ ) - pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4; - //channel 6 ~ 10 + for (i = 0; i < 5; i++) + pHwData->TxVgaFor24[i] = pTxVga[0] + stmp * i / 4; + /* channel 6 ~ 10 */ stmp = pTxVga[2] - pTxVga[1]; - for( i=5; i<10; i++ ) - pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4; - //channel 11 ~ 13 + for (i = 5; i < 10; i++) + pHwData->TxVgaFor24[i] = pTxVga[1] + stmp * (i - 5) / 4; + /* channel 11 ~ 13 */ stmp = pTxVga[3] - pTxVga[2]; - for( i=10; i<13; i++ ) - pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2; - //channel 14 + for (i = 10; i < 13; i++) + pHwData->TxVgaFor24[i] = pTxVga[2] + stmp * (i - 10) / 2; + /* channel 14 */ pHwData->TxVgaFor24[13] = pTxVga[3]; - //-- 5G -- - if( pHwData->phy_type == RF_AIROHA_7230 ) - { - //channel 184 + /* -- 5G -- */ + if (pHwData->phy_type == RF_AIROHA_7230) { + /* channel 184 */ pHwData->TxVgaFor50[0].ChanNo = 184; pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4]; - //channel 196 + /* channel 196 */ pHwData->TxVgaFor50[3].ChanNo = 196; pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[1].ChanNo = 188; pHwData->TxVgaFor50[2].ChanNo = 192; stmp = pTxVga[5] - pTxVga[4]; - pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3; - pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3; + pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp / 3; + pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp * 2 / 3; - //channel 16 + /* channel 16 */ pHwData->TxVgaFor50[6].ChanNo = 16; pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6]; pHwData->TxVgaFor50[4].ChanNo = 8; @@ -2523,7 +2250,7 @@ void EEPROMTxVgaAdjust( struct hw_data * pHwData ) // 20060619.5 Add pHwData->TxVgaFor50[5].ChanNo = 12; pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6]; - //channel 36 + /* channel 36 */ pHwData->TxVgaFor50[8].ChanNo = 36; pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7]; pHwData->TxVgaFor50[7].ChanNo = 34; @@ -2531,153 +2258,135 @@ void EEPROMTxVgaAdjust( struct hw_data * pHwData ) // 20060619.5 Add pHwData->TxVgaFor50[9].ChanNo = 38; pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7]; - //channel 40 + /* channel 40 */ pHwData->TxVgaFor50[10].ChanNo = 40; pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8]; - //channel 48 + /* channel 48 */ pHwData->TxVgaFor50[14].ChanNo = 48; pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[11].ChanNo = 42; pHwData->TxVgaFor50[12].ChanNo = 44; pHwData->TxVgaFor50[13].ChanNo = 46; stmp = pTxVga[9] - pTxVga[8]; - pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4; - pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4; - pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4; + pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp / 4; + pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp * 2 / 4; + pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp * 3 / 4; - //channel 52 + /* channel 52 */ pHwData->TxVgaFor50[15].ChanNo = 52; pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10]; - //channel 64 + /* channel 64 */ pHwData->TxVgaFor50[18].ChanNo = 64; pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[16].ChanNo = 56; pHwData->TxVgaFor50[17].ChanNo = 60; stmp = pTxVga[11] - pTxVga[10]; - pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3; - pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3; + pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp / 3; + pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp * 2 / 3; - //channel 100 + /* channel 100 */ pHwData->TxVgaFor50[19].ChanNo = 100; pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12]; - //channel 112 + /* channel 112 */ pHwData->TxVgaFor50[22].ChanNo = 112; pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[20].ChanNo = 104; pHwData->TxVgaFor50[21].ChanNo = 108; stmp = pTxVga[13] - pTxVga[12]; - pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3; - pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3; + pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp / 3; + pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp * 2 / 3; - //channel 128 + /* channel 128 */ pHwData->TxVgaFor50[26].ChanNo = 128; pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[23].ChanNo = 116; pHwData->TxVgaFor50[24].ChanNo = 120; pHwData->TxVgaFor50[25].ChanNo = 124; stmp = pTxVga[14] - pTxVga[13]; - pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4; - pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4; - pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4; + pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp / 4; + pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp * 2 / 4; + pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp * 3 / 4; - //channel 140 + /* channel 140 */ pHwData->TxVgaFor50[29].ChanNo = 140; pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[27].ChanNo = 132; pHwData->TxVgaFor50[28].ChanNo = 136; stmp = pTxVga[15] - pTxVga[14]; - pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3; - pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3; + pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp / 3; + pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp * 2 / 3; - //channel 149 + /* channel 149 */ pHwData->TxVgaFor50[30].ChanNo = 149; pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16]; - //channel 165 + /* channel 165 */ pHwData->TxVgaFor50[34].ChanNo = 165; pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17]; - //interpolate + /* interpolate */ pHwData->TxVgaFor50[31].ChanNo = 153; pHwData->TxVgaFor50[32].ChanNo = 157; pHwData->TxVgaFor50[33].ChanNo = 161; stmp = pTxVga[17] - pTxVga[16]; - pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4; - pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4; - pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4; + pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp / 4; + pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp * 2 / 4; + pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp * 3 / 4; } #ifdef _PE_STATE_DUMP_ - printk(" TxVgaFor24 : \n"); - DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0); - printk(" TxVgaFor50 : \n"); - DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0); + printk(" TxVgaFor24 :\n"); + DataDmp((u8 *)pHwData->TxVgaFor24, 14 , 0); + printk(" TxVgaFor50 :\n"); + DataDmp((u8 *)pHwData->TxVgaFor50, 70 , 0); #endif } -void BBProcessor_RateChanging( struct hw_data * pHwData, u8 rate ) // 20060613.1 +void BBProcessor_RateChanging(struct hw_data *pHwData, u8 rate) { struct wb35_reg *reg = &pHwData->reg; - unsigned char Is11bRate; + unsigned char Is11bRate; Is11bRate = (rate % 6) ? 1 : 0; - switch( pHwData->phy_type ) - { - case RF_AIROHA_2230: - case RF_AIROHA_2230S: // 20060420 Add this - if( Is11bRate ) - { - if( (reg->BB48 != BB48_DEFAULT_AL2230_11B) && - (reg->BB4C != BB4C_DEFAULT_AL2230_11B) ) - { - Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B ); - Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B ); - } + switch (pHwData->phy_type) { + case RF_AIROHA_2230: + case RF_AIROHA_2230S: + if (Is11bRate) { + if ((reg->BB48 != BB48_DEFAULT_AL2230_11B) && + (reg->BB4C != BB4C_DEFAULT_AL2230_11B)) { + Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11B); + Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B); } - else - { - if( (reg->BB48 != BB48_DEFAULT_AL2230_11G) && - (reg->BB4C != BB4C_DEFAULT_AL2230_11G) ) - { - Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G ); - Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G ); - } + } else { + if ((reg->BB48 != BB48_DEFAULT_AL2230_11G) && + (reg->BB4C != BB4C_DEFAULT_AL2230_11G)) { + Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11G); + Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G); } - break; - - case RF_WB_242: // 20060623 The fix only for old TxVGA setting - if( Is11bRate ) - { - if( (reg->BB48 != BB48_DEFAULT_WB242_11B) && - (reg->BB4C != BB4C_DEFAULT_WB242_11B) ) - { - reg->BB48 = BB48_DEFAULT_WB242_11B; - reg->BB4C = BB4C_DEFAULT_WB242_11B; - Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B ); - Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B ); - } + } + break; + case RF_WB_242: + if (Is11bRate) { + if ((reg->BB48 != BB48_DEFAULT_WB242_11B) && + (reg->BB4C != BB4C_DEFAULT_WB242_11B)) { + reg->BB48 = BB48_DEFAULT_WB242_11B; + reg->BB4C = BB4C_DEFAULT_WB242_11B; + Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11B); + Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11B); } - else - { - if( (reg->BB48 != BB48_DEFAULT_WB242_11G) && - (reg->BB4C != BB4C_DEFAULT_WB242_11G) ) - { - reg->BB48 = BB48_DEFAULT_WB242_11G; - reg->BB4C = BB4C_DEFAULT_WB242_11G; - Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G ); - Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G ); - } + } else { + if ((reg->BB48 != BB48_DEFAULT_WB242_11G) && + (reg->BB4C != BB4C_DEFAULT_WB242_11G)) { + reg->BB48 = BB48_DEFAULT_WB242_11G; + reg->BB4C = BB4C_DEFAULT_WB242_11G; + Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11G); + Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11G); } - break; + } + break; } } - - - - - - diff --git a/drivers/staging/winbond/scan_s.h b/drivers/staging/winbond/scan_s.h index 209717f5d47..85e7523196d 100644 --- a/drivers/staging/winbond/scan_s.h +++ b/drivers/staging/winbond/scan_s.h @@ -4,117 +4,107 @@ #include <linux/types.h> #include "localpara.h" -// -// SCAN task global CONSTANTS, STRUCTURES, variables -// - -////////////////////////////////////////////////////////////////////////// -//define the msg type of SCAN module -#define SCANMSG_SCAN_REQ 0x01 -#define SCANMSG_BEACON 0x02 +/* + * SCAN task global CONSTANTS, STRUCTURES, variables + */ + +/* define the msg type of SCAN module */ +#define SCANMSG_SCAN_REQ 0x01 +#define SCANMSG_BEACON 0x02 #define SCANMSG_PROBE_RESPONSE 0x03 -#define SCANMSG_TIMEOUT 0x04 +#define SCANMSG_TIMEOUT 0x04 #define SCANMSG_TXPROBE_FAIL 0x05 #define SCANMSG_ENABLE_BGSCAN 0x06 -#define SCANMSG_STOP_SCAN 0x07 +#define SCANMSG_STOP_SCAN 0x07 -// BSS Type =>conform to -// IBSS : ToDS/FromDS = 00 -// Infrastructure : ToDS/FromDS = 01 +/* + * BSS Type =>conform to + * IBSS : ToDS/FromDS = 00 + * Infrastructure : ToDS/FromDS = 01 + */ #define IBSS_NET 0 #define ESS_NET 1 #define ANYBSS_NET 2 -// Scan Type +/* Scan Type */ #define ACTIVE_SCAN 0 -#define PASSIVE_SCAN 1 +#define PASSIVE_SCAN 1 + +/* Global data structures, Initial Scan & Background Scan */ +typedef struct _SCAN_REQ_PARA { /* mandatory parameters for SCAN request */ -/////////////////////////////////////////////////////////////////////////// -//Global data structures, Initial Scan & Background Scan -typedef struct _SCAN_REQ_PARA //mandatory parameters for SCAN request -{ - u32 ScanType; //passive/active scan + u32 ScanType; /* passive/active scan */ u8 reserved_1[2]; - struct SSID_Element sSSID; // 34B. scan only for this SSID + struct SSID_Element sSSID; /* 34B. scan only for this SSID */ u8 reserved_2[2]; } SCAN_REQ_PARA, *psSCAN_REQ_PARA; -typedef struct _SCAN_PARAMETERS -{ - u16 wState; - u16 iCurrentChannelIndex; +typedef struct _SCAN_PARAMETERS { + u16 wState; + u16 iCurrentChannelIndex; SCAN_REQ_PARA sScanReq; - u8 BSSID[MAC_ADDR_LENGTH + 2]; //scan only for this BSSID + u8 BSSID[MAC_ADDR_LENGTH + 2]; /* scan only for this BSSID */ - u32 BssType; //scan only for this BSS type + u32 BssType; /* scan only for this BSS type */ - //struct SSID_Element sSSID; //scan only for this SSID - u16 ProbeDelay; - u16 MinChannelTime; + u16 ProbeDelay; + u16 MinChannelTime; - u16 MaxChannelTime; - u16 reserved_1; + u16 MaxChannelTime; + u16 reserved_1; - s32 iBgScanPeriod; // XP: 5 sec + s32 iBgScanPeriod; /* XP: 5 sec */ - u8 boBgScan; // Wb: enable BG scan, For XP, this value must be FALSE - u8 boFastScan; // Wb: reserved - u8 boCCAbusy; // Wb: HWMAC CCA busy status - u8 reserved_2; + u8 boBgScan; /* Wb: enable BG scan, For XP, this value must be FALSE */ + u8 boFastScan; /* Wb: reserved */ + u8 boCCAbusy; /* Wb: HWMAC CCA busy status */ + u8 reserved_2; struct timer_list timer; - u32 ScanTimeStamp; //Increase 1 per background scan(1 minute) - u32 BssTimeStamp; //Increase 1 per connect status check - u32 RxNumPerAntenna[2]; // - - u8 AntennaToggle; // - u8 boInTimerHandler; - u8 boTimerActive; // Wb: reserved - u8 boSave; + u32 ScanTimeStamp; /* Increase 1 per background scan(1 minute) */ + u32 BssTimeStamp; /* Increase 1 per connect status check */ + u32 RxNumPerAntenna[2]; - u32 BScanEnable; // Background scan enable. Default is On + u8 AntennaToggle; + u8 boInTimerHandler; + u8 boTimerActive; /* Wb: reserved */ + u8 boSave; + u32 BScanEnable; /* Background scan enable. Default is On */ } SCAN_PARAMETERS, *psSCAN_PARAMETERS; -// Encapsulate 'adapter' data structure -#define psSCAN (&(adapter->sScanPara)) -#define psSCANREQ (&(adapter->sScanPara.sScanReq)) - -//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -// scan.h -// Define the related definitions of scan module -// history -- 01/14/03' created -// -//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -//Define the state of scan module -#define SCAN_INACTIVE 0 -#define WAIT_PROBE_DELAY 1 -#define WAIT_RESPONSE_MIN 2 -#define WAIT_RESPONSE_MAX_ACTIVE 3 -#define WAIT_BEACON_MAX_PASSIVE 4 -#define SCAN_COMPLETE 5 -#define BG_SCAN 6 -#define BG_SCANNING 7 - - -// The value will load from EEPROM -// If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead. -// The definition is in WbHal.h -// #define SCAN_MAX_CHNL_TIME (50) - - - -// static functions - -//static void ScanTimerHandler(struct wbsoft_priv * adapter); -//static void vScanTimerStart(struct wbsoft_priv * adapter, int timeout_value); -//static void vScanTimerStop(struct wbsoft_priv * adapter); - +/* Encapsulate 'adapter' data structure */ +#define psSCAN (&(adapter->sScanPara)) +#define psSCANREQ (&(adapter->sScanPara.sScanReq)) + +/* + * =========================================================== + * scan.h + * Define the related definitions of scan module + * + * =========================================================== + */ + +/* Define the state of scan module */ +#define SCAN_INACTIVE 0 +#define WAIT_PROBE_DELAY 1 +#define WAIT_RESPONSE_MIN 2 +#define WAIT_RESPONSE_MAX_ACTIVE 3 +#define WAIT_BEACON_MAX_PASSIVE 4 +#define SCAN_COMPLETE 5 +#define BG_SCAN 6 +#define BG_SCANNING 7 + + +/* + * The value will load from EEPROM + * If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead. + * The definition is in WbHal.h + */ #endif diff --git a/drivers/staging/winbond/sme_api.h b/drivers/staging/winbond/sme_api.h index b5898294eb8..8f4596c9e9b 100644 --- a/drivers/staging/winbond/sme_api.h +++ b/drivers/staging/winbond/sme_api.h @@ -2,12 +2,6 @@ * sme_api.h * * Copyright(C) 2002 Winbond Electronics Corp. - * - * modification history - * --------------------------------------------------------------------------- - * 1.00.001, 2003-04-21, Kevin created - * 1.00.002, 2003-05-14, PD43 & PE20 modified - * */ #ifndef __SME_API_H__ @@ -18,42 +12,42 @@ #include "localpara.h" /****************** CONSTANT AND MACRO SECTION ******************************/ -#define _INLINE __inline +#define _INLINE __inline -#define MEDIA_STATE_DISCONNECTED 0 -#define MEDIA_STATE_CONNECTED 1 +#define MEDIA_STATE_DISCONNECTED 0 +#define MEDIA_STATE_CONNECTED 1 -//ARRAY CHECK -#define MAX_POWER_TO_DB 32 +/* ARRAY CHECK */ +#define MAX_POWER_TO_DB 32 /****************** TYPE DEFINITION SECTION *********************************/ /****************** EXPORTED FUNCTION DECLARATION SECTION *******************/ -// OID_802_11_BSSID +/* OID_802_11_BSSID */ s8 sme_get_bssid(void *pcore_data, u8 *pbssid); -s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid);//Not use +s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid); /* Not use */ s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid); -// OID_802_11_SSID +/* OID_802_11_SSID */ s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len); -s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);// Not use +s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);/* Not use */ s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len); -// OID_802_11_INFRASTRUCTURE_MODE +/* OID_802_11_INFRASTRUCTURE_MODE */ s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type); -s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type);//Not use +s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type); /* Not use */ s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type); -// OID_802_11_FRAGMENTATION_THRESHOLD +/* OID_802_11_FRAGMENTATION_THRESHOLD */ s8 sme_get_fragment_threshold(void *pcore_data, u32 *pthreshold); s8 sme_set_fragment_threshold(void *pcore_data, u32 threshold); -// OID_802_11_RTS_THRESHOLD +/* OID_802_11_RTS_THRESHOLD */ s8 sme_get_rts_threshold(void *pcore_data, u32 *pthreshold); s8 sme_set_rts_threshold(void *pcore_data, u32 threshold); -// OID_802_11_CONFIGURATION +/* OID_802_11_CONFIGURATION */ s8 sme_get_beacon_period(void *pcore_data, u16 *pbeacon_period); s8 sme_set_beacon_period(void *pcore_data, u16 beacon_period); @@ -64,116 +58,69 @@ s8 sme_get_current_channel(void *pcore_data, u8 *pcurrent_channel); s8 sme_get_current_band(void *pcore_data, u8 *pcurrent_band); s8 sme_set_current_channel(void *pcore_data, u8 current_channel); -// OID_802_11_BSSID_LIST +/* OID_802_11_BSSID_LIST */ s8 sme_get_scan_bss_count(void *pcore_data, u8 *pcount); s8 sme_get_scan_bss(void *pcore_data, u8 index, void **ppbss); s8 sme_get_connected_bss(void *pcore_data, void **ppbss_now); -// OID_802_11_AUTHENTICATION_MODE +/* OID_802_11_AUTHENTICATION_MODE */ s8 sme_get_auth_mode(void *pcore_data, u8 *pauth_mode); s8 sme_set_auth_mode(void *pcore_data, u8 auth_mode); -// OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS +/* OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS */ s8 sme_get_wep_mode(void *pcore_data, u8 *pwep_mode); s8 sme_set_wep_mode(void *pcore_data, u8 wep_mode); -//s8 sme_get_encryption_status(void *pcore_data, u8 *pstatus); -//s8 sme_set_encryption_status(void *pcore_data, u8 status); - -// ??????????????????????????????????????? -// OID_GEN_VENDOR_ID -// OID_802_3_PERMANENT_ADDRESS +/* OID_GEN_VENDOR_ID */ +/* OID_802_3_PERMANENT_ADDRESS */ s8 sme_get_permanent_mac_addr(void *pcore_data, u8 *pmac_addr); -// OID_802_3_CURRENT_ADDRESS +/* OID_802_3_CURRENT_ADDRESS */ s8 sme_get_current_mac_addr(void *pcore_data, u8 *pmac_addr); -// OID_802_11_NETWORK_TYPE_IN_USE +/* OID_802_11_NETWORK_TYPE_IN_USE */ s8 sme_get_network_type_in_use(void *pcore_data, u8 *ptype); s8 sme_set_network_type_in_use(void *pcore_data, u8 type); -// OID_802_11_SUPPORTED_RATES +/* OID_802_11_SUPPORTED_RATES */ s8 sme_get_supported_rate(void *pcore_data, u8 *prates); -// OID_802_11_ADD_WEP -//12/29/03' wkchen +/* OID_802_11_ADD_WEP */ s8 sme_set_add_wep(void *pcore_data, u32 key_index, u32 key_len, u8 *Address, u8 *key); -// OID_802_11_REMOVE_WEP +/* OID_802_11_REMOVE_WEP */ s8 sme_set_remove_wep(void *pcre_data, u32 key_index); -// OID_802_11_DISASSOCIATE +/* OID_802_11_DISASSOCIATE */ s8 sme_set_disassociate(void *pcore_data); -// OID_802_11_POWER_MODE +/* OID_802_11_POWER_MODE */ s8 sme_get_power_mode(void *pcore_data, u8 *pmode); s8 sme_set_power_mode(void *pcore_data, u8 mode); -// OID_802_11_BSSID_LIST_SCAN +/* OID_802_11_BSSID_LIST_SCAN */ s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para); -// OID_802_11_RELOAD_DEFAULTS +/* OID_802_11_RELOAD_DEFAULTS */ s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type); -// The following SME API functions are used for WPA -// -// Mandatory OIDs for WPA -// - -// OID_802_11_ADD_KEY -//s8 sme_set_add_key(void *pcore_data, NDIS_802_11_KEY *pkey); - -// OID_802_11_REMOVE_KEY -//s8 sme_set_remove_key(void *pcore_data, NDIS_802_11_REMOVE_KEY *pkey); - -// OID_802_11_ASSOCIATION_INFORMATION -//s8 sme_set_association_information(void *pcore_data, -// NDIS_802_11_ASSOCIATION_INFORMATION *pinfo); - -// OID_802_11_TEST -//s8 sme_set_test(void *pcore_data, NDIS_802_11_TEST *ptest_data); - -//--------------------------------------------------------------------------// -/* -// The left OIDs - -// OID_802_11_NETWORK_TYPES_SUPPORTED -// OID_802_11_TX_POWER_LEVEL -// OID_802_11_RSSI_TRIGGER -// OID_802_11_NUMBER_OF_ANTENNAS -// OID_802_11_RX_ANTENNA_SELECTED -// OID_802_11_TX_ANTENNA_SELECTED -// OID_802_11_STATISTICS -// OID_802_11_DESIRED_RATES -// OID_802_11_PRIVACY_FILTER - -*/ - /*------------------------- none-standard ----------------------------------*/ s8 sme_get_connect_status(void *pcore_data, u8 *pstatus); - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -//s8 sme_get_scan_type(void *pcore_data, u8 *pscan_type); -//s8 sme_set_scan_type(void *pcore_data, u8 scan_type); - -//s8 sme_get_scan_channel_list(void *pcore_data, u8 *pscan_type); -//s8 sme_set_scan_channel_list(void *pcore_data, u8 scan_type); - +/*--------------------------------------------------------------------------*/ void sme_get_encryption_status(void *pcore_data, u8 *EncryptStatus); void sme_set_encryption_status(void *pcore_data, u8 EncryptStatus); -s8 sme_add_key(void *pcore_data, - u32 key_index, - u8 key_len, - u8 key_type, - u8 *key_bssid, - //u8 *key_rsc, - u8 *ptx_tsc, - u8 *prx_tsc, - u8 *key_material); +s8 sme_add_key(void *pcore_data, + u32 key_index, + u8 key_len, + u8 key_type, + u8 *key_bssid, + u8 *ptx_tsc, + u8 *prx_tsc, + u8 *key_material); void sme_remove_default_key(void *pcore_data, int index); void sme_remove_mapping_key(void *pcore_data, u8 *pmac_addr); void sme_clear_all_mapping_key(void *pcore_data); @@ -202,60 +149,44 @@ u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna); void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna); s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna); s8 sme_set_IBSS_chan(void *pcore_data, struct chan_info chan); - -//20061108 WPS s8 sme_set_IE_append(void *pcore_data, u8 *buffer, u16 buf_len); - - - -//================== Local functions ====================== -//#ifdef _HSINCHU -//void drv_translate_rssi(); // HW RSSI bit -> NDIS RSSI representation -//void drv_translate_bss_description(); // Local bss desc -> NDIS bss desc -//void drv_translate_channel(u8 NetworkType, u8 ChannelNumber, u32 *freq); // channel number -> channel /freq. -//#endif _HSINCHU -// -static const u32 PowerDbToMw[] = -{ - 56, //mW, MAX - 0, 17.5 dbm - 40, //mW, MAX - 1, 16.0 dbm - 30, //mW, MAX - 2, 14.8 dbm - 20, //mW, MAX - 3, 13.0 dbm - 15, //mW, MAX - 4, 11.8 dbm - 12, //mW, MAX - 5, 10.6 dbm - 9, //mW, MAX - 6, 9.4 dbm - 7, //mW, MAX - 7, 8.3 dbm - 5, //mW, MAX - 8, 6.4 dbm - 4, //mW, MAX - 9, 5.3 dbm - 3, //mW, MAX - 10, 4.0 dbm - 2, //mW, MAX - 11, ? dbm - 2, //mW, MAX - 12, ? dbm - 2, //mW, MAX - 13, ? dbm - 2, //mW, MAX - 14, ? dbm - 2, //mW, MAX - 15, ? dbm - 2, //mW, MAX - 16, ? dbm - 2, //mW, MAX - 17, ? dbm - 2, //mW, MAX - 18, ? dbm - 1, //mW, MAX - 19, ? dbm - 1, //mW, MAX - 20, ? dbm - 1, //mW, MAX - 21, ? dbm - 1, //mW, MAX - 22, ? dbm - 1, //mW, MAX - 23, ? dbm - 1, //mW, MAX - 24, ? dbm - 1, //mW, MAX - 25, ? dbm - 1, //mW, MAX - 26, ? dbm - 1, //mW, MAX - 27, ? dbm - 1, //mW, MAX - 28, ? dbm - 1, //mW, MAX - 29, ? dbm - 1, //mW, MAX - 30, ? dbm - 1 //mW, MAX - 31, ? dbm +/* ================== Local functions ====================== */ +static const u32 PowerDbToMw[] = { + 56, /* mW, MAX - 0, 17.5 dbm */ + 40, /* mW, MAX - 1, 16.0 dbm */ + 30, /* mW, MAX - 2, 14.8 dbm */ + 20, /* mW, MAX - 3, 13.0 dbm */ + 15, /* mW, MAX - 4, 11.8 dbm */ + 12, /* mW, MAX - 5, 10.6 dbm */ + 9, /* mW, MAX - 6, 9.4 dbm */ + 7, /* mW, MAX - 7, 8.3 dbm */ + 5, /* mW, MAX - 8, 6.4 dbm */ + 4, /* mW, MAX - 9, 5.3 dbm */ + 3, /* mW, MAX - 10, 4.0 dbm */ + 2, /* mW, MAX - 11, ? dbm */ + 2, /* mW, MAX - 12, ? dbm */ + 2, /* mW, MAX - 13, ? dbm */ + 2, /* mW, MAX - 14, ? dbm */ + 2, /* mW, MAX - 15, ? dbm */ + 2, /* mW, MAX - 16, ? dbm */ + 2, /* mW, MAX - 17, ? dbm */ + 2, /* mW, MAX - 18, ? dbm */ + 1, /* mW, MAX - 19, ? dbm */ + 1, /* mW, MAX - 20, ? dbm */ + 1, /* mW, MAX - 21, ? dbm */ + 1, /* mW, MAX - 22, ? dbm */ + 1, /* mW, MAX - 23, ? dbm */ + 1, /* mW, MAX - 24, ? dbm */ + 1, /* mW, MAX - 25, ? dbm */ + 1, /* mW, MAX - 26, ? dbm */ + 1, /* mW, MAX - 27, ? dbm */ + 1, /* mW, MAX - 28, ? dbm */ + 1, /* mW, MAX - 29, ? dbm */ + 1, /* mW, MAX - 30, ? dbm */ + 1 /* mW, MAX - 31, ? dbm */ }; - - - - #endif /* __SME_API_H__ */ diff --git a/drivers/staging/winbond/sysdef.h b/drivers/staging/winbond/sysdef.h index 251b9c553b6..9195adf98e1 100644 --- a/drivers/staging/winbond/sysdef.h +++ b/drivers/staging/winbond/sysdef.h @@ -1,31 +1,19 @@ +/* Winbond WLAN System Configuration defines */ - -// -// Winbond WLAN System Configuration defines -// - -//===================================================================== -// Current directory is Linux -// The definition WB_LINUX is a keyword for this OS -//===================================================================== #ifndef SYS_DEF_H #define SYS_DEF_H #define WB_LINUX #define WB_LINUX_WPA_PSK - -//#define _IBSS_BEACON_SEQ_STICK_ #define _USE_FALLBACK_RATE_ -//#define ANTDIV_DEFAULT_ON - -#define _WPA2_ // 20061122 It's needed for current Linux driver +#define _WPA2_ #ifndef _WPA_PSK_DEBUG #undef _WPA_PSK_DEBUG #endif -// debug print options, mark what debug you don't need +/* debug print options, mark what debug you don't need */ #ifdef FULL_DEBUG #define _PE_STATE_DUMP_ diff --git a/drivers/staging/winbond/wb35reg.c b/drivers/staging/winbond/wb35reg.c index 1b93547ff5b..770722385ee 100644 --- a/drivers/staging/winbond/wb35reg.c +++ b/drivers/staging/winbond/wb35reg.c @@ -6,60 +6,61 @@ extern void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency); -// true : read command process successfully -// false : register not support -// RegisterNo : start base -// pRegisterData : data point -// NumberOfData : number of register data -// Flag : AUTO_INCREMENT - RegisterNo will auto increment 4 -// NO_INCREMENT - Function will write data into the same register -unsigned char -Wb35Reg_BurstWrite(struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag) +/* + * true : read command process successfully + * false : register not support + * RegisterNo : start base + * pRegisterData : data point + * NumberOfData : number of register data + * Flag : AUTO_INCREMENT - RegisterNo will auto increment 4 + * NO_INCREMENT - Function will write data into the same register + */ +unsigned char Wb35Reg_BurstWrite(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegisterData, u8 NumberOfData, u8 Flag) { - struct wb35_reg *reg = &pHwData->reg; - struct urb *urb = NULL; - struct wb35_reg_queue *reg_queue = NULL; - u16 UrbSize; - struct usb_ctrlrequest *dr; - u16 i, DataSize = NumberOfData*4; - - // Module shutdown + struct wb35_reg *reg = &pHwData->reg; + struct urb *urb = NULL; + struct wb35_reg_queue *reg_queue = NULL; + u16 UrbSize; + struct usb_ctrlrequest *dr; + u16 i, DataSize = NumberOfData * 4; + + /* Module shutdown */ if (pHwData->SurpriseRemove) return false; - // Trying to use burst write function if use new hardware + /* Trying to use burst write function if use new hardware */ UrbSize = sizeof(struct wb35_reg_queue) + DataSize + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); urb = usb_alloc_urb(0, GFP_ATOMIC); - if( urb && reg_queue ) { - reg_queue->DIRECT = 2;// burst write register + if (urb && reg_queue) { + reg_queue->DIRECT = 2; /* burst write register */ reg_queue->INDEX = RegisterNo; reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - memcpy( reg_queue->pBuffer, pRegisterData, DataSize ); - //the function for reversing register data from little endian to big endian - for( i=0; i<NumberOfData ; i++ ) - reg_queue->pBuffer[i] = cpu_to_le32( reg_queue->pBuffer[i] ); + memcpy(reg_queue->pBuffer, pRegisterData, DataSize); + /* the function for reversing register data from little endian to big endian */ + for (i = 0; i < NumberOfData ; i++) + reg_queue->pBuffer[i] = cpu_to_le32(reg_queue->pBuffer[i]); dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize); dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; - dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode - dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment - dr->wIndex = cpu_to_le16( RegisterNo ); - dr->wLength = cpu_to_le16( DataSize ); + dr->bRequest = 0x04; /* USB or vendor-defined request code, burst mode */ + dr->wValue = cpu_to_le16(Flag); /* 0: Register number auto-increment, 1: No auto increment */ + dr->wIndex = cpu_to_le16(RegisterNo); + dr->wLength = cpu_to_le16(DataSize); reg_queue->Next = NULL; reg_queue->pUsbReq = dr; reg_queue->urb = urb; - spin_lock_irq( ®->EP0VM_spin_lock ); + spin_lock_irq(®->EP0VM_spin_lock); if (reg->reg_first == NULL) reg->reg_first = reg_queue; else reg->reg_last->Next = reg_queue; reg->reg_last = reg_queue; - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); - // Start EP0VM + /* Start EP0VM */ Wb35Reg_EP0VM_start(pHwData); return true; @@ -73,8 +74,7 @@ Wb35Reg_BurstWrite(struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterData return false; } -void -Wb35Reg_Update(struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue) +void Wb35Reg_Update(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) { struct wb35_reg *reg = &pHwData->reg; switch (RegisterNo) { @@ -116,97 +116,96 @@ Wb35Reg_Update(struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue) } } -// true : read command process successfully -// false : register not support -unsigned char -Wb35Reg_WriteSync( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue ) +/* + * true : read command process successfully + * false : register not support + */ +unsigned char Wb35Reg_WriteSync(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) { struct wb35_reg *reg = &pHwData->reg; int ret = -1; - // Module shutdown + /* Module shutdown */ if (pHwData->SurpriseRemove) return false; RegisterValue = cpu_to_le32(RegisterValue); - // update the register by send usb message------------------------------------ + /* update the register by send usb message */ reg->SyncIoPause = 1; - // 20060717.5 Wait until EP0VM stop + /* Wait until EP0VM stop */ while (reg->EP0vm_state != VM_STOP) msleep(10); - // Sync IoCallDriver + /* Sync IoCallDriver */ reg->EP0vm_state = VM_RUNNING; - ret = usb_control_msg( pHwData->WbUsb.udev, - usb_sndctrlpipe( pHwData->WbUsb.udev, 0 ), + ret = usb_control_msg(pHwData->WbUsb.udev, + usb_sndctrlpipe(pHwData->WbUsb.udev, 0), 0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, - 0x0,RegisterNo, &RegisterValue, 4, HZ*100 ); + 0x0, RegisterNo, &RegisterValue, 4, HZ * 100); reg->EP0vm_state = VM_STOP; reg->SyncIoPause = 0; Wb35Reg_EP0VM_start(pHwData); if (ret < 0) { - #ifdef _PE_REG_DUMP_ +#ifdef _PE_REG_DUMP_ printk("EP0 Write register usb message sending error\n"); - #endif - - pHwData->SurpriseRemove = 1; // 20060704.2 +#endif + pHwData->SurpriseRemove = 1; return false; } - return true; } -// true : read command process successfully -// false : register not support -unsigned char -Wb35Reg_Write( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue ) +/* + * true : read command process successfully + * false : register not support + */ +unsigned char Wb35Reg_Write(struct hw_data *pHwData, u16 RegisterNo, u32 RegisterValue) { - struct wb35_reg *reg = &pHwData->reg; - struct usb_ctrlrequest *dr; - struct urb *urb = NULL; - struct wb35_reg_queue *reg_queue = NULL; - u16 UrbSize; - + struct wb35_reg *reg = &pHwData->reg; + struct usb_ctrlrequest *dr; + struct urb *urb = NULL; + struct wb35_reg_queue *reg_queue = NULL; + u16 UrbSize; - // Module shutdown + /* Module shutdown */ if (pHwData->SurpriseRemove) return false; - // update the register by send urb request------------------------------------ + /* update the register by send urb request */ UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); urb = usb_alloc_urb(0, GFP_ATOMIC); if (urb && reg_queue) { - reg_queue->DIRECT = 1;// burst write register + reg_queue->DIRECT = 1; /* burst write register */ reg_queue->INDEX = RegisterNo; reg_queue->VALUE = cpu_to_le32(RegisterValue); reg_queue->RESERVED_VALID = false; dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE; - dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode + dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; + dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ dr->wValue = cpu_to_le16(0x0); dr->wIndex = cpu_to_le16(RegisterNo); dr->wLength = cpu_to_le16(4); - // Enter the sending queue + /* Enter the sending queue */ reg_queue->Next = NULL; reg_queue->pUsbReq = dr; reg_queue->urb = urb; - spin_lock_irq(®->EP0VM_spin_lock ); + spin_lock_irq(®->EP0VM_spin_lock); if (reg->reg_first == NULL) reg->reg_first = reg_queue; else reg->reg_last->Next = reg_queue; reg->reg_last = reg_queue; - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); - // Start EP0VM + /* Start EP0VM */ Wb35Reg_EP0VM_start(pHwData); return true; @@ -218,56 +217,60 @@ Wb35Reg_Write( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue ) } } -//This command will be executed with a user defined value. When it completes, -//this value is useful. For example, hal_set_current_channel will use it. -// true : read command process successfully -// false : register not support -unsigned char -Wb35Reg_WriteWithCallbackValue( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue, - s8 *pValue, s8 Len) +/* + * This command will be executed with a user defined value. When it completes, + * this value is useful. For example, hal_set_current_channel will use it. + * true : read command process successfully + * false : register not support + */ +unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *pHwData, + u16 RegisterNo, + u32 RegisterValue, + s8 *pValue, + s8 Len) { - struct wb35_reg *reg = &pHwData->reg; - struct usb_ctrlrequest *dr; - struct urb *urb = NULL; - struct wb35_reg_queue *reg_queue = NULL; - u16 UrbSize; + struct wb35_reg *reg = &pHwData->reg; + struct usb_ctrlrequest *dr; + struct urb *urb = NULL; + struct wb35_reg_queue *reg_queue = NULL; + u16 UrbSize; - // Module shutdown + /* Module shutdown */ if (pHwData->SurpriseRemove) return false; - // update the register by send urb request------------------------------------ + /* update the register by send urb request */ UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); urb = usb_alloc_urb(0, GFP_ATOMIC); if (urb && reg_queue) { - reg_queue->DIRECT = 1;// burst write register + reg_queue->DIRECT = 1; /* burst write register */ reg_queue->INDEX = RegisterNo; reg_queue->VALUE = cpu_to_le32(RegisterValue); - //NOTE : Users must guarantee the size of value will not exceed the buffer size. + /* NOTE : Users must guarantee the size of value will not exceed the buffer size. */ memcpy(reg_queue->RESERVED, pValue, Len); reg_queue->RESERVED_VALID = true; dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE; - dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode + dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; + dr->bRequest = 0x03; /* USB or vendor-defined request code, burst mode */ dr->wValue = cpu_to_le16(0x0); dr->wIndex = cpu_to_le16(RegisterNo); dr->wLength = cpu_to_le16(4); - // Enter the sending queue + /* Enter the sending queue */ reg_queue->Next = NULL; reg_queue->pUsbReq = dr; reg_queue->urb = urb; - spin_lock_irq (®->EP0VM_spin_lock ); - if( reg->reg_first == NULL ) + spin_lock_irq(®->EP0VM_spin_lock); + if (reg->reg_first == NULL) reg->reg_first = reg_queue; else reg->reg_last->Next = reg_queue; reg->reg_last = reg_queue; - spin_unlock_irq ( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); - // Start EP0VM + /* Start EP0VM */ Wb35Reg_EP0VM_start(pHwData); return true; } else { @@ -278,115 +281,114 @@ Wb35Reg_WriteWithCallbackValue( struct hw_data * pHwData, u16 RegisterNo, u32 Re } } -// true : read command process successfully -// false : register not support -// pRegisterValue : It must be a resident buffer due to asynchronous read register. -unsigned char -Wb35Reg_ReadSync( struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterValue ) +/* + * true : read command process successfully + * false : register not support + * pRegisterValue : It must be a resident buffer due to + * asynchronous read register. + */ +unsigned char Wb35Reg_ReadSync(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegisterValue) { struct wb35_reg *reg = &pHwData->reg; - u32 * pltmp = pRegisterValue; - int ret = -1; + u32 *pltmp = pRegisterValue; + int ret = -1; - // Module shutdown + /* Module shutdown */ if (pHwData->SurpriseRemove) return false; - // Read the register by send usb message------------------------------------ - + /* Read the register by send usb message */ reg->SyncIoPause = 1; - // 20060717.5 Wait until EP0VM stop + /* Wait until EP0VM stop */ while (reg->EP0vm_state != VM_STOP) msleep(10); reg->EP0vm_state = VM_RUNNING; - ret = usb_control_msg( pHwData->WbUsb.udev, + ret = usb_control_msg(pHwData->WbUsb.udev, usb_rcvctrlpipe(pHwData->WbUsb.udev, 0), - 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN, - 0x0, RegisterNo, pltmp, 4, HZ*100 ); + 0x01, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN, + 0x0, RegisterNo, pltmp, 4, HZ * 100); *pRegisterValue = cpu_to_le32(*pltmp); reg->EP0vm_state = VM_STOP; - Wb35Reg_Update( pHwData, RegisterNo, *pRegisterValue ); + Wb35Reg_Update(pHwData, RegisterNo, *pRegisterValue); reg->SyncIoPause = 0; - Wb35Reg_EP0VM_start( pHwData ); + Wb35Reg_EP0VM_start(pHwData); if (ret < 0) { - #ifdef _PE_REG_DUMP_ +#ifdef _PE_REG_DUMP_ printk("EP0 Read register usb message sending error\n"); - #endif - - pHwData->SurpriseRemove = 1; // 20060704.2 +#endif + pHwData->SurpriseRemove = 1; return false; } - return true; } -// true : read command process successfully -// false : register not support -// pRegisterValue : It must be a resident buffer due to asynchronous read register. -unsigned char -Wb35Reg_Read(struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterValue ) +/* + * true : read command process successfully + * false : register not support + * pRegisterValue : It must be a resident buffer due to + * asynchronous read register. + */ +unsigned char Wb35Reg_Read(struct hw_data *pHwData, u16 RegisterNo, u32 *pRegisterValue) { - struct wb35_reg *reg = &pHwData->reg; - struct usb_ctrlrequest * dr; - struct urb *urb; - struct wb35_reg_queue *reg_queue; - u16 UrbSize; + struct wb35_reg *reg = &pHwData->reg; + struct usb_ctrlrequest *dr; + struct urb *urb; + struct wb35_reg_queue *reg_queue; + u16 UrbSize; - // Module shutdown + /* Module shutdown */ if (pHwData->SurpriseRemove) return false; - // update the variable by send Urb to read register ------------------------------------ + /* update the variable by send Urb to read register */ UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); reg_queue = kzalloc(UrbSize, GFP_ATOMIC); urb = usb_alloc_urb(0, GFP_ATOMIC); - if( urb && reg_queue ) - { - reg_queue->DIRECT = 0;// read register + if (urb && reg_queue) { + reg_queue->DIRECT = 0; /* read register */ reg_queue->INDEX = RegisterNo; reg_queue->pBuffer = pRegisterValue; dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); - dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN; - dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode + dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN; + dr->bRequest = 0x01; /* USB or vendor-defined request code, burst mode */ dr->wValue = cpu_to_le16(0x0); - dr->wIndex = cpu_to_le16 (RegisterNo); - dr->wLength = cpu_to_le16 (4); + dr->wIndex = cpu_to_le16(RegisterNo); + dr->wLength = cpu_to_le16(4); - // Enter the sending queue + /* Enter the sending queue */ reg_queue->Next = NULL; reg_queue->pUsbReq = dr; reg_queue->urb = urb; - spin_lock_irq ( ®->EP0VM_spin_lock ); - if( reg->reg_first == NULL ) + spin_lock_irq(®->EP0VM_spin_lock); + if (reg->reg_first == NULL) reg->reg_first = reg_queue; else reg->reg_last->Next = reg_queue; reg->reg_last = reg_queue; - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); - // Start EP0VM - Wb35Reg_EP0VM_start( pHwData ); + /* Start EP0VM */ + Wb35Reg_EP0VM_start(pHwData); return true; } else { if (urb) - usb_free_urb( urb ); + usb_free_urb(urb); kfree(reg_queue); return false; } } -void -Wb35Reg_EP0VM_start( struct hw_data * pHwData ) +void Wb35Reg_EP0VM_start(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; @@ -397,15 +399,14 @@ Wb35Reg_EP0VM_start( struct hw_data * pHwData ) atomic_dec(®->RegFireCount); } -void -Wb35Reg_EP0VM(struct hw_data * pHwData ) +void Wb35Reg_EP0VM(struct hw_data *pHwData) { - struct wb35_reg *reg = &pHwData->reg; - struct urb *urb; - struct usb_ctrlrequest *dr; - u32 * pBuffer; + struct wb35_reg *reg = &pHwData->reg; + struct urb *urb; + struct usb_ctrlrequest *dr; + u32 *pBuffer; int ret = -1; - struct wb35_reg_queue *reg_queue; + struct wb35_reg_queue *reg_queue; if (reg->SyncIoPause) @@ -414,27 +415,27 @@ Wb35Reg_EP0VM(struct hw_data * pHwData ) if (pHwData->SurpriseRemove) goto cleanup; - // Get the register data and send to USB through Irp - spin_lock_irq( ®->EP0VM_spin_lock ); + /* Get the register data and send to USB through Irp */ + spin_lock_irq(®->EP0VM_spin_lock); reg_queue = reg->reg_first; - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); if (!reg_queue) goto cleanup; - // Get an Urb, send it + /* Get an Urb, send it */ urb = (struct urb *)reg_queue->urb; dr = reg_queue->pUsbReq; urb = reg_queue->urb; pBuffer = reg_queue->pBuffer; - if (reg_queue->DIRECT == 1) // output + if (reg_queue->DIRECT == 1) /* output */ pBuffer = ®_queue->VALUE; - usb_fill_control_urb( urb, pHwData->WbUsb.udev, - REG_DIRECTION(pHwData->WbUsb.udev,reg_queue), - (u8 *)dr,pBuffer,cpu_to_le16(dr->wLength), - Wb35Reg_EP0VM_complete, (void*)pHwData); + usb_fill_control_urb(urb, pHwData->WbUsb.udev, + REG_DIRECTION(pHwData->WbUsb.udev, reg_queue), + (u8 *)dr, pBuffer, cpu_to_le16(dr->wLength), + Wb35Reg_EP0VM_complete, (void *)pHwData); reg->EP0vm_state = VM_RUNNING; @@ -446,7 +447,6 @@ Wb35Reg_EP0VM(struct hw_data * pHwData ) #endif goto cleanup; } - return; cleanup: @@ -455,29 +455,28 @@ Wb35Reg_EP0VM(struct hw_data * pHwData ) } -void -Wb35Reg_EP0VM_complete(struct urb *urb) +void Wb35Reg_EP0VM_complete(struct urb *urb) { - struct hw_data * pHwData = (struct hw_data *)urb->context; - struct wb35_reg *reg = &pHwData->reg; - struct wb35_reg_queue *reg_queue; + struct hw_data *pHwData = (struct hw_data *)urb->context; + struct wb35_reg *reg = &pHwData->reg; + struct wb35_reg_queue *reg_queue; - // Variable setting + /* Variable setting */ reg->EP0vm_state = VM_COMPLETED; reg->EP0VM_status = urb->status; - if (pHwData->SurpriseRemove) { // Let WbWlanHalt to handle surprise remove + if (pHwData->SurpriseRemove) { /* Let WbWlanHalt to handle surprise remove */ reg->EP0vm_state = VM_STOP; atomic_dec(®->RegFireCount); } else { - // Complete to send, remove the URB from the first - spin_lock_irq( ®->EP0VM_spin_lock ); + /* Complete to send, remove the URB from the first */ + spin_lock_irq(®->EP0VM_spin_lock); reg_queue = reg->reg_first; if (reg_queue == reg->reg_last) reg->reg_last = NULL; reg->reg_first = reg->reg_first->Next; - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); if (reg->EP0VM_status) { #ifdef _PE_REG_DUMP_ @@ -486,37 +485,35 @@ Wb35Reg_EP0VM_complete(struct urb *urb) reg->EP0vm_state = VM_STOP; pHwData->SurpriseRemove = 1; } else { - // Success. Update the result + /* Success. Update the result */ - // Start the next send + /* Start the next send */ Wb35Reg_EP0VM(pHwData); } - kfree(reg_queue); + kfree(reg_queue); } usb_free_urb(urb); } -void -Wb35Reg_destroy(struct hw_data * pHwData) +void Wb35Reg_destroy(struct hw_data *pHwData) { - struct wb35_reg *reg = &pHwData->reg; - struct urb *urb; - struct wb35_reg_queue *reg_queue; - + struct wb35_reg *reg = &pHwData->reg; + struct urb *urb; + struct wb35_reg_queue *reg_queue; Uxx_power_off_procedure(pHwData); - // Wait for Reg operation completed + /* Wait for Reg operation completed */ do { - msleep(10); // Delay for waiting function enter 940623.1.a + msleep(10); /* Delay for waiting function enter */ } while (reg->EP0vm_state != VM_STOP); - msleep(10); // Delay for waiting function enter 940623.1.b + msleep(10); /* Delay for waiting function enter */ - // Release all the data in RegQueue - spin_lock_irq( ®->EP0VM_spin_lock ); + /* Release all the data in RegQueue */ + spin_lock_irq(®->EP0VM_spin_lock); reg_queue = reg->reg_first; while (reg_queue) { if (reg_queue == reg->reg_last) @@ -524,84 +521,88 @@ Wb35Reg_destroy(struct hw_data * pHwData) reg->reg_first = reg->reg_first->Next; urb = reg_queue->urb; - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); if (urb) { usb_free_urb(urb); kfree(reg_queue); } else { - #ifdef _PE_REG_DUMP_ +#ifdef _PE_REG_DUMP_ printk("EP0 queue release error\n"); - #endif +#endif } - spin_lock_irq( ®->EP0VM_spin_lock ); + spin_lock_irq(®->EP0VM_spin_lock); reg_queue = reg->reg_first; } - spin_unlock_irq( ®->EP0VM_spin_lock ); + spin_unlock_irq(®->EP0VM_spin_lock); } -//==================================================================================== -// The function can be run in passive-level only. -//==================================================================================== -unsigned char Wb35Reg_initial(struct hw_data * pHwData) +/* + * ======================================================================= + * The function can be run in passive-level only. + * ========================================================================= + */ +unsigned char Wb35Reg_initial(struct hw_data *pHwData) { - struct wb35_reg *reg=&pHwData->reg; + struct wb35_reg *reg = &pHwData->reg; u32 ltmp; u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval; - // Spin lock is acquired for read and write IRP command - spin_lock_init( ®->EP0VM_spin_lock ); - - // Getting RF module type from EEPROM ------------------------------------ - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d) - Wb35Reg_ReadSync( pHwData, 0x03b4, <mp ); - - //Update RF module type and determine the PHY type by inf or EEPROM - reg->EEPROMPhyType = (u8)( ltmp & 0xff ); - // 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829 - // 16V AL2230, 17 - AL7230, 18 - AL2230S - // 32 Reserved - // 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34) + /* Spin lock is acquired for read and write IRP command */ + spin_lock_init(®->EP0VM_spin_lock); + + /* Getting RF module type from EEPROM */ + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x080d0000); /* Start EEPROM access + Read + address(0x0d) */ + Wb35Reg_ReadSync(pHwData, 0x03b4, <mp); + + /* Update RF module type and determine the PHY type by inf or EEPROM */ + reg->EEPROMPhyType = (u8)(ltmp & 0xff); + /* + * 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829 + * 16V AL2230, 17 - AL7230, 18 - AL2230S + * 32 Reserved + * 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34) + */ if (reg->EEPROMPhyType != RF_DECIDE_BY_INF) { - if( (reg->EEPROMPhyType == RF_MAXIM_2825) || + if ((reg->EEPROMPhyType == RF_MAXIM_2825) || (reg->EEPROMPhyType == RF_MAXIM_2827) || (reg->EEPROMPhyType == RF_MAXIM_2828) || (reg->EEPROMPhyType == RF_MAXIM_2829) || (reg->EEPROMPhyType == RF_MAXIM_V1) || (reg->EEPROMPhyType == RF_AIROHA_2230) || - (reg->EEPROMPhyType == RF_AIROHA_2230S) || + (reg->EEPROMPhyType == RF_AIROHA_2230S) || (reg->EEPROMPhyType == RF_AIROHA_7230) || - (reg->EEPROMPhyType == RF_WB_242) || + (reg->EEPROMPhyType == RF_WB_242) || (reg->EEPROMPhyType == RF_WB_242_1)) pHwData->phy_type = reg->EEPROMPhyType; } - // Power On procedure running. The relative parameter will be set according to phy_type - Uxx_power_on_procedure( pHwData ); + /* Power On procedure running. The relative parameter will be set according to phy_type */ + Uxx_power_on_procedure(pHwData); - // Reading MAC address - Uxx_ReadEthernetAddress( pHwData ); + /* Reading MAC address */ + Uxx_ReadEthernetAddress(pHwData); - // Read VCO trim for RF parameter - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08200000 ); - Wb35Reg_ReadSync( pHwData, 0x03b4, &VCO_trim ); + /* Read VCO trim for RF parameter */ + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08200000); + Wb35Reg_ReadSync(pHwData, 0x03b4, &VCO_trim); - // Read Antenna On/Off of software flag - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08210000 ); - Wb35Reg_ReadSync( pHwData, 0x03b4, &SoftwareSet ); + /* Read Antenna On/Off of software flag */ + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08210000); + Wb35Reg_ReadSync(pHwData, 0x03b4, &SoftwareSet); - // Read TXVGA - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 ); - Wb35Reg_ReadSync( pHwData, 0x03b4, &TxVga ); + /* Read TXVGA */ + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000); + Wb35Reg_ReadSync(pHwData, 0x03b4, &TxVga); - // Get Scan interval setting from EEPROM offset 0x1c - Wb35Reg_WriteSync( pHwData, 0x03b4, 0x081d0000 ); - Wb35Reg_ReadSync( pHwData, 0x03b4, &Region_ScanInterval ); + /* Get Scan interval setting from EEPROM offset 0x1c */ + Wb35Reg_WriteSync(pHwData, 0x03b4, 0x081d0000); + Wb35Reg_ReadSync(pHwData, 0x03b4, &Region_ScanInterval); - // Update Ethernet address - memcpy( pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_ALEN ); + /* Update Ethernet address */ + memcpy(pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_ALEN); - // Update software variable + /* Update software variable */ pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff); TxVga &= 0x000000ff; pHwData->PowerIndexFromEEPROM = (u8)TxVga; @@ -609,22 +610,22 @@ unsigned char Wb35Reg_initial(struct hw_data * pHwData) if (pHwData->VCO_trim == 0xff) pHwData->VCO_trim = 0x28; - reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720 - if( reg->EEPROMRegion<1 || reg->EEPROMRegion>6 ) + reg->EEPROMRegion = (u8)(Region_ScanInterval >> 8); + if (reg->EEPROMRegion < 1 || reg->EEPROMRegion > 6) reg->EEPROMRegion = REGION_AUTO; - //For Get Tx VGA from EEPROM 20060315.5 move here - GetTxVgaFromEEPROM( pHwData ); + /* For Get Tx VGA from EEPROM */ + GetTxVgaFromEEPROM(pHwData); - // Set Scan Interval + /* Set Scan Interval */ pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10; - if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) // Is default setting 0xff * 10 + if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) /* Is default setting 0xff * 10 */ pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME; - // Initial register + /* Initial register */ RFSynthesizer_initial(pHwData); - BBProcessor_initial(pHwData); // Async write, must wait until complete + BBProcessor_initial(pHwData); /* Async write, must wait until complete */ Wb35Reg_phy_calibration(pHwData); @@ -634,113 +635,104 @@ unsigned char Wb35Reg_initial(struct hw_data * pHwData) if (pHwData->SurpriseRemove) return false; else - return true; // Initial fail + return true; /* Initial fail */ } -//=================================================================================== -// CardComputeCrc -- -// -// Description: -// Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length. -// -// Arguments: -// Buffer - the input buffer -// Length - the length of Buffer -// -// Return Value: -// The 32-bit CRC value. -// -// Note: -// This is adapted from the comments in the assembly language -// version in _GENREQ.ASM of the DWB NE1000/2000 driver. -//================================================================================== -u32 -CardComputeCrc(u8 * Buffer, u32 Length) +/* + * ================================================================ + * CardComputeCrc -- + * + * Description: + * Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length. + * + * Arguments: + * Buffer - the input buffer + * Length - the length of Buffer + * + * Return Value: + * The 32-bit CRC value. + * =================================================================== + */ +u32 CardComputeCrc(u8 *Buffer, u32 Length) { - u32 Crc, Carry; - u32 i, j; - u8 CurByte; - - Crc = 0xffffffff; - - for (i = 0; i < Length; i++) { - - CurByte = Buffer[i]; - - for (j = 0; j < 8; j++) { - - Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01); - Crc <<= 1; - CurByte >>= 1; - - if (Carry) { - Crc =(Crc ^ 0x04c11db6) | Carry; - } - } - } - - return Crc; + u32 Crc, Carry; + u32 i, j; + u8 CurByte; + + Crc = 0xffffffff; + + for (i = 0; i < Length; i++) { + CurByte = Buffer[i]; + for (j = 0; j < 8; j++) { + Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01); + Crc <<= 1; + CurByte >>= 1; + if (Carry) + Crc = (Crc ^ 0x04c11db6) | Carry; + } + } + return Crc; } -//================================================================== -// BitReverse -- -// Reverse the bits in the input argument, dwData, which is -// regarded as a string of bits with the length, DataLength. -// -// Arguments: -// dwData : -// DataLength : -// -// Return: -// The converted value. -//================================================================== -u32 BitReverse( u32 dwData, u32 DataLength) +/* + * ================================================================== + * BitReverse -- + * Reverse the bits in the input argument, dwData, which is + * regarded as a string of bits with the length, DataLength. + * + * Arguments: + * dwData : + * DataLength : + * + * Return: + * The converted value. + * ================================================================== + */ +u32 BitReverse(u32 dwData, u32 DataLength) { - u32 HalfLength, i, j; - u32 BitA, BitB; + u32 HalfLength, i, j; + u32 BitA, BitB; - if ( DataLength <= 0) return 0; // No conversion is done. + if (DataLength <= 0) + return 0; /* No conversion is done. */ dwData = dwData & (0xffffffff >> (32 - DataLength)); HalfLength = DataLength / 2; - for ( i = 0, j = DataLength-1 ; i < HalfLength; i++, j--) - { - BitA = GetBit( dwData, i); - BitB = GetBit( dwData, j); + for (i = 0, j = DataLength - 1; i < HalfLength; i++, j--) { + BitA = GetBit(dwData, i); + BitB = GetBit(dwData, j); if (BitA && !BitB) { - dwData = ClearBit( dwData, i); - dwData = SetBit( dwData, j); + dwData = ClearBit(dwData, i); + dwData = SetBit(dwData, j); } else if (!BitA && BitB) { - dwData = SetBit( dwData, i); - dwData = ClearBit( dwData, j); - } else - { - // Do nothing since these two bits are of the save values. + dwData = SetBit(dwData, i); + dwData = ClearBit(dwData, j); + } else { + /* Do nothing since these two bits are of the save values. */ } } - return dwData; } -void Wb35Reg_phy_calibration( struct hw_data * pHwData ) +void Wb35Reg_phy_calibration(struct hw_data *pHwData) { - u32 BB3c, BB54; + u32 BB3c, BB54; if ((pHwData->phy_type == RF_WB_242) || (pHwData->phy_type == RF_WB_242_1)) { - phy_calibration_winbond ( pHwData, 2412 ); // Sync operation - Wb35Reg_ReadSync( pHwData, 0x103c, &BB3c ); - Wb35Reg_ReadSync( pHwData, 0x1054, &BB54 ); + phy_calibration_winbond(pHwData, 2412); /* Sync operation */ + Wb35Reg_ReadSync(pHwData, 0x103c, &BB3c); + Wb35Reg_ReadSync(pHwData, 0x1054, &BB54); pHwData->BB3c_cal = BB3c; pHwData->BB54_cal = BB54; RFSynthesizer_initial(pHwData); - BBProcessor_initial(pHwData); // Async operation + BBProcessor_initial(pHwData); /* Async operation */ - Wb35Reg_WriteSync( pHwData, 0x103c, BB3c ); - Wb35Reg_WriteSync( pHwData, 0x1054, BB54 ); + Wb35Reg_WriteSync(pHwData, 0x103c, BB3c); + Wb35Reg_WriteSync(pHwData, 0x1054, BB54); } } diff --git a/drivers/staging/winbond/wb35reg_f.h b/drivers/staging/winbond/wb35reg_f.h index d352bce5c17..bf23c108419 100644 --- a/drivers/staging/winbond/wb35reg_f.h +++ b/drivers/staging/winbond/wb35reg_f.h @@ -3,59 +3,63 @@ #include "wbhal_s.h" -//==================================== -// Interface function declare -//==================================== -unsigned char Wb35Reg_initial( struct hw_data * pHwData ); -void Uxx_power_on_procedure( struct hw_data * pHwData ); -void Uxx_power_off_procedure( struct hw_data * pHwData ); -void Uxx_ReadEthernetAddress( struct hw_data * pHwData ); -void Dxx_initial( struct hw_data * pHwData ); -void Mxx_initial( struct hw_data * pHwData ); -void RFSynthesizer_initial( struct hw_data * pHwData ); -//void RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, s8 Channel ); -void RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, struct chan_info Channel ); -void BBProcessor_initial( struct hw_data * pHwData ); -void BBProcessor_RateChanging( struct hw_data * pHwData, u8 rate ); // 20060613.1 -//void RF_RateChanging( struct hw_data * pHwData, u8 rate ); // 20060626.5.c Add -u8 RFSynthesizer_SetPowerIndex( struct hw_data * pHwData, u8 PowerIndex ); -u8 RFSynthesizer_SetMaxim2828_24Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetMaxim2828_50Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetMaxim2827_24Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetMaxim2827_50Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetMaxim2825Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetAiroha2230Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetAiroha7230Power( struct hw_data *, u8 index ); -u8 RFSynthesizer_SetWinbond242Power( struct hw_data *, u8 index ); -void GetTxVgaFromEEPROM( struct hw_data * pHwData ); -void EEPROMTxVgaAdjust( struct hw_data * pHwData ); // 20060619.5 Add - -#define RFWriteControlData( _A, _V ) Wb35Reg_Write( _A, 0x0864, _V ) - -void Wb35Reg_destroy( struct hw_data * pHwData ); - -unsigned char Wb35Reg_Read( struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterValue ); -unsigned char Wb35Reg_ReadSync( struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterValue ); -unsigned char Wb35Reg_Write( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue ); -unsigned char Wb35Reg_WriteSync( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue ); -unsigned char Wb35Reg_WriteWithCallbackValue( struct hw_data * pHwData, - u16 RegisterNo, - u32 RegisterValue, - s8 *pValue, - s8 Len); -unsigned char Wb35Reg_BurstWrite( struct hw_data * pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag ); - -void Wb35Reg_EP0VM( struct hw_data * pHwData ); -void Wb35Reg_EP0VM_start( struct hw_data * pHwData ); +/* + * ==================================== + * Interface function declare + * ==================================== + */ +unsigned char Wb35Reg_initial(struct hw_data *hw_data); +void Uxx_power_on_procedure(struct hw_data *hw_data); +void Uxx_power_off_procedure(struct hw_data *hw_data); +void Uxx_ReadEthernetAddress(struct hw_data *hw_data); +void Dxx_initial(struct hw_data *hw_data); +void Mxx_initial(struct hw_data *hw_data); +void RFSynthesizer_initial(struct hw_data *hw_data); +void RFSynthesizer_SwitchingChannel(struct hw_data *hw_data, struct chan_info channel); +void BBProcessor_initial(struct hw_data *hw_data); +void BBProcessor_RateChanging(struct hw_data *hw_data, u8 rate); +u8 RFSynthesizer_SetPowerIndex(struct hw_data *hw_data, u8 power_index); +u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *, u8 index); +u8 RFSynthesizer_SetWinbond242Power(struct hw_data *, u8 index); +void GetTxVgaFromEEPROM(struct hw_data *hw_data); +void EEPROMTxVgaAdjust(struct hw_data *hw_data); + +#define RFWriteControlData(_A, _V) Wb35Reg_Write(_A, 0x0864, _V) + +void Wb35Reg_destroy(struct hw_data *hw_data); + +unsigned char Wb35Reg_Read(struct hw_data *hw_data, u16 register_no, u32 *register_value); +unsigned char Wb35Reg_ReadSync(struct hw_data *hw_data, u16 register_no, u32 *register_value); +unsigned char Wb35Reg_Write(struct hw_data *hw_data, u16 register_no, u32 register_value); +unsigned char Wb35Reg_WriteSync(struct hw_data *hw_data, u16 register_no, u32 register_value); +unsigned char Wb35Reg_WriteWithCallbackValue(struct hw_data *hw_data, + u16 register_no, + u32 register_value, + s8 *value, + s8 len); +unsigned char Wb35Reg_BurstWrite(struct hw_data *hw_data, + u16 register_no, + u32 *register_data, + u8 number_of_data, + u8 flag); + +void Wb35Reg_EP0VM(struct hw_data *hw_data); +void Wb35Reg_EP0VM_start(struct hw_data *hw_data); void Wb35Reg_EP0VM_complete(struct urb *urb); -u32 BitReverse( u32 dwData, u32 DataLength); +u32 BitReverse(u32 data, u32 data_length); -void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value ); -u32 CardComputeCrc( u8 * Buffer, u32 Length ); +void CardGetMulticastBit(u8 address[MAC_ADDR_LENGTH], u8 *byte, u8 *value); +u32 CardComputeCrc(u8 *buffer, u32 length); -void Wb35Reg_phy_calibration( struct hw_data * pHwData ); -void Wb35Reg_Update( struct hw_data * pHwData, u16 RegisterNo, u32 RegisterValue ); -unsigned char adjust_TXVGA_for_iq_mag( struct hw_data * pHwData ); +void Wb35Reg_phy_calibration(struct hw_data *hw_data); +void Wb35Reg_Update(struct hw_data *hw_data, u16 register_no, u32 register_value); +unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *hw_data); #endif diff --git a/drivers/staging/winbond/wb35reg_s.h b/drivers/staging/winbond/wb35reg_s.h index 32ef4b8a2d2..4eff009444b 100644 --- a/drivers/staging/winbond/wb35reg_s.h +++ b/drivers/staging/winbond/wb35reg_s.h @@ -5,98 +5,100 @@ #include <linux/types.h> #include <asm/atomic.h> -//======================================================================================= -/* - HAL setting function - - ======================================== - |Uxx| |Dxx| |Mxx| |BB| |RF| - ======================================== - | | - Wb35Reg_Read Wb35Reg_Write - - ---------------------------------------- - WbUsb_CallUSBDASync supplied By WbUsb module -*/ -//======================================================================================= - -#define GetBit( dwData, i) ( dwData & (0x00000001 << i)) -#define SetBit( dwData, i) ( dwData | (0x00000001 << i)) -#define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i)) - -#define IGNORE_INCREMENT 0 -#define AUTO_INCREMENT 0 -#define NO_INCREMENT 1 -#define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0)) -#define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4) - -// 20060613.2 Add the follow definition +/* ========================================================================= + * + * HAL setting function + * + * ======================================== + * |Uxx| |Dxx| |Mxx| |BB| |RF| + * ======================================== + * | | + * Wb35Reg_Read Wb35Reg_Write + * + * ---------------------------------------- + * WbUsb_CallUSBDASync supplied By WbUsb module + * ========================================================================== + */ +#define GetBit(dwData, i) (dwData & (0x00000001 << i)) +#define SetBit(dwData, i) (dwData | (0x00000001 << i)) +#define ClearBit(dwData, i) (dwData & ~(0x00000001 << i)) + +#define IGNORE_INCREMENT 0 +#define AUTO_INCREMENT 0 +#define NO_INCREMENT 1 +#define REG_DIRECTION(_x, _y) ((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0)) +#define REG_BUF_SIZE(_x) ((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4) + #define BB48_DEFAULT_AL2230_11B 0x0033447c #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF #define BB48_DEFAULT_AL2230_11G 0x00332C1B #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF -#define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB -#define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB -//#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB -//#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB +#define BB48_DEFAULT_WB242_11B 0x00292315 /* backoff 2dB */ +#define BB4C_DEFAULT_WB242_11B 0x0800FEFF /* backoff 2dB */ #define BB48_DEFAULT_WB242_11G 0x00453B24 #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF -//==================================== -// Default setting for Mxx -//==================================== -#define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31. -#define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023. -#define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007. +/* + * ==================================== + * Default setting for Mxx + * ==================================== + */ +#define DEFAULT_CWMIN 31 /* (M2C) CWmin. Its value is in the range 0-31. */ +#define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */ +#define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */ #ifdef _USE_FALLBACK_RATE_ -#define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named +#define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */ #else -#define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named +#define DEFAULT_RATE_RETRY_LIMIT 7 /* (M38) as named */ #endif -#define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15. -#define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15. -#define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535. -#define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575. -#define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535. -#define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535. -#define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15. -#define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535. -#define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255. -#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. -#define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535. -#define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535. -#define DEFAULT_PROTOCOL_VERSION 0 //(M4C) -#define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active -#define DEFAULT_DTIM_ALERT_TIME 0 +#define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */ +#define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */ +#define DEFAULT_PIFST 25 /* (M3C) PIFS Time. Its value is in the range 0-65535. */ +#define DEFAULT_EIFST 354 /* (M3C) EIFS Time. Its value is in the range 0-1048575. */ +#define DEFAULT_DIFST 45 /* (M3C) DIFS Time. Its value is in the range 0-65535. */ +#define DEFAULT_SIFST 5 /* (M3C) SIFS Time. Its value is in the range 0-65535. */ +#define DEFAULT_OSIFST 10 /* (M3C) Original SIFS Time. Its value is in the range 0-15. */ +#define DEFAULT_ATIMWD 0 /* (M40) ATIM Window. Its value is in the range 0-65535. */ +#define DEFAULT_SLOT_TIME 20 /* (M40) ($) SlotTime. Its value is in the range 0-255. */ +#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 /* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */ +#define DEFAULT_BEACON_INTERVAL 500 /* (M48) Beacon Interval. Its value is in the range 0-65535. */ +#define DEFAULT_PROBE_DELAY_TIME 200 /* (M48) Probe Delay Time. Its value is in the range 0-65535. */ +#define DEFAULT_PROTOCOL_VERSION 0 /* (M4C) */ +#define DEFAULT_MAC_POWER_STATE 2 /* (M4C) 2: MAC at power active */ +#define DEFAULT_DTIM_ALERT_TIME 0 struct wb35_reg_queue { - struct urb *urb; + struct urb *urb; void *pUsbReq; void *Next; union { u32 VALUE; u32 *pBuffer; }; - u8 RESERVED[4]; // space reserved for communication - u16 INDEX; // For storing the register index - u8 RESERVED_VALID; // Indicate whether the RESERVED space is valid at this command. - u8 DIRECT; // 0:In 1:Out + u8 RESERVED[4]; /* space reserved for communication */ + u16 INDEX; /* For storing the register index */ + u8 RESERVED_VALID; /* Indicate whether the RESERVED space is valid at this command. */ + u8 DIRECT; /* 0:In 1:Out */ }; -//==================================== -// Internal variable for module -//==================================== +/* + * ==================================== + * Internal variable for module + * ==================================== + */ #define MAX_SQ3_FILTER_SIZE 5 struct wb35_reg { - //============================ - // Register Bank backup - //============================ - u32 U1B0; //bit16 record the h/w radio on/off status + /* + * ============================ + * Register Bank backup + * ============================ + */ + u32 U1B0; /* bit16 record the h/w radio on/off status */ u32 U1BC_LEDConfigure; u32 D00_DmaControl; u32 M00_MacControl; @@ -105,68 +107,65 @@ struct wb35_reg { u32 M04_MulticastAddress1; u32 M08_MulticastAddress2; }; - u8 Multicast[8]; // contents of card multicast registers + u8 Multicast[8]; /* contents of card multicast registers */ }; u32 M24_MacControl; u32 M28_MacControl; u32 M2C_MacControl; u32 M38_MacControl; - u32 M3C_MacControl; // 20060214 backup only + u32 M3C_MacControl; u32 M40_MacControl; - u32 M44_MacControl; // 20060214 backup only - u32 M48_MacControl; // 20060214 backup only + u32 M44_MacControl; + u32 M48_MacControl; u32 M4C_MacStatus; - u32 M60_MacControl; // 20060214 backup only - u32 M68_MacControl; // 20060214 backup only - u32 M70_MacControl; // 20060214 backup only - u32 M74_MacControl; // 20060214 backup only - u32 M78_ERPInformation;//930206.2.b - u32 M7C_MacControl; // 20060214 backup only - u32 M80_MacControl; // 20060214 backup only - u32 M84_MacControl; // 20060214 backup only - u32 M88_MacControl; // 20060214 backup only - u32 M98_MacControl; // 20060214 backup only - - //[20040722 WK] - //Baseband register - u32 BB0C; // Used for LNA calculation - u32 BB2C; // - u32 BB30; //11b acquisition control register + u32 M60_MacControl; + u32 M68_MacControl; + u32 M70_MacControl; + u32 M74_MacControl; + u32 M78_ERPInformation; + u32 M7C_MacControl; + u32 M80_MacControl; + u32 M84_MacControl; + u32 M88_MacControl; + u32 M98_MacControl; + + /* Baseband register */ + u32 BB0C; /* Used for LNA calculation */ + u32 BB2C; + u32 BB30; /* 11b acquisition control register */ u32 BB3C; - u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate - u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate - u32 BB50; //mode control register + u32 BB48; + u32 BB4C; + u32 BB50; /* mode control register */ u32 BB54; - u32 BB58; //IQ_ALPHA - u32 BB5C; // For test - u32 BB60; // for WTO read value - - //------------------- - // VM - //------------------- - spinlock_t EP0VM_spin_lock; // 4B - u32 EP0VM_status;//$$ + u32 BB58; /* IQ_ALPHA */ + u32 BB5C; /* For test */ + u32 BB60; /* for WTO read value */ + + /* VM */ + spinlock_t EP0VM_spin_lock; /* 4B */ + u32 EP0VM_status; /* $$ */ struct wb35_reg_queue *reg_first; struct wb35_reg_queue *reg_last; - atomic_t RegFireCount; + atomic_t RegFireCount; - // Hardware status + /* Hardware status */ u8 EP0vm_state; u8 mac_power_save; - u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829), - // 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230) - // 32 ~ Reserved - // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step) - // 48 ~ 255 ARE RESERVED. - u8 EEPROMRegion; //Region setting in EEPROM - - u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access - - u8 LNAValue[4]; //Table for speed up running + u8 EEPROMPhyType; /* + * 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829), + * 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230) + * 32 ~ Reserved + * 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step) + * 48 ~ 255 ARE RESERVED. + */ + u8 EEPROMRegion; /* Region setting in EEPROM */ + + u32 SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */ + + u8 LNAValue[4]; /* Table for speed up running */ u32 SQ3_filter[MAX_SQ3_FILTER_SIZE]; u32 SQ3_index; - }; - #endif diff --git a/drivers/staging/winbond/wb35rx.c b/drivers/staging/winbond/wb35rx.c index d7b57e62db0..efe82b141c1 100644 --- a/drivers/staging/winbond/wb35rx.c +++ b/drivers/staging/winbond/wb35rx.c @@ -1,13 +1,15 @@ -//============================================================================ -// Copyright (c) 1996-2002 Winbond Electronic Corporation -// -// Module Name: -// Wb35Rx.c -// -// Abstract: -// Processing the Rx message from down layer -// -//============================================================================ +/* + * ============================================================================ + * Copyright (c) 1996-2002 Winbond Electronic Corporation + * + * Module Name: + * Wb35Rx.c + * + * Abstract: + * Processing the Rx message from down layer + * + * ============================================================================ + */ #include <linux/usb.h> #include <linux/slab.h> @@ -30,16 +32,7 @@ static void packet_came(struct ieee80211_hw *hw, char *pRxBufferAddress, int Pac return; } - memcpy(skb_put(skb, PacketSize), - pRxBufferAddress, - PacketSize); - -/* - rx_status.rate = 10; - rx_status.channel = 1; - rx_status.freq = 12345; - rx_status.phymode = MODE_IEEE80211B; -*/ + memcpy(skb_put(skb, PacketSize), pRxBufferAddress, PacketSize); memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); ieee80211_rx_irqsafe(hw, skb); @@ -47,7 +40,7 @@ static void packet_came(struct ieee80211_hw *hw, char *pRxBufferAddress, int Pac static void Wb35Rx_adjust(struct wb35_descriptor *pRxDes) { - u32 * pRxBufferAddress; + u32 *pRxBufferAddress; u32 DecryptionMethod; u32 i; u16 BufferSize; @@ -56,81 +49,80 @@ static void Wb35Rx_adjust(struct wb35_descriptor *pRxDes) pRxBufferAddress = pRxDes->buffer_address[0]; BufferSize = pRxDes->buffer_size[0]; - // Adjust the last part of data. Only data left - BufferSize -= 4; // For CRC-32 + /* Adjust the last part of data. Only data left */ + BufferSize -= 4; /* For CRC-32 */ if (DecryptionMethod) BufferSize -= 4; - if (DecryptionMethod == 3) // For CCMP + if (DecryptionMethod == 3) /* For CCMP */ BufferSize -= 4; - // Adjust the IV field which after 802.11 header and ICV field. - if (DecryptionMethod == 1) // For WEP - { - for( i=6; i>0; i-- ) - pRxBufferAddress[i] = pRxBufferAddress[i-1]; + /* Adjust the IV field which after 802.11 header and ICV field. */ + if (DecryptionMethod == 1) { /* For WEP */ + for (i = 6; i > 0; i--) + pRxBufferAddress[i] = pRxBufferAddress[i - 1]; pRxDes->buffer_address[0] = pRxBufferAddress + 1; - BufferSize -= 4; // 4 byte for IV - } - else if( DecryptionMethod ) // For TKIP and CCMP - { - for (i=7; i>1; i--) - pRxBufferAddress[i] = pRxBufferAddress[i-2]; - pRxDes->buffer_address[0] = pRxBufferAddress + 2;//Update the descriptor, shift 8 byte - BufferSize -= 8; // 8 byte for IV + ICV + BufferSize -= 4; /* 4 byte for IV */ + } else if (DecryptionMethod) { /* For TKIP and CCMP */ + for (i = 7; i > 1; i--) + pRxBufferAddress[i] = pRxBufferAddress[i - 2]; + pRxDes->buffer_address[0] = pRxBufferAddress + 2; /* Update the descriptor, shift 8 byte */ + BufferSize -= 8; /* 8 byte for IV + ICV */ } pRxDes->buffer_size[0] = BufferSize; } static u16 Wb35Rx_indicate(struct ieee80211_hw *hw) { - struct wbsoft_priv *priv = hw->priv; - struct hw_data * pHwData = &priv->sHwData; + struct wbsoft_priv *priv = hw->priv; + struct hw_data *pHwData = &priv->sHwData; struct wb35_descriptor RxDes; - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - u8 * pRxBufferAddress; - u16 PacketSize; - u16 stmp, BufferSize, stmp2 = 0; - u32 RxBufferId; + struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; + u8 *pRxBufferAddress; + u16 PacketSize; + u16 stmp, BufferSize, stmp2 = 0; + u32 RxBufferId; - // Only one thread be allowed to run into the following + /* Only one thread be allowed to run into the following */ do { RxBufferId = pWb35Rx->RxProcessIndex; - if (pWb35Rx->RxOwner[ RxBufferId ]) //Owner by VM + if (pWb35Rx->RxOwner[RxBufferId]) /* Owner by VM */ break; pWb35Rx->RxProcessIndex++; pWb35Rx->RxProcessIndex %= MAX_USB_RX_BUFFER_NUMBER; pRxBufferAddress = pWb35Rx->pDRx; - BufferSize = pWb35Rx->RxBufferSize[ RxBufferId ]; + BufferSize = pWb35Rx->RxBufferSize[RxBufferId]; - // Parse the bulkin buffer + /* Parse the bulkin buffer */ while (BufferSize >= 4) { - if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a + if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) /* Is ending? */ break; - // Get the R00 R01 first + /* Get the R00 R01 first */ RxDes.R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress); PacketSize = (u16)RxDes.R00.R00_receive_byte_count; - RxDes.R01.value = le32_to_cpu(*((u32 *)(pRxBufferAddress+4))); - // For new DMA 4k + RxDes.R01.value = le32_to_cpu(*((u32 *)(pRxBufferAddress + 4))); + /* For new DMA 4k */ if ((PacketSize & 0x03) > 0) PacketSize -= 4; - // Basic check for Rx length. Is length valid? + /* Basic check for Rx length. Is length valid? */ if (PacketSize > MAX_PACKET_SIZE) { - #ifdef _PE_RX_DUMP_ +#ifdef _PE_RX_DUMP_ printk("Serious ERROR : Rx data size too long, size =%d\n", PacketSize); - #endif +#endif pWb35Rx->EP3vm_state = VM_STOP; pWb35Rx->Ep3ErrorCount2++; break; } - // Start to process Rx buffer -// RxDes.Descriptor_ID = RxBufferId; // Due to synchronous indicate, the field doesn't necessary to use. - BufferSize -= 8; //subtract 8 byte for 35's USB header length + /* + * Wb35Rx_indicate() is called synchronously so it isn't + * necessary to set "RxDes.Desctriptor_ID = RxBufferID;" + */ + BufferSize -= 8; /* subtract 8 byte for 35's USB header length */ pRxBufferAddress += 8; RxDes.buffer_address[0] = pRxBufferAddress; @@ -142,18 +134,17 @@ static u16 Wb35Rx_indicate(struct ieee80211_hw *hw) packet_came(hw, pRxBufferAddress, PacketSize); - // Move RxBuffer point to the next + /* Move RxBuffer point to the next */ stmp = PacketSize + 3; - stmp &= ~0x03; // 4n alignment + stmp &= ~0x03; /* 4n alignment */ pRxBufferAddress += stmp; BufferSize -= stmp; stmp2 += stmp; } - // Reclaim resource - pWb35Rx->RxOwner[ RxBufferId ] = 1; + /* Reclaim resource */ + pWb35Rx->RxOwner[RxBufferId] = 1; } while (true); - return stmp2; } @@ -161,112 +152,110 @@ static void Wb35Rx(struct ieee80211_hw *hw); static void Wb35Rx_Complete(struct urb *urb) { - struct ieee80211_hw *hw = urb->context; - struct wbsoft_priv *priv = hw->priv; - struct hw_data * pHwData = &priv->sHwData; - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - u8 * pRxBufferAddress; - u32 SizeCheck; - u16 BulkLength; - u32 RxBufferId; - R00_DESCRIPTOR R00; - - // Variable setting + struct ieee80211_hw *hw = urb->context; + struct wbsoft_priv *priv = hw->priv; + struct hw_data *pHwData = &priv->sHwData; + struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; + u8 *pRxBufferAddress; + u32 SizeCheck; + u16 BulkLength; + u32 RxBufferId; + R00_DESCRIPTOR R00; + + /* Variable setting */ pWb35Rx->EP3vm_state = VM_COMPLETED; - pWb35Rx->EP3VM_status = urb->status;//Store the last result of Irp + pWb35Rx->EP3VM_status = urb->status; /* Store the last result of Irp */ RxBufferId = pWb35Rx->CurrentRxBufferId; pRxBufferAddress = pWb35Rx->pDRx; BulkLength = (u16)urb->actual_length; - // The IRP is completed + /* The IRP is completed */ pWb35Rx->EP3vm_state = VM_COMPLETED; - if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid + if (pHwData->SurpriseRemove || pHwData->HwStop) /* Must be here, or RxBufferId is invalid */ goto error; if (pWb35Rx->rx_halt) goto error; - // Start to process the data only in successful condition - pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver + /* Start to process the data only in successful condition */ + pWb35Rx->RxOwner[RxBufferId] = 0; /* Set the owner to driver */ R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress); - // The URB is completed, check the result + /* The URB is completed, check the result */ if (pWb35Rx->EP3VM_status != 0) { - #ifdef _PE_USB_STATE_DUMP_ +#ifdef _PE_USB_STATE_DUMP_ printk("EP3 IoCompleteRoutine return error\n"); - #endif +#endif pWb35Rx->EP3vm_state = VM_STOP; goto error; } - // 20060220 For recovering. check if operating in single USB mode + /* For recovering. check if operating in single USB mode */ if (!HAL_USB_MODE_BURST(pHwData)) { - SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian + SizeCheck = R00.R00_receive_byte_count; if ((SizeCheck & 0x03) > 0) SizeCheck -= 4; SizeCheck = (SizeCheck + 3) & ~0x03; - SizeCheck += 12; // 8 + 4 badbeef + SizeCheck += 12; /* 8 + 4 badbeef */ if ((BulkLength > 1600) || (SizeCheck > 1600) || (BulkLength != SizeCheck) || - (BulkLength == 0)) { // Add for fail Urb + (BulkLength == 0)) { /* Add for fail Urb */ pWb35Rx->EP3vm_state = VM_STOP; pWb35Rx->Ep3ErrorCount2++; } } - // Indicating the receiving data + /* Indicating the receiving data */ pWb35Rx->ByteReceived += BulkLength; - pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength; + pWb35Rx->RxBufferSize[RxBufferId] = BulkLength; - if (!pWb35Rx->RxOwner[ RxBufferId ]) + if (!pWb35Rx->RxOwner[RxBufferId]) Wb35Rx_indicate(hw); kfree(pWb35Rx->pDRx); - // Do the next receive + /* Do the next receive */ Wb35Rx(hw); return; error: - pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware + pWb35Rx->RxOwner[RxBufferId] = 1; /* Set the owner to hardware */ atomic_dec(&pWb35Rx->RxFireCounter); pWb35Rx->EP3vm_state = VM_STOP; } -// This function cannot reentrain +/* This function cannot reentrain */ static void Wb35Rx(struct ieee80211_hw *hw) { - struct wbsoft_priv *priv = hw->priv; - struct hw_data * pHwData = &priv->sHwData; - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - u8 * pRxBufferAddress; - struct urb *urb = pWb35Rx->RxUrb; - int retv; - u32 RxBufferId; - - // - // Issuing URB - // + struct wbsoft_priv *priv = hw->priv; + struct hw_data *pHwData = &priv->sHwData; + struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; + u8 *pRxBufferAddress; + struct urb *urb = pWb35Rx->RxUrb; + int retv; + u32 RxBufferId; + + /* Issuing URB */ if (pHwData->SurpriseRemove || pHwData->HwStop) goto error; if (pWb35Rx->rx_halt) goto error; - // Get RxBuffer's ID + /* Get RxBuffer's ID */ RxBufferId = pWb35Rx->RxBufferId; if (!pWb35Rx->RxOwner[RxBufferId]) { - // It's impossible to run here. - #ifdef _PE_RX_DUMP_ + /* It's impossible to run here. */ +#ifdef _PE_RX_DUMP_ printk("Rx driver fifo unavailable\n"); - #endif +#endif goto error; } - // Update buffer point, then start to bulkin the data from USB + /* Update buffer point, then start to bulkin the data from USB */ pWb35Rx->RxBufferId++; pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER; @@ -295,18 +284,18 @@ static void Wb35Rx(struct ieee80211_hw *hw) return; error: - // VM stop + /* VM stop */ pWb35Rx->EP3vm_state = VM_STOP; atomic_dec(&pWb35Rx->RxFireCounter); } void Wb35Rx_start(struct ieee80211_hw *hw) { - struct wbsoft_priv *priv = hw->priv; - struct hw_data * pHwData = &priv->sHwData; - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; + struct wbsoft_priv *priv = hw->priv; + struct hw_data *pHwData = &priv->sHwData; + struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - // Allow only one thread to run into the Wb35Rx() function + /* Allow only one thread to run into the Wb35Rx() function */ if (atomic_inc_return(&pWb35Rx->RxFireCounter) == 1) { pWb35Rx->EP3vm_state = VM_RUNNING; Wb35Rx(hw); @@ -314,11 +303,10 @@ void Wb35Rx_start(struct ieee80211_hw *hw) atomic_dec(&pWb35Rx->RxFireCounter); } -//===================================================================================== -static void Wb35Rx_reset_descriptor( struct hw_data * pHwData ) +static void Wb35Rx_reset_descriptor(struct hw_data *pHwData) { - struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - u32 i; + struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; + u32 i; pWb35Rx->ByteReceived = 0; pWb35Rx->RxProcessIndex = 0; @@ -326,49 +314,49 @@ static void Wb35Rx_reset_descriptor( struct hw_data * pHwData ) pWb35Rx->EP3vm_state = VM_STOP; pWb35Rx->rx_halt = 0; - // Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable. - for( i=0; i<MAX_USB_RX_BUFFER_NUMBER; i++ ) + /* Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable. */ + for (i = 0; i < MAX_USB_RX_BUFFER_NUMBER; i++) pWb35Rx->RxOwner[i] = 1; } -unsigned char Wb35Rx_initial(struct hw_data * pHwData) +unsigned char Wb35Rx_initial(struct hw_data *pHwData) { struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - // Initial the Buffer Queue - Wb35Rx_reset_descriptor( pHwData ); + /* Initial the Buffer Queue */ + Wb35Rx_reset_descriptor(pHwData); pWb35Rx->RxUrb = usb_alloc_urb(0, GFP_ATOMIC); - return (!!pWb35Rx->RxUrb); + return !!pWb35Rx->RxUrb; } -void Wb35Rx_stop(struct hw_data * pHwData) +void Wb35Rx_stop(struct hw_data *pHwData) { struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; - // Canceling the Irp if already sends it out. + /* Canceling the Irp if already sends it out. */ if (pWb35Rx->EP3vm_state == VM_RUNNING) { - usb_unlink_urb( pWb35Rx->RxUrb ); // Only use unlink, let Wb35Rx_destroy to free them - #ifdef _PE_RX_DUMP_ + usb_unlink_urb(pWb35Rx->RxUrb); /* Only use unlink, let Wb35Rx_destroy to free them */ +#ifdef _PE_RX_DUMP_ printk("EP3 Rx stop\n"); - #endif +#endif } } -// Needs process context -void Wb35Rx_destroy(struct hw_data * pHwData) +/* Needs process context */ +void Wb35Rx_destroy(struct hw_data *pHwData) { struct wb35_rx *pWb35Rx = &pHwData->Wb35Rx; do { - msleep(10); // Delay for waiting function enter 940623.1.a + msleep(10); /* Delay for waiting function enter */ } while (pWb35Rx->EP3vm_state != VM_STOP); - msleep(10); // Delay for waiting function exit 940623.1.b + msleep(10); /* Delay for waiting function exit */ if (pWb35Rx->RxUrb) - usb_free_urb( pWb35Rx->RxUrb ); - #ifdef _PE_RX_DUMP_ + usb_free_urb(pWb35Rx->RxUrb); +#ifdef _PE_RX_DUMP_ printk("Wb35Rx_destroy OK\n"); - #endif +#endif } diff --git a/drivers/staging/winbond/wb35tx_f.h b/drivers/staging/winbond/wb35tx_f.h index a7af9cbe202..1d3b515f83b 100644 --- a/drivers/staging/winbond/wb35tx_f.h +++ b/drivers/staging/winbond/wb35tx_f.h @@ -4,18 +4,20 @@ #include "core.h" #include "wbhal_f.h" -//==================================== -// Interface function declare -//==================================== -unsigned char Wb35Tx_initial( struct hw_data * pHwData ); -void Wb35Tx_destroy( struct hw_data * pHwData ); -unsigned char Wb35Tx_get_tx_buffer( struct hw_data * pHwData, u8 **pBuffer ); +/* + * ==================================== + * Interface function declare + * ==================================== + */ +unsigned char Wb35Tx_initial(struct hw_data *hw_data); +void Wb35Tx_destroy(struct hw_data *hw_data); +unsigned char Wb35Tx_get_tx_buffer(struct hw_data *hw_data, u8 **buffer); void Wb35Tx_EP2VM_start(struct wbsoft_priv *adapter); void Wb35Tx_start(struct wbsoft_priv *adapter); -void Wb35Tx_stop( struct hw_data * pHwData ); +void Wb35Tx_stop(struct hw_data *hw_data); -void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 TimeCount); +void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 time_count); #endif diff --git a/drivers/staging/winbond/wbhal_f.h b/drivers/staging/winbond/wbhal_f.h index 64a008db30f..401c024bead 100644 --- a/drivers/staging/winbond/wbhal_f.h +++ b/drivers/staging/winbond/wbhal_f.h @@ -1,70 +1,91 @@ -//===================================================================== -// Device related include -//===================================================================== +/* + * ===================================================================== + * Device related include + * ===================================================================== +*/ #include "wb35reg_f.h" #include "wb35tx_f.h" #include "wb35rx_f.h" #include "core.h" -//==================================================================================== -// Function declaration -//==================================================================================== -void hal_remove_mapping_key( struct hw_data * pHwData, u8 *pmac_addr ); -void hal_remove_default_key( struct hw_data * pHwData, u32 index ); -unsigned char hal_set_mapping_key( struct hw_data * adapter, u8 *pmac_addr, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data ); -unsigned char hal_set_default_key( struct hw_data * adapter, u8 index, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data ); -void hal_clear_all_default_key( struct hw_data * pHwData ); -void hal_clear_all_group_key( struct hw_data * pHwData ); -void hal_clear_all_mapping_key( struct hw_data * pHwData ); -void hal_clear_all_key( struct hw_data * pHwData ); -void hal_set_power_save_mode( struct hw_data * pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim ); -void hal_get_power_save_mode( struct hw_data * pHwData, u8 *pin_pwr_save ); -void hal_set_slot_time( struct hw_data * pHwData, u8 type ); -#define hal_set_atim_window( _A, _ATM ) -void hal_start_bss( struct hw_data * pHwData, u8 mac_op_mode ); -void hal_join_request( struct hw_data * pHwData, u8 bss_type ); // 0:BSS STA 1:IBSS STA// -void hal_stop_sync_bss( struct hw_data * pHwData ); -void hal_resume_sync_bss( struct hw_data * pHwData); -void hal_set_aid( struct hw_data * pHwData, u16 aid ); -void hal_set_bssid( struct hw_data * pHwData, u8 *pbssid ); -void hal_get_bssid( struct hw_data * pHwData, u8 *pbssid ); -void hal_set_listen_interval( struct hw_data * pHwData, u16 listen_interval ); -void hal_set_cap_info( struct hw_data * pHwData, u16 capability_info ); -void hal_set_ssid( struct hw_data * pHwData, u8 *pssid, u8 ssid_len ); -void hal_start_tx0( struct hw_data * pHwData ); -#define hal_get_cwmin( _A ) ( (_A)->cwmin ) -void hal_set_cwmax( struct hw_data * pHwData, u16 cwin_max ); -#define hal_get_cwmax( _A ) ( (_A)->cwmax ) -void hal_set_rsn_wpa( struct hw_data * pHwData, u32 * RSN_IE_Bitmap , u32 * RSN_OUI_type , unsigned char bDesiredAuthMode); -void hal_set_connect_info( struct hw_data * pHwData, unsigned char boConnect ); -u8 hal_get_est_sq3( struct hw_data * pHwData, u8 Count ); -void hal_descriptor_indicate( struct hw_data * pHwData, struct wb35_descriptor *pDes ); -u8 hal_get_antenna_number( struct hw_data * pHwData ); -u32 hal_get_bss_pk_cnt( struct hw_data * pHwData ); -#define hal_get_region_from_EEPROM( _A ) ( (_A)->reg.EEPROMRegion ) -#define hal_get_tx_buffer( _A, _B ) Wb35Tx_get_tx_buffer( _A, _B ) -#define hal_software_set( _A ) (_A->SoftwareSet) -#define hal_driver_init_OK( _A ) (_A->IsInitOK) -#define hal_rssi_boundary_high( _A ) (_A->RSSI_high) -#define hal_rssi_boundary_low( _A ) (_A->RSSI_low) -#define hal_scan_interval( _A ) (_A->Scan_Interval) - -#define PHY_DEBUG( msg, args... ) - -#define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count -#define hal_detect_error( _P ) (_P->WbUsb.DetectCount) - -//------------------------------------------------------------------------- -// The follow function is unused for IS89C35 -//------------------------------------------------------------------------- +/* ===================================================================== + * Function declaration + * ===================================================================== + */ +void hal_remove_mapping_key(struct hw_data *hw_data, u8 *mac_addr); +void hal_remove_default_key(struct hw_data *hw_data, u32 index); +unsigned char hal_set_mapping_key(struct hw_data *adapter, u8 *mac_addr, + u8 null_key, u8 wep_on, u8 *tx_tsc, + u8 *rx_tsc, u8 key_type, u8 key_len, + u8 *key_data); +unsigned char hal_set_default_key(struct hw_data *adapter, u8 index, + u8 null_key, u8 wep_on, u8 *tx_tsc, + u8 *rx_tsc, u8 key_type, u8 key_len, + u8 *key_data); +void hal_clear_all_default_key(struct hw_data *hw_data); +void hal_clear_all_group_key(struct hw_data *hw_data); +void hal_clear_all_mapping_key(struct hw_data *hw_data); +void hal_clear_all_key(struct hw_data *hw_data); +void hal_set_power_save_mode(struct hw_data *hw_data, unsigned char power_save, + unsigned char wakeup, unsigned char dtim); +void hal_get_power_save_mode(struct hw_data *hw_data, u8 *in_pwr_save); +void hal_set_slot_time(struct hw_data *hw_data, u8 type); + +#define hal_set_atim_window(_A, _ATM) + +void hal_start_bss(struct hw_data *hw_data, u8 mac_op_mode); + +/* 0:BSS STA 1:IBSS STA */ +void hal_join_request(struct hw_data *hw_data, u8 bss_type); + +void hal_stop_sync_bss(struct hw_data *hw_data); +void hal_resume_sync_bss(struct hw_data *hw_data); +void hal_set_aid(struct hw_data *hw_data, u16 aid); +void hal_set_bssid(struct hw_data *hw_data, u8 *bssid); +void hal_get_bssid(struct hw_data *hw_data, u8 *bssid); +void hal_set_listen_interval(struct hw_data *hw_data, u16 listen_interval); +void hal_set_cap_info(struct hw_data *hw_data, u16 capability_info); +void hal_set_ssid(struct hw_data *hw_data, u8 *ssid, u8 ssid_len); +void hal_start_tx0(struct hw_data *hw_data); + +#define hal_get_cwmin(_A) ((_A)->cwmin) + +void hal_set_cwmax(struct hw_data *hw_data, u16 cwin_max); + +#define hal_get_cwmax(_A) ((_A)->cwmax) + +void hal_set_rsn_wpa(struct hw_data *hw_data, u32 *rsn_ie_bitmap, + u32 *rsn_oui_type , unsigned char desired_auth_mode); +void hal_set_connect_info(struct hw_data *hw_data, unsigned char bo_connect); +u8 hal_get_est_sq3(struct hw_data *hw_data, u8 count); +void hal_descriptor_indicate(struct hw_data *hw_data, + struct wb35_descriptor *des); +u8 hal_get_antenna_number(struct hw_data *hw_data); +u32 hal_get_bss_pk_cnt(struct hw_data *hw_data); + +#define hal_get_region_from_EEPROM(_A) ((_A)->reg.EEPROMRegion) +#define hal_get_tx_buffer(_A, _B) Wb35Tx_get_tx_buffer(_A, _B) +#define hal_software_set(_A) (_A->SoftwareSet) +#define hal_driver_init_OK(_A) (_A->IsInitOK) +#define hal_rssi_boundary_high(_A) (_A->RSSI_high) +#define hal_rssi_boundary_low(_A) (_A->RSSI_low) +#define hal_scan_interval(_A) (_A->Scan_Interval) + +#define PHY_DEBUG(msg, args...) + +/* return 100ms count */ +#define hal_get_time_count(_P) (_P->time_count / 10) +#define hal_detect_error(_P) (_P->WbUsb.DetectCount) + +/* The follow function is unused for IS89C35 */ #define hal_disable_interrupt(_A) #define hal_enable_interrupt(_A) -#define hal_get_interrupt_type( _A) +#define hal_get_interrupt_type(_A) #define hal_get_clear_interrupt(_A) -#define hal_ibss_disconnect(_A) hal_stop_sync_bss(_A) +#define hal_ibss_disconnect(_A) (hal_stop_sync_bss(_A)) #define hal_join_request_stop(_A) -#define hw_get_cxx_reg( _A, _B, _C ) -#define hw_set_cxx_reg( _A, _B, _C ) +#define hw_get_cxx_reg(_A, _B, _C) +#define hw_set_cxx_reg(_A, _B, _C) diff --git a/drivers/staging/winbond/wbhal_s.h b/drivers/staging/winbond/wbhal_s.h index 372a05e3021..33457c2e39b 100644 --- a/drivers/staging/winbond/wbhal_s.h +++ b/drivers/staging/winbond/wbhal_s.h @@ -4,179 +4,166 @@ #include <linux/types.h> #include <linux/if_ether.h> /* for ETH_ALEN */ -//[20040722 WK] -#define HAL_LED_SET_MASK 0x001c //20060901 Extend -#define HAL_LED_SET_SHIFT 2 +#define HAL_LED_SET_MASK 0x001c +#define HAL_LED_SET_SHIFT 2 -//supported RF type +/* supported RF type */ #define RF_MAXIM_2825 0 #define RF_MAXIM_2827 1 #define RF_MAXIM_2828 2 #define RF_MAXIM_2829 3 -#define RF_MAXIM_V1 15 +#define RF_MAXIM_V1 15 #define RF_AIROHA_2230 16 #define RF_AIROHA_7230 17 -#define RF_AIROHA_2230S 18 // 20060420 Add this -// #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD -#define RF_WB_242 33 -#define RF_WB_242_1 34 // 20060619.5 Add +#define RF_AIROHA_2230S 18 +#define RF_WB_242 33 +#define RF_WB_242_1 34 #define RF_DECIDE_BY_INF 255 -//---------------------------------------------------------------- -// The follow define connect to upper layer -// User must modify for connection between HAL and upper layer -//---------------------------------------------------------------- - - - - -///////////////////////////////////////////////////////////////////////////////////////////////////// -//================================================================================================ -// Common define -//================================================================================================ -#define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify - -// Scan interval -#define SCAN_MAX_CHNL_TIME (50) - -// For TxL2 Frame typr recognise +/* + * ---------------------------------------------------------------- + * The follow define connect to upper layer + * User must modify for connection between HAL and upper layer + * ---------------------------------------------------------------- + */ + +/* + * ============================== + * Common define + * ============================== + */ +/* Bit 5 */ +#define HAL_USB_MODE_BURST(_H) (_H->SoftwareSet & 0x20) + +/* Scan interval */ +#define SCAN_MAX_CHNL_TIME (50) + +/* For TxL2 Frame typr recognise */ #define FRAME_TYPE_802_3_DATA 0 #define FRAME_TYPE_802_11_MANAGEMENT 1 -#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2 +#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2 #define FRAME_TYPE_802_11_CONTROL 3 #define FRAME_TYPE_802_11_DATA 4 #define FRAME_TYPE_PROMISCUOUS 5 -// The follow definition is used for convert the frame-------------------- -#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset +/* The follow definition is used for convert the frame------------ */ +#define DOT_11_SEQUENCE_OFFSET 22 /* Sequence control offset */ #define DOT_3_TYPE_OFFSET 12 -#define DOT_11_MAC_HEADER_SIZE 24 +#define DOT_11_MAC_HEADER_SIZE 24 #define DOT_11_SNAP_SIZE 6 -#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin. +#define DOT_11_TYPE_OFFSET 30 /* The start offset of 802.11 Frame. Type encapsulation. */ #define DEFAULT_SIFSTIME 10 -#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment +#define DEFAULT_FRAGMENT_THRESHOLD 2346 /* No fragment */ #define DEFAULT_MSDU_LIFE_TIME 0xffff -#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48) -#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24) -#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6) -#define Tsym 4 +#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144 + 48) +#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72 + 24) +#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16 + 4 + 6) +#define Tsym 4 -// Frame Type of Bits (2, 3)--------------------------------------------- +/* Frame Type of Bits (2, 3)----------------------------------- */ #define MAC_TYPE_MANAGEMENT 0x00 #define MAC_TYPE_CONTROL 0x04 #define MAC_TYPE_DATA 0x08 -#define MASK_FRAGMENT_NUMBER 0x000F -#define SEQUENCE_NUMBER_SHIFT 4 +#define MASK_FRAGMENT_NUMBER 0x000F +#define SEQUENCE_NUMBER_SHIFT 4 #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01 #define HAL_WOL_TYPE_MAGIC_PACKET 0x02 -// 20040106 ADDED -#define HAL_KEYTYPE_WEP40 0 -#define HAL_KEYTYPE_WEP104 1 -#define HAL_KEYTYPE_TKIP 2 // 128 bit key -#define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key +#define HAL_KEYTYPE_WEP40 0 +#define HAL_KEYTYPE_WEP104 1 +#define HAL_KEYTYPE_TKIP 2 /* 128 bit key */ +#define HAL_KEYTYPE_AES_CCMP 3 /* 128 bit key */ -// For VM state +/* For VM state */ enum { VM_STOP = 0, VM_RUNNING, VM_COMPLETED }; -//----------------------------------------------------- -// Normal Key table format -//----------------------------------------------------- -// The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX -#define MAX_KEY_TABLE 24 // 24 entry for storing key data +/* + * ================================ + * Normal Key table format + * ================================ + */ + +/* The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX */ +#define MAX_KEY_TABLE 24 /* 24 entry for storing key data */ #define GROUP_KEY_START_INDEX 4 #define MAPPING_KEY_START_INDEX 8 -//-------------------------------------------------------- -// Descriptor -//-------------------------------------------------------- -#define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2 -//#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian -#define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian -//#define FLAG_ERROR_RX_MASK 0x00000c3f -//#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian - //Don't care replay error, - //it is handled by S/W -#define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian - -#define FLAG_BAND_RX_MASK 0x10000000 //Bit 28 - -typedef struct _R00_DESCRIPTOR -{ - union - { +/* + * ========================================= + * Descriptor + * ========================================= + */ +#define MAX_DESCRIPTOR_BUFFER_INDEX 8 /* Have to multiple of 2 */ +#define FLAG_ERROR_TX_MASK 0x000000bf +#define FLAG_ERROR_RX_MASK 0x0000083f + +#define FLAG_BAND_RX_MASK 0x10000000 /* Bit 28 */ + +typedef struct _R00_DESCRIPTOR { + union { u32 value; - #ifdef _BIG_ENDIAN_ //20060926 anson's endian - struct - { +#ifdef _BIG_ENDIAN_ + struct { u32 R00_packet_or_buffer_status:1; u32 R00_packet_in_fifo:1; u32 R00_RESERVED:2; u32 R00_receive_byte_count:12; u32 R00_receive_time_index:16; }; - #else - struct - { +#else + struct { u32 R00_receive_time_index:16; u32 R00_receive_byte_count:12; u32 R00_RESERVED:2; u32 R00_packet_in_fifo:1; u32 R00_packet_or_buffer_status:1; }; - #endif +#endif }; } R00_DESCRIPTOR, *PR00_DESCRIPTOR; -typedef struct _T00_DESCRIPTOR -{ - union - { +typedef struct _T00_DESCRIPTOR { + union { u32 value; - #ifdef _BIG_ENDIAN_ //20061009 anson's endian - struct - { - u32 T00_first_mpdu:1; // for hardware use - u32 T00_last_mpdu:1; // for hardware use - u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used - u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS - u32 T00_RESERVED_ID:2;//3 bit ID reserved - u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c +#ifdef _BIG_ENDIAN_ + struct { + u32 T00_first_mpdu:1; /* for hardware use */ + u32 T00_last_mpdu:1; /* for hardware use */ + u32 T00_IsLastMpdu:1;/* 0:not 1:Yes for software used */ + u32 T00_IgnoreResult:1;/* The same mechanism with T00 setting. */ + u32 T00_RESERVED_ID:2;/* 3 bit ID reserved */ + u32 T00_tx_packet_id:4; u32 T00_RESERVED:4; u32 T00_header_length:6; u32 T00_frame_length:12; }; - #else - struct - { +#else + struct { u32 T00_frame_length:12; u32 T00_header_length:6; u32 T00_RESERVED:4; - u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c - u32 T00_RESERVED_ID:2;//3 bit ID reserved - u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS - u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used - u32 T00_last_mpdu:1; // for hardware use - u32 T00_first_mpdu:1; // for hardware use + u32 T00_tx_packet_id:4; + u32 T00_RESERVED_ID:2; /* 3 bit ID reserved */ + u32 T00_IgnoreResult:1; /* The same mechanism with T00 setting. */ + u32 T00_IsLastMpdu:1; /* 0:not 1:Yes for software used */ + u32 T00_last_mpdu:1; /* for hardware use */ + u32 T00_first_mpdu:1; /* for hardware use */ }; - #endif +#endif }; } T00_DESCRIPTOR, *PT00_DESCRIPTOR; -typedef struct _R01_DESCRIPTOR -{ - union - { +typedef struct _R01_DESCRIPTOR { + union { u32 value; - #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian - struct - { +#ifdef _BIG_ENDIAN_ + struct { u32 R01_RESERVED:3; u32 R01_mod_type:1; u32 R01_pre_type:1; @@ -197,9 +184,8 @@ typedef struct _R01_DESCRIPTOR u32 R01_icv_error:1; u32 R01_crc_error:1; }; - #else - struct - { +#else + struct { u32 R01_crc_error:1; u32 R01_icv_error:1; u32 R01_null_key_to_authentication_frame:1; @@ -220,18 +206,15 @@ typedef struct _R01_DESCRIPTOR u32 R01_mod_type:1; u32 R01_RESERVED:3; }; - #endif +#endif }; } R01_DESCRIPTOR, *PR01_DESCRIPTOR; -typedef struct _T01_DESCRIPTOR -{ - union - { +typedef struct _T01_DESCRIPTOR { + union { u32 value; - #ifdef _BIG_ENDIAN_ //20061009 anson's endian - struct - { +#ifdef _BIG_ENDIAN_ + struct { u32 T01_rts_cts_duration:16; u32 T01_fall_back_rate:3; u32 T01_add_rts:1; @@ -245,9 +228,8 @@ typedef struct _T01_DESCRIPTOR u32 T01_loop_back_wep_mode:1; u32 T01_retry_abort_ebable:1; }; - #else - struct - { +#else + struct { u32 T01_retry_abort_ebable:1; u32 T01_loop_back_wep_mode:1; u32 T01_inhibit_crc:1; @@ -261,21 +243,18 @@ typedef struct _T01_DESCRIPTOR u32 T01_fall_back_rate:3; u32 T01_rts_cts_duration:16; }; - #endif +#endif }; } T01_DESCRIPTOR, *PT01_DESCRIPTOR; -typedef struct _T02_DESCRIPTOR -{ - union - { +typedef struct _T02_DESCRIPTOR { + union { u32 value; - #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian - struct - { - u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting - u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS - u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting +#ifdef _BIG_ENDIAN_ + struct { + u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */ + u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */ + u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */ u32 T02_Tx_PktID:4; u32 T02_MPDU_Cnt:4; u32 T02_RTS_Cnt:4; @@ -290,9 +269,8 @@ typedef struct _T02_DESCRIPTOR u32 T02_transmit_abort:1; u32 T02_transmit_fail:1; }; - #else - struct - { +#else + struct { u32 T02_transmit_fail:1; u32 T02_transmit_abort:1; u32 T02_out_of_MaxTxMSDULiftTime:1; @@ -306,122 +284,120 @@ typedef struct _T02_DESCRIPTOR u32 T02_RTS_Cnt:4; u32 T02_MPDU_Cnt:4; u32 T02_Tx_PktID:4; - u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting - u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS - u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting + u32 T02_RESERVED_ID:2; /* The same mechanism with T00 setting */ + u32 T02_IgnoreResult:1; /* The same mechanism with T00 setting. */ + u32 T02_IsLastMpdu:1; /* The same mechanism with T00 setting */ }; - #endif +#endif }; } T02_DESCRIPTOR, *PT02_DESCRIPTOR; -struct wb35_descriptor { // Skip length = 8 DWORD - // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition +struct wb35_descriptor { /* Skip length = 8 DWORD */ + /* ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition */ u8 Descriptor_ID; - //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ + /* ----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ */ u8 RESERVED[3]; u16 FragmentThreshold; - u8 InternalUsed;//Only can be used by operation of descriptor definition - u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame + u8 InternalUsed; /* Only can be used by operation of descriptor definition */ + u8 Type; /* 0: 802.3 1:802.11 data frame 2:802.11 management frame */ - u8 PreambleMode;// 0: short 1:long + u8 PreambleMode;/* 0: short 1:long */ u8 TxRate; u8 FragmentCount; - u8 EapFix; // For speed up key install + u8 EapFix; /* For speed up key install */ - // For R00 and T00 ---------------------------------------------- - union - { + /* For R00 and T00 ------------------------------ */ + union { R00_DESCRIPTOR R00; T00_DESCRIPTOR T00; }; - // For R01 and T01 ---------------------------------------------- - union - { + /* For R01 and T01 ------------------------------ */ + union { R01_DESCRIPTOR R01; T01_DESCRIPTOR T01; }; - // For R02 and T02 ---------------------------------------------- - union - { - u32 R02; + /* For R02 and T02 ------------------------------ */ + union { + u32 R02; T02_DESCRIPTOR T02; }; - // For R03 and T03 ---------------------------------------------- - // For software used - union - { + /* For R03 and T03 ------------------------------ */ + /* For software used */ + union { u32 R03; u32 T03; - struct - { + struct { u8 buffer_number; u8 buffer_start_index; u16 buffer_total_size; }; }; - // For storing the buffer - u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ]; - void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q - + /* For storing the buffer */ + u16 buffer_size[MAX_DESCRIPTOR_BUFFER_INDEX]; + void *buffer_address[MAX_DESCRIPTOR_BUFFER_INDEX]; }; -#define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds +#define DEFAULT_NULL_PACKET_COUNT 180000 /* 180 seconds */ -#define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA -#define MAX_RF_PARAMETER 32 +#define MAX_TXVGA_EEPROM 9 /* How many word(u16) of EEPROM will be used for TxVGA */ +#define MAX_RF_PARAMETER 32 typedef struct _TXVGA_FOR_50 { - u8 ChanNo; - u8 TxVgaValue; + u8 ChanNo; + u8 TxVgaValue; } TXVGA_FOR_50; -//===================================================================== -// Device related include -//===================================================================== +/* + * ============================================== + * Device related include + * ============================================== + */ #include "wbusb_s.h" #include "wb35reg_s.h" #include "wb35tx_s.h" #include "wb35rx_s.h" -// For Hal using ================================================================== +/* For Hal using ============================================ */ struct hw_data { - // For compatible with 33 + /* For compatible with 33 */ u32 revision; - u32 BB3c_cal; // The value for Tx calibration comes from EEPROM - u32 BB54_cal; // The value for Rx calibration comes from EEPROM + u32 BB3c_cal; /* The value for Tx calibration comes from EEPROM */ + u32 BB54_cal; /* The value for Rx calibration comes from EEPROM */ - - // For surprise remove - u32 SurpriseRemove; // 0: Normal 1: Surprise remove + /* For surprise remove */ + u32 SurpriseRemove; /* 0: Normal 1: Surprise remove */ u8 IsKeyPreSet; - u8 CalOneTime; // 20060630.1 + u8 CalOneTime; u8 VCO_trim; - // For Fix 1'st DMA bug u32 FragCount; - u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. - - //=============================================== - // Definition for MAC address - //=============================================== - u8 PermanentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment - u8 CurrentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment - - //===================================================================== - // Definition for 802.11 - //===================================================================== - u8 *bssid_pointer; // Used by hal_get_bssid for return value - u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer - u8 ssid[32];// maximum ssid length is 32 byte + u32 DMAFix; /* V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. */ + + /* + * =============================================== + * Definition for MAC address + * =============================================== + */ + u8 PermanentMacAddress[ETH_ALEN + 2]; /* The Ethernet addr that are stored in EEPROM. + 2 to 8-byte alignment */ + u8 CurrentMacAddress[ETH_ALEN + 2]; /* The Enthernet addr that are in used. + 2 to 8-byte alignment */ + + /* + * ========================================= + * Definition for 802.11 + * ========================================= + */ + u8 *bssid_pointer; /* Used by hal_get_bssid for return value */ + u8 bssid[8]; /* Only 6 byte will be used. 8 byte is required for read buffer */ + u8 ssid[32]; /* maximum ssid length is 32 byte */ u16 AID; u8 ssid_length; @@ -433,112 +409,118 @@ struct hw_data { u16 BeaconPeriod; u16 ProbeDelay; - u8 bss_type;// 0: IBSS_NET or 1:ESS_NET - u8 preamble;// 0: short preamble, 1: long preamble - u8 slot_time_select;// 9 or 20 value - u8 phy_type;// Phy select + u8 bss_type;/* 0: IBSS_NET or 1:ESS_NET */ + u8 preamble;/* 0: short preamble, 1: long preamble */ + u8 slot_time_select; /* 9 or 20 value */ + u8 phy_type; /* Phy select */ u32 phy_para[MAX_RF_PARAMETER]; u32 phy_number; - u32 CurrentRadioSw; // 20060320.2 0:On 1:Off - u32 CurrentRadioHw; // 20060825 0:On 1:Off + u32 CurrentRadioSw; /* 0:On 1:Off */ + u32 CurrentRadioHw; /* 0:On 1:Off */ - u8 *power_save_point; // Used by hal_get_power_save_mode for return value + u8 *power_save_point; /* Used by hal_get_power_save_mode for return value */ u8 cwmin; u8 desired_power_save; - u8 dtim;// Is running dtim - u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r + u8 dtim; /* Is running dtim */ + u8 mapping_key_replace_index; /* In Key table, the next index be replaced */ u16 MaxReceiveLifeTime; u16 FragmentThreshold; u16 FragmentThreshold_tmp; u16 cwmax; - u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment - u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit) + u8 Key_slot[MAX_KEY_TABLE][8]; /* Ownership record for key slot. For Alignment */ + u32 Key_content[MAX_KEY_TABLE][12]; /* 10DW for each entry + 2 for burst command (Off and On valid bit) */ u8 CurrentDefaultKeyIndex; u32 CurrentDefaultKeyLength; - //======================================================================== - // Variable for each module - //======================================================================== - struct wb_usb WbUsb; // Need WbUsb.h - struct wb35_reg reg; // Need Wb35Reg.h - struct wb35_tx Wb35Tx; // Need Wb35Tx.h - struct wb35_rx Wb35Rx; // Need Wb35Rx.h + /* + * ================================================== + * Variable for each module + * ================================================== + */ + struct wb_usb WbUsb; /* Need WbUsb.h */ + struct wb35_reg reg; /* Need Wb35Reg.h */ + struct wb35_tx Wb35Tx; /* Need Wb35Tx.h */ + struct wb35_rx Wb35Rx; /* Need Wb35Rx.h */ - struct timer_list LEDTimer;// For LED + struct timer_list LEDTimer; /* For LED */ - u32 LEDpoint;// For LED + u32 LEDpoint; /* For LED */ - u32 dto_tx_retry_count; // LA20040210_DTO kevin - u32 dto_tx_frag_count; // LA20040210_DTO kevin - u32 rx_ok_count[13]; // index=0: total rx ok - //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes - u32 rx_err_count[13]; // index=0: total rx err + u32 dto_tx_retry_count; + u32 dto_tx_frag_count; + u32 rx_ok_count[13]; /* index=0: total rx ok */ + u32 rx_err_count[13]; /* index=0: total rx err */ - //for Tx debug + /* for Tx debug */ u32 tx_TBTT_start_count; u32 tx_ETR_count; u32 tx_WepOn_false_count; u32 tx_Null_key_count; u32 tx_retry_count[8]; - u8 PowerIndexFromEEPROM; // For 2412MHz - u8 power_index; - u8 IsWaitJoinComplete; // TRUE: set join request - u8 band; + u8 PowerIndexFromEEPROM; /* For 2412MHz */ + u8 power_index; + u8 IsWaitJoinComplete; /* TRUE: set join request */ + u8 band; - u16 SoftwareSet; - u16 Reserved_s; + u16 SoftwareSet; + u16 Reserved_s; - u32 IsInitOK; // 0: Driver starting 1: Driver init OK + u32 IsInitOK; /* 0: Driver starting 1: Driver init OK */ - // For Phy calibration - s32 iq_rsdl_gain_tx_d2; - s32 iq_rsdl_phase_tx_d2; - u32 txvga_setting_for_cal; // 20060703.1 Add + /* For Phy calibration */ + s32 iq_rsdl_gain_tx_d2; + s32 iq_rsdl_phase_tx_d2; + u32 txvga_setting_for_cal; - u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value - u8 TxVgaFor24[16]; // Max is 14, 2 for alignment - TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments + u8 TxVgaSettingInEEPROM[(((MAX_TXVGA_EEPROM * 2) + 3) & ~0x03)]; /* For EEPROM value */ + u8 TxVgaFor24[16]; /* Max is 14, 2 for alignment */ + TXVGA_FOR_50 TxVgaFor50[36]; /* 35 channels in 5G. 35x2 = 70 byte. 2 for alignments */ - u16 Scan_Interval; - u16 RESERVED6; + u16 Scan_Interval; + u16 RESERVED6; - // LED control + /* LED control */ u32 LED_control; - // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0] - // Gray_Led - // For Led gray setting - // Led - // 0: normal control, LED behavior will decide by EEPROM setting - // 1: Turn off specific LED - // 2: Always on specific LED - // 3: slow blinking specific LED - // 4: fast blinking specific LED - // 5: WPS led control is set. Led0 is Red, Led1 id Green - // Led[1] is parameter for WPS LED mode - // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control - - u32 LED_LinkOn; //Turn LED on control - u32 LED_Scanning; // Let LED in scan process control - u32 LED_Blinking; // Temp variable for shining + /* + * LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0] + * Gray_Led + * For Led gray setting + * Led + * 0: normal control, + * LED behavior will decide by EEPROM setting + * 1: Turn off specific LED + * 2: Always on specific LED + * 3: slow blinking specific LED + * 4: fast blinking specific LED + * 5: WPS led control is set. Led0 is Red, Led1 id Green + * + * Led[1] is parameter for WPS LED mode + * 1:InProgress + * 2: Error + * 3: Session overlap + * 4: Success control + */ + u32 LED_LinkOn; /* Turn LED on control */ + u32 LED_Scanning; /* Let LED in scan process control */ + u32 LED_Blinking; /* Temp variable for shining */ u32 RxByteCountLast; u32 TxByteCountLast; atomic_t SurpriseRemoveCount; - // For global timer - u32 time_count;//TICK_TIME_100ms 1 = 100ms + /* For global timer */ + u32 time_count; /* TICK_TIME_100ms 1 = 100ms */ - // For error recover + /* For error recover */ u32 HwStop; - // 20060828.1 for avoid AP disconnect + /* For avoid AP disconnect */ u32 NullPacketCount; - }; #endif diff --git a/drivers/staging/winbond/wblinux_f.h b/drivers/staging/winbond/wblinux_f.h index 868e8772724..0a9d214f718 100644 --- a/drivers/staging/winbond/wblinux_f.h +++ b/drivers/staging/winbond/wblinux_f.h @@ -4,13 +4,14 @@ #include "core.h" #include "mds_s.h" -//========================================================================= -// Copyright (c) 1996-2004 Winbond Electronic Corporation -// -// wblinux_f.h -// -int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev ); -void wb35_set_multicast( struct net_device *netdev ); -struct net_device_stats * wb35_netdev_stats( struct net_device *netdev ); - +/* + * ==================================================================== + * Copyright (c) 1996-2004 Winbond Electronic Corporation + * + * wblinux_f.h + * ==================================================================== + */ +int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev); +void wb35_set_multicast(struct net_device *netdev); +struct net_device_stats *wb35_netdev_stats(struct net_device *netdev); #endif diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c index 5d9499bba9c..681419d6856 100644 --- a/drivers/staging/winbond/wbusb.c +++ b/drivers/staging/winbond/wbusb.c @@ -142,19 +142,17 @@ static void hal_set_radio_mode(struct hw_data *pHwData, unsigned char radio_off) if (pHwData->SurpriseRemove) return; - if (radio_off) //disable Baseband receive off - { - pHwData->CurrentRadioSw = 1; // off + if (radio_off) { /* disable Baseband receive off */ + pHwData->CurrentRadioSw = 1; /* off */ reg->M24_MacControl &= 0xffffffbf; } else { - pHwData->CurrentRadioSw = 0; // on + pHwData->CurrentRadioSw = 0; /* on */ reg->M24_MacControl |= 0x00000040; } Wb35Reg_Write(pHwData, 0x0824, reg->M24_MacControl); } -static void -hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info channel) +static void hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info channel) { struct wb35_reg *reg = &pHwData->reg; @@ -163,17 +161,18 @@ hal_set_current_channel_ex(struct hw_data *pHwData, struct chan_info channel) printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo); - RFSynthesizer_SwitchingChannel(pHwData, channel); // Switch channel + RFSynthesizer_SwitchingChannel(pHwData, channel); /* Switch channel */ pHwData->Channel = channel.ChanNo; pHwData->band = channel.band; #ifdef _PE_STATE_DUMP_ printk("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band); #endif - reg->M28_MacControl &= ~0xff; // Clean channel information field + reg->M28_MacControl &= ~0xff; /* Clean channel information field */ reg->M28_MacControl |= channel.ChanNo; Wb35Reg_WriteWithCallbackValue(pHwData, 0x0828, reg->M28_MacControl, - (s8 *) & channel, sizeof(struct chan_info)); + (s8 *) &channel, + sizeof(struct chan_info)); } static void hal_set_current_channel(struct hw_data *pHwData, struct chan_info channel) @@ -188,21 +187,22 @@ static void hal_set_accept_broadcast(struct hw_data *pHwData, u8 enable) if (pHwData->SurpriseRemove) return; - reg->M00_MacControl &= ~0x02000000; //The HW value + reg->M00_MacControl &= ~0x02000000; /* The HW value */ if (enable) - reg->M00_MacControl |= 0x02000000; //The HW value + reg->M00_MacControl |= 0x02000000; /* The HW value */ Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); } -//for wep key error detection, we need to accept broadcast packets to be received temporary. +/* For wep key error detection, we need to accept broadcast packets to be received temporary. */ static void hal_set_accept_promiscuous(struct hw_data *pHwData, u8 enable) { struct wb35_reg *reg = &pHwData->reg; if (pHwData->SurpriseRemove) return; + if (enable) { reg->M00_MacControl |= 0x00400000; Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); @@ -219,9 +219,9 @@ static void hal_set_accept_multicast(struct hw_data *pHwData, u8 enable) if (pHwData->SurpriseRemove) return; - reg->M00_MacControl &= ~0x01000000; //The HW value + reg->M00_MacControl &= ~0x01000000; /* The HW value */ if (enable) - reg->M00_MacControl |= 0x01000000; //The HW value + reg->M00_MacControl |= 0x01000000; /* The HW value */ Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); } @@ -232,13 +232,12 @@ static void hal_set_accept_beacon(struct hw_data *pHwData, u8 enable) if (pHwData->SurpriseRemove) return; - // 20040108 debug - if (!enable) //Due to SME and MLME are not suitable for 35 + if (!enable) /* Due to SME and MLME are not suitable for 35 */ return; - reg->M00_MacControl &= ~0x04000000; //The HW value + reg->M00_MacControl &= ~0x04000000; /* The HW value */ if (enable) - reg->M00_MacControl |= 0x04000000; //The HW value + reg->M00_MacControl |= 0x04000000; /* The HW value */ Wb35Reg_Write(pHwData, 0x0800, reg->M00_MacControl); } @@ -283,8 +282,7 @@ static const struct ieee80211_ops wbsoft_ops = { .get_tsf = wbsoft_get_tsf, }; -static void -hal_set_ethernet_address(struct hw_data *pHwData, u8 * current_address) +static void hal_set_ethernet_address(struct hw_data *pHwData, u8 *current_address) { u32 ltmp[2]; @@ -294,14 +292,12 @@ hal_set_ethernet_address(struct hw_data *pHwData, u8 * current_address) memcpy(pHwData->CurrentMacAddress, current_address, ETH_ALEN); ltmp[0] = cpu_to_le32(*(u32 *) pHwData->CurrentMacAddress); - ltmp[1] = - cpu_to_le32(*(u32 *) (pHwData->CurrentMacAddress + 4)) & 0xffff; + ltmp[1] = cpu_to_le32(*(u32 *) (pHwData->CurrentMacAddress + 4)) & 0xffff; Wb35Reg_BurstWrite(pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT); } -static void -hal_get_permanent_address(struct hw_data *pHwData, u8 * pethernet_address) +static void hal_get_permanent_address(struct hw_data *pHwData, u8 *pethernet_address) { if (pHwData->SurpriseRemove) return; @@ -319,7 +315,7 @@ static void hal_stop(struct hw_data *pHwData) pHwData->Wb35Tx.tx_halt = 1; Wb35Tx_stop(pHwData); - reg->D00_DmaControl &= ~0xc0000000; //Tx Off, Rx Off + reg->D00_DmaControl &= ~0xc0000000; /* Tx Off, Rx Off */ Wb35Reg_Write(pHwData, 0x0400, reg->D00_DmaControl); } @@ -346,14 +342,14 @@ u8 hal_get_antenna_number(struct hw_data *pHwData) } /* 0 : radio on; 1: radio off */ -static u8 hal_get_hw_radio_off(struct hw_data * pHwData) +static u8 hal_get_hw_radio_off(struct hw_data *pHwData) { struct wb35_reg *reg = &pHwData->reg; if (pHwData->SurpriseRemove) return 1; - //read the bit16 of register U1B0 + /* read the bit16 of register U1B0 */ Wb35Reg_Read(pHwData, 0x3b0, ®->U1B0); if ((reg->U1B0 & 0x00010000)) { pHwData->CurrentRadioHw = 1; @@ -387,104 +383,98 @@ static void hal_led_control(unsigned long data) if (pHwData->LED_control) { ltmp2 = pHwData->LED_control & 0xff; - if (ltmp2 == 5) // 5 is WPS mode - { + if (ltmp2 == 5) { /* 5 is WPS mode */ TimeInterval = 100; ltmp2 = (pHwData->LED_control >> 8) & 0xff; switch (ltmp2) { - case 1: // [0.2 On][0.1 Off]... + case 1: /* [0.2 On][0.1 Off]... */ pHwData->LED_Blinking %= 3; - ltmp = 0x1010; // Led 1 & 0 Green and Red - if (pHwData->LED_Blinking == 2) // Turn off + ltmp = 0x1010; /* Led 1 & 0 Green and Red */ + if (pHwData->LED_Blinking == 2) /* Turn off */ ltmp = 0; break; - case 2: // [0.1 On][0.1 Off]... + case 2: /* [0.1 On][0.1 Off]... */ pHwData->LED_Blinking %= 2; - ltmp = 0x0010; // Led 0 red color - if (pHwData->LED_Blinking) // Turn off + ltmp = 0x0010; /* Led 0 red color */ + if (pHwData->LED_Blinking) /* Turn off */ ltmp = 0; break; - case 3: // [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]... + case 3: /* [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]... */ pHwData->LED_Blinking %= 15; - ltmp = 0x0010; // Led 0 red color - if ((pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking % 2)) // Turn off 0.6 sec + ltmp = 0x0010; /* Led 0 red color */ + if ((pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking % 2)) /* Turn off 0.6 sec */ ltmp = 0; break; - case 4: // [300 On][ off ] - ltmp = 0x1000; // Led 1 Green color + case 4: /* [300 On][ off ] */ + ltmp = 0x1000; /* Led 1 Green color */ if (pHwData->LED_Blinking >= 3000) - ltmp = 0; // led maybe on after 300sec * 32bit counter overlap. + ltmp = 0; /* led maybe on after 300sec * 32bit counter overlap. */ break; } pHwData->LED_Blinking++; reg->U1BC_LEDConfigure = ltmp; - if (LEDSet != 7) // Only 111 mode has 2 LEDs on PCB. - { - reg->U1BC_LEDConfigure |= (ltmp & 0xff) << 8; // Copy LED result to each LED control register + if (LEDSet != 7) { /* Only 111 mode has 2 LEDs on PCB. */ + reg->U1BC_LEDConfigure |= (ltmp & 0xff) << 8; /* Copy LED result to each LED control register */ reg->U1BC_LEDConfigure |= (ltmp & 0xff00) >> 8; } Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); } - } else if (pHwData->CurrentRadioSw || pHwData->CurrentRadioHw) // If radio off - { + } else if (pHwData->CurrentRadioSw || pHwData->CurrentRadioHw) { /* If radio off */ if (reg->U1BC_LEDConfigure & 0x1010) { reg->U1BC_LEDConfigure &= ~0x1010; Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); } } else { switch (LEDSet) { - case 4: // [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing - if (!pHwData->LED_LinkOn) // Blink only if not Link On - { - // Blinking if scanning is on progress + case 4: /* [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing */ + if (!pHwData->LED_LinkOn) { /* Blink only if not Link On */ + /* Blinking if scanning is on progress */ if (pHwData->LED_Scanning) { if (pHwData->LED_Blinking == 0) { reg->U1BC_LEDConfigure |= 0x10; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 On + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 On */ pHwData->LED_Blinking = 1; TimeInterval = 300; } else { reg->U1BC_LEDConfigure &= ~0x10; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 Off + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ pHwData->LED_Blinking = 0; TimeInterval = 300; } } else { - //Turn Off LED_0 + /* Turn Off LED_0 */ if (reg->U1BC_LEDConfigure & 0x10) { reg->U1BC_LEDConfigure &= ~0x10; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 Off + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ } } } else { - // Turn On LED_0 + /* Turn On LED_0 */ if ((reg->U1BC_LEDConfigure & 0x10) == 0) { reg->U1BC_LEDConfigure |= 0x10; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 Off + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ } } break; - - case 6: // [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing - if (!pHwData->LED_LinkOn) // Blink only if not Link On - { - // Blinking if scanning is on progress + case 6: /* [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing */ + if (!pHwData->LED_LinkOn) { /* Blink only if not Link On */ + /* Blinking if scanning is on progress */ if (pHwData->LED_Scanning) { if (pHwData->LED_Blinking == 0) { reg->U1BC_LEDConfigure &= ~0xf; reg->U1BC_LEDConfigure |= 0x10; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 On + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 On */ pHwData->LED_Blinking = 1; TimeInterval = 300; } else { reg->U1BC_LEDConfigure &= ~0x1f; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 Off + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ pHwData->LED_Blinking = 0; TimeInterval = 300; } } else { - // 20060901 Gray blinking if in disconnect state and not scanning + /* Gray blinking if in disconnect state and not scanning */ ltmp = reg->U1BC_LEDConfigure; reg->U1BC_LEDConfigure &= ~0x1f; if (LED_GRAY2[(pHwData->LED_Blinking % 30)]) { @@ -494,85 +484,78 @@ static void hal_led_control(unsigned long data) } pHwData->LED_Blinking++; if (reg->U1BC_LEDConfigure != ltmp) - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 Off + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ TimeInterval = 100; } } else { - // Turn On LED_0 + /* Turn On LED_0 */ if ((reg->U1BC_LEDConfigure & 0x10) == 0) { reg->U1BC_LEDConfigure |= 0x10; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_0 Off + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_0 Off */ } } break; - - case 5: // [101] Only 1 Led be placed on PCB and use LED_1 for showing - if (!pHwData->LED_LinkOn) // Blink only if not Link On - { - // Blinking if scanning is on progress + case 5: /* [101] Only 1 Led be placed on PCB and use LED_1 for showing */ + if (!pHwData->LED_LinkOn) { /* Blink only if not Link On */ + /* Blinking if scanning is on progress */ if (pHwData->LED_Scanning) { if (pHwData->LED_Blinking == 0) { - reg->U1BC_LEDConfigure |= - 0x1000; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_1 On + reg->U1BC_LEDConfigure |= 0x1000; + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 On */ pHwData->LED_Blinking = 1; TimeInterval = 300; } else { - reg->U1BC_LEDConfigure &= - ~0x1000; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_1 Off + reg->U1BC_LEDConfigure &= ~0x1000; + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 Off */ pHwData->LED_Blinking = 0; TimeInterval = 300; } } else { - //Turn Off LED_1 + /* Turn Off LED_1 */ if (reg->U1BC_LEDConfigure & 0x1000) { - reg->U1BC_LEDConfigure &= - ~0x1000; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_1 Off + reg->U1BC_LEDConfigure &= ~0x1000; + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 Off */ } } } else { - // Is transmitting/receiving ?? + /* Is transmitting/receiving ?? */ if ((adapter->RxByteCount != pHwData->RxByteCountLast) || (adapter->TxByteCount != pHwData->TxByteCountLast)) { if ((reg->U1BC_LEDConfigure & 0x3000) != 0x3000) { - reg->U1BC_LEDConfigure |= - 0x3000; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_1 On + reg->U1BC_LEDConfigure |= 0x3000; + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 On */ } - // Update variable + /* Update variable */ pHwData->RxByteCountLast = adapter->RxByteCount; pHwData->TxByteCountLast = adapter->TxByteCount; TimeInterval = 200; } else { - // Turn On LED_1 and blinking if transmitting/receiving + /* Turn On LED_1 and blinking if transmitting/receiving */ if ((reg->U1BC_LEDConfigure & 0x3000) != 0x1000) { reg->U1BC_LEDConfigure &= ~0x3000; reg->U1BC_LEDConfigure |= 0x1000; - Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); // LED_1 On + Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); /* LED_1 On */ } } } break; - - default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active + default: /* Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active */ if ((reg->U1BC_LEDConfigure & 0x3000) != 0x3000) { - reg->U1BC_LEDConfigure |= 0x3000; // LED_1 is always on and event enable + reg->U1BC_LEDConfigure |= 0x3000; /* LED_1 is always on and event enable */ Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); } if (pHwData->LED_Blinking) { - // Gray blinking + /* Gray blinking */ reg->U1BC_LEDConfigure &= ~0x0f; reg->U1BC_LEDConfigure |= 0x10; reg->U1BC_LEDConfigure |= @@ -584,7 +567,7 @@ static void hal_led_control(unsigned long data) if (pHwData->LED_Blinking < 40) TimeInterval = 100; else { - pHwData->LED_Blinking = 0; // Stop blinking + pHwData->LED_Blinking = 0; /* Stop blinking */ reg->U1BC_LEDConfigure &= ~0x0f; Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); @@ -593,16 +576,14 @@ static void hal_led_control(unsigned long data) } if (pHwData->LED_LinkOn) { - if (!(reg->U1BC_LEDConfigure & 0x10)) // Check the LED_0 - { - //Try to turn ON LED_0 after gray blinking + if (!(reg->U1BC_LEDConfigure & 0x10)) { /* Check the LED_0 */ + /* Try to turn ON LED_0 after gray blinking */ reg->U1BC_LEDConfigure |= 0x10; - pHwData->LED_Blinking = 1; //Start blinking + pHwData->LED_Blinking = 1; /* Start blinking */ TimeInterval = 50; } } else { - if (reg->U1BC_LEDConfigure & 0x10) // Check the LED_0 - { + if (reg->U1BC_LEDConfigure & 0x10) { /* Check the LED_0 */ reg->U1BC_LEDConfigure &= ~0x10; Wb35Reg_Write(pHwData, 0x03bc, reg->U1BC_LEDConfigure); @@ -611,7 +592,7 @@ static void hal_led_control(unsigned long data) break; } - //20060828.1 Active send null packet to avoid AP disconnect + /* Active send null packet to avoid AP disconnect */ if (pHwData->LED_LinkOn) { pHwData->NullPacketCount += TimeInterval; if (pHwData->NullPacketCount >= @@ -622,7 +603,7 @@ static void hal_led_control(unsigned long data) } pHwData->time_count += TimeInterval; - Wb35Tx_CurrentTime(adapter, pHwData->time_count); // 20060928 add + Wb35Tx_CurrentTime(adapter, pHwData->time_count); pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(TimeInterval); add_timer(&pHwData->LEDTimer); } @@ -654,7 +635,7 @@ static int hal_init_hardware(struct ieee80211_hw *hw) SoftwareSet = hal_software_set(pHwData); #ifdef Vendor2 - // Try to make sure the EEPROM contain + /* Try to make sure the EEPROM contain */ SoftwareSet >>= 8; if (SoftwareSet != 0x82) return false; diff --git a/drivers/staging/winbond/wbusb_s.h b/drivers/staging/winbond/wbusb_s.h index 0c7e6a383f2..8961ae594c4 100644 --- a/drivers/staging/winbond/wbusb_s.h +++ b/drivers/staging/winbond/wbusb_s.h @@ -1,16 +1,10 @@ -//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -// Copyright (c) 1996-2004 Winbond Electronic Corporation -// -// Module Name: -// wbusb_s.h -// -// Abstract: -// Linux driver. -// -// Author: -// -//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - +/* ========================================================= + * Copyright (c) 1996-2004 Winbond Electronic Corporation + * + * Module Name: + * wbusb_s.h + * ========================================================= + */ #ifndef __WINBOND_WBUSB_S_H #define __WINBOND_WBUSB_S_H @@ -18,8 +12,7 @@ struct wb_usb { u32 IsUsb20; - struct usb_device *udev; + struct usb_device *udev; u32 DetectCount; }; - #endif |