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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-23 12:33:02 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-23 12:33:02 -0700
commitc44dead70a841d90ddc01968012f323c33217c9e (patch)
tree85489ebe9b9a3413cd8ee197ffb40c8aa8d97e63 /drivers/usb/gadget
parent99dff5856220a02b8711f2e8746413ea6e53ccf6 (diff)
parentd5f6db9e1aff6ccf1876224f152c0268b0c8a992 (diff)
Merge branch 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
* 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (205 commits) USB: EHCI: Remove SPARC_LEON {read,write}_be definitions from ehci.h USB: UHCI: Support big endian GRUSBHC HC sparc: add {read,write}*_be routines USB: UHCI: Add support for big endian descriptors USB: UHCI: Use ACCESS_ONCE rather than using a full compiler barrier USB: UHCI: Add support for big endian mmio usb-storage: Correct adjust_quirks to include latest flags usb/isp1760: Fix possible unlink problems usb/isp1760: Move function isp1760_endpoint_disable() within file. USB: remove remaining usages of hcd->state from usbcore and fix regression usb: musb: ux500: add configuration and build options for ux500 dma usb: musb: ux500: add dma glue layer for ux500 usb: musb: ux500: add dma name for ux500 usb: musb: ux500: add ux500 specific code for gadget side usb: musb: fix compile error usb-storage: fix up the unusual_realtek device list USB: gadget: f_audio: Fix invalid dereference of initdata EHCI: don't rescan interrupt QHs needlessly OHCI: fix regression caused by nVidia shutdown workaround USB: OTG: msm: Free VCCCX regulator even if we can't set the voltage ...
Diffstat (limited to 'drivers/usb/gadget')
-rw-r--r--drivers/usb/gadget/Kconfig35
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/at91_udc.c2
-rw-r--r--drivers/usb/gadget/ci13xxx_udc.c75
-rw-r--r--drivers/usb/gadget/composite.c62
-rw-r--r--drivers/usb/gadget/dbgp.c14
-rw-r--r--drivers/usb/gadget/dummy_hcd.c21
-rw-r--r--drivers/usb/gadget/f_audio.c2
-rw-r--r--drivers/usb/gadget/f_mass_storage.c68
-rw-r--r--drivers/usb/gadget/f_rndis.c3
-rw-r--r--drivers/usb/gadget/file_storage.c55
-rw-r--r--drivers/usb/gadget/fsl_qe_udc.h2
-rw-r--r--drivers/usb/gadget/fsl_udc_core.c438
-rw-r--r--drivers/usb/gadget/fsl_usb2_udc.h6
-rw-r--r--drivers/usb/gadget/gadget_chips.h17
-rw-r--r--drivers/usb/gadget/printer.c2
-rw-r--r--drivers/usb/gadget/s3c-hsotg.c235
-rw-r--r--drivers/usb/gadget/s3c-hsudc.c1349
-rw-r--r--drivers/usb/gadget/storage_common.c18
19 files changed, 2107 insertions, 298 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index bc5123cf41c..58456d1aec2 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -260,6 +260,24 @@ config USB_R8A66597
default USB_GADGET
select USB_GADGET_SELECTED
+config USB_GADGET_RENESAS_USBHS
+ boolean "Renesas USBHS"
+ depends on USB_RENESAS_USBHS
+ select USB_GADGET_DUALSPEED
+ help
+ Renesas USBHS is a discrete USB host and peripheral controller
+ chip that supports both full and high speed USB 2.0 data transfers.
+ platform is able to configure endpoint (pipe) style
+
+ Say "y" to enable the gadget specific portion of the USBHS driver.
+
+
+config USB_RENESAS_USBHS_UDC
+ tristate
+ depends on USB_GADGET_RENESAS_USBHS
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
config USB_GADGET_PXA27X
boolean "PXA 27x"
depends on ARCH_PXA && (PXA27x || PXA3xx)
@@ -338,6 +356,23 @@ config USB_S3C2410_DEBUG
boolean "S3C2410 udc debug messages"
depends on USB_GADGET_S3C2410
+config USB_GADGET_S3C_HSUDC
+ boolean "S3C2416, S3C2443 and S3C2450 USB Device Controller"
+ depends on ARCH_S3C2410
+ select USB_GADGET_DUALSPEED
+ help
+ Samsung's S3C2416, S3C2443 and S3C2450 is an ARM9 based SoC
+ integrated with dual speed USB 2.0 device controller. It has
+ 8 endpoints, as well as endpoint zero.
+
+ This driver has been tested on S3C2416 and S3C2450 processors.
+
+config USB_S3C_HSUDC
+ tristate
+ depends on USB_GADGET_S3C_HSUDC
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
config USB_GADGET_PXA_U2O
boolean "PXA9xx Processor USB2.0 controller"
select USB_GADGET_DUALSPEED
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 1ea15ee74fd..4fe92b18a05 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
obj-$(CONFIG_USB_CI13XXX_PCI) += ci13xxx_pci.o
obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
+obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
obj-$(CONFIG_USB_EG20T) += pch_udc.o
obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 9b7cdb16f26..41dc093c0a1 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -1767,7 +1767,7 @@ static int __init at91udc_probe(struct platform_device *pdev)
}
/* newer chips have more FIFO memory than rm9200 */
- if (cpu_is_at91sam9260()) {
+ if (cpu_is_at91sam9260() || cpu_is_at91sam9g20()) {
udc->ep[0].maxpacket = 64;
udc->ep[3].maxpacket = 64;
udc->ep[4].maxpacket = 512;
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index e09178bc145..baaf87ed768 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -310,7 +310,7 @@ static int hw_device_reset(struct ci13xxx *udc)
udc->udc_driver->notify_event(udc,
CI13XXX_CONTROLLER_RESET_EVENT);
- if (udc->udc_driver->flags && CI13XXX_DISABLE_STREAMING)
+ if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
/* USBMODE should be configured step by step */
@@ -1634,8 +1634,6 @@ static int _gadget_stop_activity(struct usb_gadget *gadget)
gadget_for_each_ep(ep, gadget) {
usb_ep_disable(ep);
}
- usb_ep_disable(&udc->ep0out.ep);
- usb_ep_disable(&udc->ep0in.ep);
if (udc->status != NULL) {
usb_ep_free_request(&udc->ep0in.ep, udc->status);
@@ -1678,18 +1676,10 @@ __acquires(udc->lock)
if (retval)
goto done;
- retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
- if (retval)
- goto done;
+ udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
+ if (udc->status == NULL)
+ retval = -ENOMEM;
- retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
- if (!retval) {
- udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
- if (udc->status == NULL) {
- usb_ep_disable(&udc->ep0out.ep);
- retval = -ENOMEM;
- }
- }
spin_lock(udc->lock);
done:
@@ -1843,7 +1833,8 @@ __releases(mEp->lock)
__acquires(mEp->lock)
{
struct ci13xxx_req *mReq, *mReqTemp;
- int retval;
+ struct ci13xxx_ep *mEpTemp = mEp;
+ int uninitialized_var(retval);
trace("%p", mEp);
@@ -1859,12 +1850,15 @@ __acquires(mEp->lock)
dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
if (mReq->req.complete != NULL) {
spin_unlock(mEp->lock);
- mReq->req.complete(&mEp->ep, &mReq->req);
+ if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
+ mReq->req.length)
+ mEpTemp = &_udc->ep0in;
+ mReq->req.complete(&mEpTemp->ep, &mReq->req);
spin_lock(mEp->lock);
}
}
- if (retval == EBUSY)
+ if (retval == -EBUSY)
retval = 0;
if (retval < 0)
dbg_event(_usb_addr(mEp), "DONE", retval);
@@ -1894,7 +1888,7 @@ __acquires(udc->lock)
for (i = 0; i < hw_ep_max; i++) {
struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
- int type, num, err = -EINVAL;
+ int type, num, dir, err = -EINVAL;
struct usb_ctrlrequest req;
if (mEp->desc == NULL)
@@ -1952,7 +1946,10 @@ __acquires(udc->lock)
if (req.wLength != 0)
break;
num = le16_to_cpu(req.wIndex);
+ dir = num & USB_ENDPOINT_DIR_MASK;
num &= USB_ENDPOINT_NUMBER_MASK;
+ if (dir) /* TX */
+ num += hw_ep_max/2;
if (!udc->ci13xxx_ep[num].wedge) {
spin_unlock(udc->lock);
err = usb_ep_clear_halt(
@@ -2001,7 +1998,10 @@ __acquires(udc->lock)
if (req.wLength != 0)
break;
num = le16_to_cpu(req.wIndex);
+ dir = num & USB_ENDPOINT_DIR_MASK;
num &= USB_ENDPOINT_NUMBER_MASK;
+ if (dir) /* TX */
+ num += hw_ep_max/2;
spin_unlock(udc->lock);
err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
@@ -2110,7 +2110,12 @@ static int ep_enable(struct usb_ep *ep,
(mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
- retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
+ /*
+ * Enable endpoints in the HW other than ep0 as ep0
+ * is always enabled
+ */
+ if (mEp->num)
+ retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
spin_unlock_irqrestore(mEp->lock, flags);
return retval;
@@ -2242,11 +2247,15 @@ static int ep_queue(struct usb_ep *ep, struct usb_request *req,
spin_lock_irqsave(mEp->lock, flags);
- if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
- !list_empty(&mEp->qh.queue)) {
- _ep_nuke(mEp);
- retval = -EOVERFLOW;
- warn("endpoint ctrl %X nuked", _usb_addr(mEp));
+ if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
+ if (req->length)
+ mEp = (_udc->ep0_dir == RX) ?
+ &_udc->ep0out : &_udc->ep0in;
+ if (!list_empty(&mEp->qh.queue)) {
+ _ep_nuke(mEp);
+ retval = -EOVERFLOW;
+ warn("endpoint ctrl %X nuked", _usb_addr(mEp));
+ }
}
/* first nuke then test link, e.g. previous status has not sent */
@@ -2497,6 +2506,15 @@ out:
return ret;
}
+static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
+{
+ struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
+
+ if (udc->transceiver)
+ return otg_set_power(udc->transceiver, mA);
+ return -ENOTSUPP;
+}
+
/**
* Device operations part of the API to the USB controller hardware,
* which don't involve endpoints (or i/o)
@@ -2505,6 +2523,7 @@ out:
static const struct usb_gadget_ops usb_gadget_ops = {
.vbus_session = ci13xxx_vbus_session,
.wakeup = ci13xxx_wakeup,
+ .vbus_draw = ci13xxx_vbus_draw,
};
/**
@@ -2595,6 +2614,14 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
}
if (retval)
goto done;
+ spin_unlock_irqrestore(udc->lock, flags);
+ retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
+ if (retval)
+ return retval;
+ retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
+ if (retval)
+ return retval;
+ spin_lock_irqsave(udc->lock, flags);
udc->gadget.ep0 = &udc->ep0in.ep;
/* bind gadget */
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 82314ed2250..5cbb1a41c22 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -461,12 +461,23 @@ static int set_config(struct usb_composite_dev *cdev,
reset_config(cdev);
goto done;
}
+
+ if (result == USB_GADGET_DELAYED_STATUS) {
+ DBG(cdev,
+ "%s: interface %d (%s) requested delayed status\n",
+ __func__, tmp, f->name);
+ cdev->delayed_status++;
+ DBG(cdev, "delayed_status count %d\n",
+ cdev->delayed_status);
+ }
}
/* when we return, be sure our power usage is valid */
power = c->bMaxPower ? (2 * c->bMaxPower) : CONFIG_USB_GADGET_VBUS_DRAW;
done:
usb_gadget_vbus_draw(gadget, power);
+ if (result >= 0 && cdev->delayed_status)
+ result = USB_GADGET_DELAYED_STATUS;
return result;
}
@@ -895,6 +906,14 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
if (w_value && !f->set_alt)
break;
value = f->set_alt(f, w_index, w_value);
+ if (value == USB_GADGET_DELAYED_STATUS) {
+ DBG(cdev,
+ "%s: interface %d (%s) requested delayed status\n",
+ __func__, intf, f->name);
+ cdev->delayed_status++;
+ DBG(cdev, "delayed_status count %d\n",
+ cdev->delayed_status);
+ }
break;
case USB_REQ_GET_INTERFACE:
if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
@@ -958,7 +977,7 @@ unknown:
}
/* respond with data transfer before status phase? */
- if (value >= 0) {
+ if (value >= 0 && value != USB_GADGET_DELAYED_STATUS) {
req->length = value;
req->zero = value < w_length;
value = usb_ep_queue(gadget->ep0, req, GFP_ATOMIC);
@@ -967,6 +986,10 @@ unknown:
req->status = 0;
composite_setup_complete(gadget->ep0, req);
}
+ } else if (value == USB_GADGET_DELAYED_STATUS && w_length != 0) {
+ WARN(cdev,
+ "%s: Delayed status not supported for w_length != 0",
+ __func__);
}
done:
@@ -1289,3 +1312,40 @@ void usb_composite_unregister(struct usb_composite_driver *driver)
return;
usb_gadget_unregister_driver(&composite_driver);
}
+
+/**
+ * usb_composite_setup_continue() - Continue with the control transfer
+ * @cdev: the composite device who's control transfer was kept waiting
+ *
+ * This function must be called by the USB function driver to continue
+ * with the control transfer's data/status stage in case it had requested to
+ * delay the data/status stages. A USB function's setup handler (e.g. set_alt())
+ * can request the composite framework to delay the setup request's data/status
+ * stages by returning USB_GADGET_DELAYED_STATUS.
+ */
+void usb_composite_setup_continue(struct usb_composite_dev *cdev)
+{
+ int value;
+ struct usb_request *req = cdev->req;
+ unsigned long flags;
+
+ DBG(cdev, "%s\n", __func__);
+ spin_lock_irqsave(&cdev->lock, flags);
+
+ if (cdev->delayed_status == 0) {
+ WARN(cdev, "%s: Unexpected call\n", __func__);
+
+ } else if (--cdev->delayed_status == 0) {
+ DBG(cdev, "%s: Completing delayed status\n", __func__);
+ req->length = 0;
+ value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
+ if (value < 0) {
+ DBG(cdev, "ep_queue --> %d\n", value);
+ req->status = 0;
+ composite_setup_complete(cdev->gadget->ep0, req);
+ }
+ }
+
+ spin_unlock_irqrestore(&cdev->lock, flags);
+}
+
diff --git a/drivers/usb/gadget/dbgp.c b/drivers/usb/gadget/dbgp.c
index e5ac8a316fe..dbe92ee8847 100644
--- a/drivers/usb/gadget/dbgp.c
+++ b/drivers/usb/gadget/dbgp.c
@@ -261,8 +261,8 @@ static int __init dbgp_configure_endpoints(struct usb_gadget *gadget)
o_desc.wMaxPacketSize =
__constant_cpu_to_le16(USB_DEBUG_MAX_PACKET_SIZE);
- dbg_desc.bDebugInEndpoint = i_desc.bEndpointAddress & 0x7f;
- dbg_desc.bDebugOutEndpoint = o_desc.bEndpointAddress & 0x7f;
+ dbg_desc.bDebugInEndpoint = i_desc.bEndpointAddress;
+ dbg_desc.bDebugOutEndpoint = o_desc.bEndpointAddress;
#ifdef CONFIG_USB_G_DBGP_SERIAL
dbgp.serial->in = dbgp.i_ep;
@@ -312,6 +312,7 @@ static int __init dbgp_bind(struct usb_gadget *gadget)
dbgp.req->length = DBGP_REQ_EP0_LEN;
gadget->ep0->driver_data = gadget;
+ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
#ifdef CONFIG_USB_G_DBGP_SERIAL
dbgp.serial = kzalloc(sizeof(struct gserial), GFP_KERNEL);
@@ -350,9 +351,9 @@ static int dbgp_setup(struct usb_gadget *gadget,
u8 request = ctrl->bRequest;
u16 value = le16_to_cpu(ctrl->wValue);
u16 length = le16_to_cpu(ctrl->wLength);
- int err = 0;
- void *data;
- u16 len;
+ int err = -EOPNOTSUPP;
+ void *data = NULL;
+ u16 len = 0;
gadget->ep0->driver_data = gadget;
@@ -371,10 +372,9 @@ static int dbgp_setup(struct usb_gadget *gadget,
default:
goto fail;
}
+ err = 0;
} else if (request == USB_REQ_SET_FEATURE &&
value == USB_DEVICE_DEBUG_MODE) {
- len = 0;
- data = NULL;
dev_dbg(&dbgp.gadget->dev, "setup: feat debug\n");
#ifdef CONFIG_USB_G_DBGP_PRINTK
err = dbgp_enable_ep();
diff --git a/drivers/usb/gadget/dummy_hcd.c b/drivers/usb/gadget/dummy_hcd.c
index 3214ca375d6..61ff927928a 100644
--- a/drivers/usb/gadget/dummy_hcd.c
+++ b/drivers/usb/gadget/dummy_hcd.c
@@ -892,10 +892,11 @@ static int dummy_udc_probe (struct platform_device *pdev)
return rc;
}
- platform_set_drvdata (pdev, dum);
rc = device_create_file (&dum->gadget.dev, &dev_attr_function);
if (rc < 0)
device_unregister (&dum->gadget.dev);
+ else
+ platform_set_drvdata(pdev, dum);
return rc;
}
@@ -1995,11 +1996,29 @@ static int __init init (void)
retval = platform_device_add(the_hcd_pdev);
if (retval < 0)
goto err_add_hcd;
+ if (!the_controller) {
+ /*
+ * The hcd was added successfully but its probe function failed
+ * for some reason.
+ */
+ retval = -EINVAL;
+ goto err_add_udc;
+ }
retval = platform_device_add(the_udc_pdev);
if (retval < 0)
goto err_add_udc;
+ if (!platform_get_drvdata(the_udc_pdev)) {
+ /*
+ * The udc was added successfully but its probe function failed
+ * for some reason.
+ */
+ retval = -EINVAL;
+ goto err_probe_udc;
+ }
return retval;
+err_probe_udc:
+ platform_device_del(the_udc_pdev);
err_add_udc:
platform_device_del(the_hcd_pdev);
err_add_hcd:
diff --git a/drivers/usb/gadget/f_audio.c b/drivers/usb/gadget/f_audio.c
index 0111f8a9cf7..8ee330a2ab5 100644
--- a/drivers/usb/gadget/f_audio.c
+++ b/drivers/usb/gadget/f_audio.c
@@ -177,7 +177,7 @@ static struct uac_format_type_i_discrete_descriptor_1 as_type_i_desc = {
};
/* Standard ISO OUT Endpoint Descriptor */
-static struct usb_endpoint_descriptor as_out_ep_desc __initdata = {
+static struct usb_endpoint_descriptor as_out_ep_desc = {
.bLength = USB_DT_ENDPOINT_AUDIO_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_OUT,
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 6d8e533949e..efb58f9f5aa 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -347,6 +347,7 @@ struct fsg_operations {
/* Data shared by all the FSG instances. */
struct fsg_common {
struct usb_gadget *gadget;
+ struct usb_composite_dev *cdev;
struct fsg_dev *fsg, *new_fsg;
wait_queue_head_t fsg_wait;
@@ -613,6 +614,11 @@ static int fsg_setup(struct usb_function *f,
if (!fsg_is_set(fsg->common))
return -EOPNOTSUPP;
+ ++fsg->common->ep0_req_tag; /* Record arrival of a new request */
+ req->context = NULL;
+ req->length = 0;
+ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
+
switch (ctrl->bRequest) {
case USB_BULK_RESET_REQUEST:
@@ -1584,37 +1590,6 @@ static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
return rc;
}
-static int pad_with_zeros(struct fsg_dev *fsg)
-{
- struct fsg_buffhd *bh = fsg->common->next_buffhd_to_fill;
- u32 nkeep = bh->inreq->length;
- u32 nsend;
- int rc;
-
- bh->state = BUF_STATE_EMPTY; /* For the first iteration */
- fsg->common->usb_amount_left = nkeep + fsg->common->residue;
- while (fsg->common->usb_amount_left > 0) {
-
- /* Wait for the next buffer to be free */
- while (bh->state != BUF_STATE_EMPTY) {
- rc = sleep_thread(fsg->common);
- if (rc)
- return rc;
- }
-
- nsend = min(fsg->common->usb_amount_left, FSG_BUFLEN);
- memset(bh->buf + nkeep, 0, nsend - nkeep);
- bh->inreq->length = nsend;
- bh->inreq->zero = 0;
- start_transfer(fsg, fsg->bulk_in, bh->inreq,
- &bh->inreq_busy, &bh->state);
- bh = fsg->common->next_buffhd_to_fill = bh->next;
- fsg->common->usb_amount_left -= nsend;
- nkeep = 0;
- }
- return 0;
-}
-
static int throw_away_data(struct fsg_common *common)
{
struct fsg_buffhd *bh;
@@ -1702,6 +1677,10 @@ static int finish_reply(struct fsg_common *common)
if (common->data_size == 0) {
/* Nothing to send */
+ /* Don't know what to do if common->fsg is NULL */
+ } else if (!fsg_is_set(common)) {
+ rc = -EIO;
+
/* If there's no residue, simply send the last buffer */
} else if (common->residue == 0) {
bh->inreq->zero = 0;
@@ -1710,24 +1689,19 @@ static int finish_reply(struct fsg_common *common)
common->next_buffhd_to_fill = bh->next;
/*
- * For Bulk-only, if we're allowed to stall then send the
- * short packet and halt the bulk-in endpoint. If we can't
- * stall, pad out the remaining data with 0's.
+ * For Bulk-only, mark the end of the data with a short
+ * packet. If we are allowed to stall, halt the bulk-in
+ * endpoint. (Note: This violates the Bulk-Only Transport
+ * specification, which requires us to pad the data if we
+ * don't halt the endpoint. Presumably nobody will mind.)
*/
- } else if (common->can_stall) {
+ } else {
bh->inreq->zero = 1;
if (!start_in_transfer(common, bh))
- /* Don't know what to do if
- * common->fsg is NULL */
rc = -EIO;
common->next_buffhd_to_fill = bh->next;
- if (common->fsg)
+ if (common->can_stall)
rc = halt_bulk_in_endpoint(common->fsg);
- } else if (fsg_is_set(common)) {
- rc = pad_with_zeros(common->fsg);
- } else {
- /* Don't know what to do if common->fsg is NULL */
- rc = -EIO;
}
break;
@@ -1910,7 +1884,7 @@ static int check_command(struct fsg_common *common, int cmnd_size,
common->lun, lun);
/* Check the LUN */
- if (common->lun >= 0 && common->lun < common->nluns) {
+ if (common->lun < common->nluns) {
curlun = &common->luns[common->lun];
common->curlun = curlun;
if (common->cmnd[0] != REQUEST_SENSE) {
@@ -2468,7 +2442,7 @@ static int fsg_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
struct fsg_dev *fsg = fsg_from_func(f);
fsg->common->new_fsg = fsg;
raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE);
- return 0;
+ return USB_GADGET_DELAYED_STATUS;
}
static void fsg_disable(struct usb_function *f)
@@ -2604,6 +2578,8 @@ static void handle_exception(struct fsg_common *common)
case FSG_STATE_CONFIG_CHANGE:
do_set_interface(common, common->new_fsg);
+ if (common->new_fsg)
+ usb_composite_setup_continue(common->cdev);
break;
case FSG_STATE_EXIT:
@@ -2774,6 +2750,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
common->gadget = gadget;
common->ep0 = gadget->ep0;
common->ep0req = cdev->req;
+ common->cdev = cdev;
/* Maybe allocate device-global string IDs, and patch descriptors */
if (fsg_strings[FSG_STRING_INTERFACE].id == 0) {
@@ -2800,6 +2777,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
for (i = 0, lcfg = cfg->luns; i < nluns; ++i, ++curlun, ++lcfg) {
curlun->cdrom = !!lcfg->cdrom;
curlun->ro = lcfg->cdrom || lcfg->ro;
+ curlun->initially_ro = curlun->ro;
curlun->removable = lcfg->removable;
curlun->dev.release = fsg_lun_release;
curlun->dev.parent = &gadget->dev;
diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
index 882484a4039..fa12ec8364e 100644
--- a/drivers/usb/gadget/f_rndis.c
+++ b/drivers/usb/gadget/f_rndis.c
@@ -420,8 +420,7 @@ rndis_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
*/
case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_SEND_ENCAPSULATED_COMMAND:
- if (w_length > req->length || w_value
- || w_index != rndis->ctrl_id)
+ if (w_value || w_index != rndis->ctrl_id)
goto invalid;
/* read the request; process it later */
value = w_length;
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index a6eacb59571..0360f56221e 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -1947,37 +1947,6 @@ static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
return rc;
}
-static int pad_with_zeros(struct fsg_dev *fsg)
-{
- struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
- u32 nkeep = bh->inreq->length;
- u32 nsend;
- int rc;
-
- bh->state = BUF_STATE_EMPTY; // For the first iteration
- fsg->usb_amount_left = nkeep + fsg->residue;
- while (fsg->usb_amount_left > 0) {
-
- /* Wait for the next buffer to be free */
- while (bh->state != BUF_STATE_EMPTY) {
- rc = sleep_thread(fsg);
- if (rc)
- return rc;
- }
-
- nsend = min(fsg->usb_amount_left, (u32) mod_data.buflen);
- memset(bh->buf + nkeep, 0, nsend - nkeep);
- bh->inreq->length = nsend;
- bh->inreq->zero = 0;
- start_transfer(fsg, fsg->bulk_in, bh->inreq,
- &bh->inreq_busy, &bh->state);
- bh = fsg->next_buffhd_to_fill = bh->next;
- fsg->usb_amount_left -= nsend;
- nkeep = 0;
- }
- return 0;
-}
-
static int throw_away_data(struct fsg_dev *fsg)
{
struct fsg_buffhd *bh;
@@ -2082,18 +2051,20 @@ static int finish_reply(struct fsg_dev *fsg)
}
}
- /* For Bulk-only, if we're allowed to stall then send the
- * short packet and halt the bulk-in endpoint. If we can't
- * stall, pad out the remaining data with 0's. */
+ /*
+ * For Bulk-only, mark the end of the data with a short
+ * packet. If we are allowed to stall, halt the bulk-in
+ * endpoint. (Note: This violates the Bulk-Only Transport
+ * specification, which requires us to pad the data if we
+ * don't halt the endpoint. Presumably nobody will mind.)
+ */
else {
- if (mod_data.can_stall) {
- bh->inreq->zero = 1;
- start_transfer(fsg, fsg->bulk_in, bh->inreq,
- &bh->inreq_busy, &bh->state);
- fsg->next_buffhd_to_fill = bh->next;
+ bh->inreq->zero = 1;
+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
+ &bh->inreq_busy, &bh->state);
+ fsg->next_buffhd_to_fill = bh->next;
+ if (mod_data.can_stall)
rc = halt_bulk_in_endpoint(fsg);
- } else
- rc = pad_with_zeros(fsg);
}
break;
@@ -2314,7 +2285,7 @@ static int check_command(struct fsg_dev *fsg, int cmnd_size,
fsg->lun = lun; // Use LUN from the command
/* Check the LUN */
- if (fsg->lun >= 0 && fsg->lun < fsg->nluns) {
+ if (fsg->lun < fsg->nluns) {
fsg->curlun = curlun = &fsg->luns[fsg->lun];
if (fsg->cmnd[0] != REQUEST_SENSE) {
curlun->sense_data = SS_NO_SENSE;
diff --git a/drivers/usb/gadget/fsl_qe_udc.h b/drivers/usb/gadget/fsl_qe_udc.h
index e35e24fd64b..1da5fb03d21 100644
--- a/drivers/usb/gadget/fsl_qe_udc.h
+++ b/drivers/usb/gadget/fsl_qe_udc.h
@@ -207,7 +207,7 @@ struct qe_frame{
/* Frame status field */
/* Receive side */
-#define FRAME_OK 0x00000000 /* Frame tranmitted or received OK */
+#define FRAME_OK 0x00000000 /* Frame transmitted or received OK */
#define FRAME_ERROR 0x80000000 /* Error occurred on frame */
#define START_FRAME_LOST 0x40000000 /* START_FRAME_LOST */
#define END_FRAME_LOST 0x20000000 /* END_FRAME_LOST */
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 07499c1cdcc..2cd9a60c7f3 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -1,12 +1,13 @@
/*
- * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
+ * All rights reserved.
*
* Author: Li Yang <leoli@freescale.com>
* Jiang Bo <tanya.jiang@freescale.com>
*
* Description:
* Freescale high-speed USB SOC DR module device controller driver.
- * This can be found on MPC8349E/MPC8313E cpus.
+ * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
* The driver is previously named as mpc_udc. Based on bare board
* code from Dave Liu and Shlomi Gridish.
*
@@ -45,6 +46,7 @@
#include <asm/system.h>
#include <asm/unaligned.h>
#include <asm/dma.h>
+#include <asm/cacheflush.h>
#include "fsl_usb2_udc.h"
@@ -77,12 +79,64 @@ fsl_ep0_desc = {
static void fsl_ep_fifo_flush(struct usb_ep *_ep);
#ifdef CONFIG_PPC32
-#define fsl_readl(addr) in_le32(addr)
-#define fsl_writel(val32, addr) out_le32(addr, val32)
-#else
+/*
+ * On some SoCs, the USB controller registers can be big or little endian,
+ * depending on the version of the chip. In order to be able to run the
+ * same kernel binary on 2 different versions of an SoC, the BE/LE decision
+ * must be made at run time. _fsl_readl and fsl_writel are pointers to the
+ * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
+ * call through those pointers. Platform code for SoCs that have BE USB
+ * registers should set pdata->big_endian_mmio flag.
+ *
+ * This also applies to controller-to-cpu accessors for the USB descriptors,
+ * since their endianness is also SoC dependant. Platform code for SoCs that
+ * have BE USB descriptors should set pdata->big_endian_desc flag.
+ */
+static u32 _fsl_readl_be(const unsigned __iomem *p)
+{
+ return in_be32(p);
+}
+
+static u32 _fsl_readl_le(const unsigned __iomem *p)
+{
+ return in_le32(p);
+}
+
+static void _fsl_writel_be(u32 v, unsigned __iomem *p)
+{
+ out_be32(p, v);
+}
+
+static void _fsl_writel_le(u32 v, unsigned __iomem *p)
+{
+ out_le32(p, v);
+}
+
+static u32 (*_fsl_readl)(const unsigned __iomem *p);
+static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
+
+#define fsl_readl(p) (*_fsl_readl)((p))
+#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
+
+static inline u32 cpu_to_hc32(const u32 x)
+{
+ return udc_controller->pdata->big_endian_desc
+ ? (__force u32)cpu_to_be32(x)
+ : (__force u32)cpu_to_le32(x);
+}
+
+static inline u32 hc32_to_cpu(const u32 x)
+{
+ return udc_controller->pdata->big_endian_desc
+ ? be32_to_cpu((__force __be32)x)
+ : le32_to_cpu((__force __le32)x);
+}
+#else /* !CONFIG_PPC32 */
#define fsl_readl(addr) readl(addr)
#define fsl_writel(val32, addr) writel(val32, addr)
-#endif
+#define cpu_to_hc32(x) cpu_to_le32(x)
+#define hc32_to_cpu(x) le32_to_cpu(x)
+#endif /* CONFIG_PPC32 */
/********************************************************************
* Internal Used Function
@@ -177,7 +231,8 @@ static void nuke(struct fsl_ep *ep, int status)
static int dr_controller_setup(struct fsl_udc *udc)
{
- unsigned int tmp, portctrl;
+ unsigned int tmp, portctrl, ep_num;
+ unsigned int max_no_of_ep;
#ifndef CONFIG_ARCH_MXC
unsigned int ctrl;
#endif
@@ -226,9 +281,12 @@ static int dr_controller_setup(struct fsl_udc *udc)
/* Set the controller as device mode */
tmp = fsl_readl(&dr_regs->usbmode);
+ tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
tmp |= USB_MODE_CTRL_MODE_DEVICE;
/* Disable Setup Lockout */
tmp |= USB_MODE_SETUP_LOCK_OFF;
+ if (udc->pdata->es)
+ tmp |= USB_MODE_ES;
fsl_writel(tmp, &dr_regs->usbmode);
/* Clear the setup status */
@@ -242,22 +300,34 @@ static int dr_controller_setup(struct fsl_udc *udc)
udc->ep_qh, (int)tmp,
fsl_readl(&dr_regs->endpointlistaddr));
+ max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
+ for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
+ tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
+ tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
+ tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
+ | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
+ fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
+ }
/* Config control enable i/o output, cpu endian register */
#ifndef CONFIG_ARCH_MXC
- ctrl = __raw_readl(&usb_sys_regs->control);
- ctrl |= USB_CTRL_IOENB;
- __raw_writel(ctrl, &usb_sys_regs->control);
+ if (udc->pdata->have_sysif_regs) {
+ ctrl = __raw_readl(&usb_sys_regs->control);
+ ctrl |= USB_CTRL_IOENB;
+ __raw_writel(ctrl, &usb_sys_regs->control);
+ }
#endif
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
/* Turn on cache snooping hardware, since some PowerPC platforms
* wholly rely on hardware to deal with cache coherent. */
- /* Setup Snooping for all the 4GB space */
- tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
- __raw_writel(tmp, &usb_sys_regs->snoop1);
- tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
- __raw_writel(tmp, &usb_sys_regs->snoop2);
+ if (udc->pdata->have_sysif_regs) {
+ /* Setup Snooping for all the 4GB space */
+ tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
+ __raw_writel(tmp, &usb_sys_regs->snoop1);
+ tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
+ __raw_writel(tmp, &usb_sys_regs->snoop2);
+ }
#endif
return 0;
@@ -293,6 +363,19 @@ static void dr_controller_stop(struct fsl_udc *udc)
{
unsigned int tmp;
+ pr_debug("%s\n", __func__);
+
+ /* if we're in OTG mode, and the Host is currently using the port,
+ * stop now and don't rip the controller out from under the
+ * ehci driver
+ */
+ if (udc->gadget.is_otg) {
+ if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
+ pr_debug("udc: Leaving early\n");
+ return;
+ }
+ }
+
/* disable all INTR */
fsl_writel(0, &dr_regs->usbintr);
@@ -318,12 +401,14 @@ static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
if (ep_num)
tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
tmp_epctrl |= EPCTRL_TX_ENABLE;
+ tmp_epctrl &= ~EPCTRL_TX_TYPE;
tmp_epctrl |= ((unsigned int)(ep_type)
<< EPCTRL_TX_EP_TYPE_SHIFT);
} else {
if (ep_num)
tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
tmp_epctrl |= EPCTRL_RX_ENABLE;
+ tmp_epctrl &= ~EPCTRL_RX_TYPE;
tmp_epctrl |= ((unsigned int)(ep_type)
<< EPCTRL_RX_EP_TYPE_SHIFT);
}
@@ -409,7 +494,7 @@ static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
if (zlt)
tmp |= EP_QUEUE_HEAD_ZLT_SEL;
- p_QH->max_pkt_length = cpu_to_le32(tmp);
+ p_QH->max_pkt_length = cpu_to_hc32(tmp);
p_QH->next_dtd_ptr = 1;
p_QH->size_ioc_int_sts = 0;
}
@@ -546,10 +631,13 @@ static int fsl_ep_disable(struct usb_ep *_ep)
/* disable ep on controller */
ep_num = ep_index(ep);
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
- if (ep_is_in(ep))
- epctrl &= ~EPCTRL_TX_ENABLE;
- else
- epctrl &= ~EPCTRL_RX_ENABLE;
+ if (ep_is_in(ep)) {
+ epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
+ epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
+ } else {
+ epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
+ epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
+ }
fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
udc = (struct fsl_udc *)ep->udc;
@@ -616,7 +704,7 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
struct fsl_req *lastreq;
lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
lastreq->tail->next_td_ptr =
- cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
+ cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
/* Read prime bit, if 1 goto done */
if (fsl_readl(&dr_regs->endpointprime) & bitmask)
goto out;
@@ -641,10 +729,10 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
/* Write dQH next pointer and terminate bit to 0 */
temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
- dQH->next_dtd_ptr = cpu_to_le32(temp);
+ dQH->next_dtd_ptr = cpu_to_hc32(temp);
/* Clear active and halt bit */
- temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
+ temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
| EP_QUEUE_HEAD_STATUS_HALT));
dQH->size_ioc_int_sts &= temp;
@@ -682,17 +770,17 @@ static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
dtd->td_dma = *dma;
/* Clear reserved field */
- swap_temp = cpu_to_le32(dtd->size_ioc_sts);
+ swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
swap_temp &= ~DTD_RESERVED_FIELDS;
- dtd->size_ioc_sts = cpu_to_le32(swap_temp);
+ dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
/* Init all of buffer page pointers */
swap_temp = (u32) (req->req.dma + req->req.actual);
- dtd->buff_ptr0 = cpu_to_le32(swap_temp);
- dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
- dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
- dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
- dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
+ dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
+ dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
+ dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
+ dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
+ dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
req->req.actual += *length;
@@ -716,7 +804,7 @@ static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
if (*is_last && !req->req.no_interrupt)
swap_temp |= DTD_IOC;
- dtd->size_ioc_sts = cpu_to_le32(swap_temp);
+ dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
mb();
@@ -743,7 +831,7 @@ static int fsl_req_to_dtd(struct fsl_req *req)
is_first = 0;
req->head = dtd;
} else {
- last_dtd->next_td_ptr = cpu_to_le32(dma);
+ last_dtd->next_td_ptr = cpu_to_hc32(dma);
last_dtd->next_td_virt = dtd;
}
last_dtd = dtd;
@@ -751,7 +839,7 @@ static int fsl_req_to_dtd(struct fsl_req *req)
req->dtd_count++;
} while (!is_last);
- dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
+ dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
req->tail = dtd;
@@ -962,6 +1050,36 @@ out:
return status;
}
+static int fsl_ep_fifo_status(struct usb_ep *_ep)
+{
+ struct fsl_ep *ep;
+ struct fsl_udc *udc;
+ int size = 0;
+ u32 bitmask;
+ struct ep_queue_head *d_qh;
+
+ ep = container_of(_ep, struct fsl_ep, ep);
+ if (!_ep || (!ep->desc && ep_index(ep) != 0))
+ return -ENODEV;
+
+ udc = (struct fsl_udc *)ep->udc;
+
+ if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
+
+ bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
+ (1 << (ep_index(ep)));
+
+ if (fsl_readl(&dr_regs->endptstatus) & bitmask)
+ size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
+ >> DTD_LENGTH_BIT_POS;
+
+ pr_debug("%s %u\n", __func__, size);
+ return size;
+}
+
static void fsl_ep_fifo_flush(struct usb_ep *_ep)
{
struct fsl_ep *ep;
@@ -1014,6 +1132,7 @@ static struct usb_ep_ops fsl_ep_ops = {
.dequeue = fsl_ep_dequeue,
.set_halt = fsl_ep_set_halt,
+ .fifo_status = fsl_ep_fifo_status,
.fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
};
@@ -1228,6 +1347,10 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
req = udc->status_req;
/* Fill in the reqest structure */
*((u16 *) req->req.buf) = cpu_to_le16(tmp);
+
+ /* flush cache for the req buffer */
+ flush_dcache_range((u32)req->req.buf, (u32)req->req.buf + 8);
+
req->ep = ep;
req->req.length = 2;
req->req.status = -EINPROGRESS;
@@ -1280,6 +1403,7 @@ static void setup_received_irq(struct fsl_udc *udc,
/* Status phase from udc */
{
int rc = -EOPNOTSUPP;
+ u16 ptc = 0;
if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
== (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
@@ -1301,17 +1425,19 @@ static void setup_received_irq(struct fsl_udc *udc,
| USB_TYPE_STANDARD)) {
/* Note: The driver has not include OTG support yet.
* This will be set when OTG support is added */
- if (!gadget_is_otg(&udc->gadget))
- break;
- else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
- udc->gadget.b_hnp_enable = 1;
- else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
- udc->gadget.a_hnp_support = 1;
- else if (setup->bRequest ==
- USB_DEVICE_A_ALT_HNP_SUPPORT)
- udc->gadget.a_alt_hnp_support = 1;
- else
- break;
+ if (wValue == USB_DEVICE_TEST_MODE)
+ ptc = wIndex >> 8;
+ else if (gadget_is_otg(&udc->gadget)) {
+ if (setup->bRequest ==
+ USB_DEVICE_B_HNP_ENABLE)
+ udc->gadget.b_hnp_enable = 1;
+ else if (setup->bRequest ==
+ USB_DEVICE_A_HNP_SUPPORT)
+ udc->gadget.a_hnp_support = 1;
+ else if (setup->bRequest ==
+ USB_DEVICE_A_ALT_HNP_SUPPORT)
+ udc->gadget.a_alt_hnp_support = 1;
+ }
rc = 0;
} else
break;
@@ -1320,6 +1446,15 @@ static void setup_received_irq(struct fsl_udc *udc,
if (ep0_prime_status(udc, EP_DIR_IN))
ep0stall(udc);
}
+ if (ptc) {
+ u32 tmp;
+
+ mdelay(10);
+ tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
+ fsl_writel(tmp, &dr_regs->portsc1);
+ printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
+ }
+
return;
}
@@ -1394,6 +1529,7 @@ static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
{
u32 temp;
struct ep_queue_head *qh;
+ struct fsl_usb2_platform_data *pdata = udc->pdata;
qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
@@ -1408,7 +1544,16 @@ static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
/* Copy the setup packet to local buffer */
- memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
+ if (pdata->le_setup_buf) {
+ u32 *p = (u32 *)buffer_ptr;
+ u32 *s = (u32 *)qh->setup_buffer;
+
+ /* Convert little endian setup buffer to CPU endian */
+ *p++ = le32_to_cpu(*s++);
+ *p = le32_to_cpu(*s);
+ } else {
+ memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
+ }
} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
/* Clear Setup Tripwire */
@@ -1432,19 +1577,19 @@ static int process_ep_req(struct fsl_udc *udc, int pipe,
actual = curr_req->req.length;
for (j = 0; j < curr_req->dtd_count; j++) {
- remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
+ remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
& DTD_PACKET_SIZE)
>> DTD_LENGTH_BIT_POS;
actual -= remaining_length;
- if ((errors = le32_to_cpu(curr_td->size_ioc_sts) &
- DTD_ERROR_MASK)) {
+ errors = hc32_to_cpu(curr_td->size_ioc_sts);
+ if (errors & DTD_ERROR_MASK) {
if (errors & DTD_STATUS_HALTED) {
ERR("dTD error %08x QH=%d\n", errors, pipe);
/* Clear the errors and Halt condition */
- tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
+ tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
tmp &= ~errors;
- curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
+ curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
status = -EPIPE;
/* FIXME: continue with next queued TD? */
@@ -1462,7 +1607,7 @@ static int process_ep_req(struct fsl_udc *udc, int pipe,
ERR("Unknown error has occurred (0x%x)!\n",
errors);
- } else if (le32_to_cpu(curr_td->size_ioc_sts)
+ } else if (hc32_to_cpu(curr_td->size_ioc_sts)
& DTD_STATUS_ACTIVE) {
VDBG("Request not complete");
status = REQ_UNCOMPLETE;
@@ -1551,6 +1696,9 @@ static void port_change_irq(struct fsl_udc *udc)
{
u32 speed;
+ if (udc->bus_reset)
+ udc->bus_reset = 0;
+
/* Bus resetting is finished */
if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
/* Get the speed */
@@ -1658,6 +1806,8 @@ static void reset_irq(struct fsl_udc *udc)
if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
VDBG("Bus reset");
+ /* Bus is reseting */
+ udc->bus_reset = 1;
/* Reset all the queues, include XD, dTD, EP queue
* head and TR Queue */
reset_queues(udc);
@@ -1735,6 +1885,7 @@ static irqreturn_t fsl_udc_irq(int irq, void *_udc)
/* Reset Received */
if (irq_src & USB_STS_RESET) {
+ VDBG("reset int");
reset_irq(udc);
status = IRQ_HANDLED;
}
@@ -1792,11 +1943,30 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
goto out;
}
- /* Enable DR IRQ reg and Set usbcmd reg Run bit */
- dr_controller_run(udc_controller);
- udc_controller->usb_state = USB_STATE_ATTACHED;
- udc_controller->ep0_state = WAIT_FOR_SETUP;
- udc_controller->ep0_dir = 0;
+ if (udc_controller->transceiver) {
+ /* Suspend the controller until OTG enable it */
+ udc_controller->stopped = 1;
+ printk(KERN_INFO "Suspend udc for OTG auto detect\n");
+
+ /* connect to bus through transceiver */
+ if (udc_controller->transceiver) {
+ retval = otg_set_peripheral(udc_controller->transceiver,
+ &udc_controller->gadget);
+ if (retval < 0) {
+ ERR("can't bind to transceiver\n");
+ driver->unbind(&udc_controller->gadget);
+ udc_controller->gadget.dev.driver = 0;
+ udc_controller->driver = 0;
+ return retval;
+ }
+ }
+ } else {
+ /* Enable DR IRQ reg and set USBCMD reg Run bit */
+ dr_controller_run(udc_controller);
+ udc_controller->usb_state = USB_STATE_ATTACHED;
+ udc_controller->ep0_state = WAIT_FOR_SETUP;
+ udc_controller->ep0_dir = 0;
+ }
printk(KERN_INFO "%s: bind to driver %s\n",
udc_controller->gadget.name, driver->driver.name);
@@ -2044,16 +2214,18 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
next += t;
#ifndef CONFIG_ARCH_MXC
- tmp_reg = usb_sys_regs->snoop1;
- t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
- size -= t;
- next += t;
+ if (udc->pdata->have_sysif_regs) {
+ tmp_reg = usb_sys_regs->snoop1;
+ t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
+ size -= t;
+ next += t;
- tmp_reg = usb_sys_regs->control;
- t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
- tmp_reg);
- size -= t;
- next += t;
+ tmp_reg = usb_sys_regs->control;
+ t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
+ tmp_reg);
+ size -= t;
+ next += t;
+ }
#endif
/* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
@@ -2233,6 +2405,7 @@ static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
*/
static int __init fsl_udc_probe(struct platform_device *pdev)
{
+ struct fsl_usb2_platform_data *pdata;
struct resource *res;
int ret = -ENODEV;
unsigned int i;
@@ -2249,20 +2422,35 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ pdata = pdev->dev.platform_data;
+ udc_controller->pdata = pdata;
spin_lock_init(&udc_controller->lock);
udc_controller->stopped = 1;
+#ifdef CONFIG_USB_OTG
+ if (pdata->operating_mode == FSL_USB2_DR_OTG) {
+ udc_controller->transceiver = otg_get_transceiver();
+ if (!udc_controller->transceiver) {
+ ERR("Can't find OTG driver!\n");
+ ret = -ENODEV;
+ goto err_kfree;
+ }
+ }
+#endif
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENXIO;
goto err_kfree;
}
- if (!request_mem_region(res->start, res->end - res->start + 1,
- driver_name)) {
- ERR("request mem region for %s failed\n", pdev->name);
- ret = -EBUSY;
- goto err_kfree;
+ if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
+ if (!request_mem_region(res->start, res->end - res->start + 1,
+ driver_name)) {
+ ERR("request mem region for %s failed\n", pdev->name);
+ ret = -EBUSY;
+ goto err_kfree;
+ }
}
dr_regs = ioremap(res->start, resource_size(res));
@@ -2271,9 +2459,29 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
goto err_release_mem_region;
}
+ pdata->regs = (void *)dr_regs;
+
+ /*
+ * do platform specific init: check the clock, grab/config pins, etc.
+ */
+ if (pdata->init && pdata->init(pdev)) {
+ ret = -ENODEV;
+ goto err_iounmap_noclk;
+ }
+
+ /* Set accessors only after pdata->init() ! */
+ if (pdata->big_endian_mmio) {
+ _fsl_readl = _fsl_readl_be;
+ _fsl_writel = _fsl_writel_be;
+ } else {
+ _fsl_readl = _fsl_readl_le;
+ _fsl_writel = _fsl_writel_le;
+ }
+
#ifndef CONFIG_ARCH_MXC
- usb_sys_regs = (struct usb_sys_interface *)
- ((u32)dr_regs + USB_DR_SYS_OFFSET);
+ if (pdata->have_sysif_regs)
+ usb_sys_regs = (struct usb_sys_interface *)
+ ((u32)dr_regs + USB_DR_SYS_OFFSET);
#endif
/* Initialize USB clocks */
@@ -2313,9 +2521,11 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
goto err_free_irq;
}
- /* initialize usb hw reg except for regs for EP,
- * leave usbintr reg untouched */
- dr_controller_setup(udc_controller);
+ if (!udc_controller->transceiver) {
+ /* initialize usb hw reg except for regs for EP,
+ * leave usbintr reg untouched */
+ dr_controller_setup(udc_controller);
+ }
fsl_udc_clk_finalize(pdev);
@@ -2335,6 +2545,9 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
if (ret < 0)
goto err_free_irq;
+ if (udc_controller->transceiver)
+ udc_controller->gadget.is_otg = 1;
+
/* setup QH and epctrl for ep0 */
ep0_setup(udc_controller);
@@ -2373,11 +2586,14 @@ err_unregister:
err_free_irq:
free_irq(udc_controller->irq, udc_controller);
err_iounmap:
+ if (pdata->exit)
+ pdata->exit(pdev);
fsl_udc_clk_release();
err_iounmap_noclk:
iounmap(dr_regs);
err_release_mem_region:
- release_mem_region(res->start, res->end - res->start + 1);
+ if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
+ release_mem_region(res->start, res->end - res->start + 1);
err_kfree:
kfree(udc_controller);
udc_controller = NULL;
@@ -2390,6 +2606,7 @@ err_kfree:
static int __exit fsl_udc_remove(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
DECLARE_COMPLETION(done);
@@ -2410,12 +2627,20 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
dma_pool_destroy(udc_controller->td_pool);
free_irq(udc_controller->irq, udc_controller);
iounmap(dr_regs);
- release_mem_region(res->start, res->end - res->start + 1);
+ if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
+ release_mem_region(res->start, res->end - res->start + 1);
device_unregister(&udc_controller->gadget.dev);
/* free udc --wait for the release() finished */
wait_for_completion(&done);
+ /*
+ * do platform specific un-initialization:
+ * release iomux pins, etc.
+ */
+ if (pdata->exit)
+ pdata->exit(pdev);
+
return 0;
}
@@ -2446,6 +2671,62 @@ static int fsl_udc_resume(struct platform_device *pdev)
return 0;
}
+static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
+{
+ struct fsl_udc *udc = udc_controller;
+ u32 mode, usbcmd;
+
+ mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
+
+ pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
+
+ /*
+ * If the controller is already stopped, then this must be a
+ * PM suspend. Remember this fact, so that we will leave the
+ * controller stopped at PM resume time.
+ */
+ if (udc->stopped) {
+ pr_debug("gadget already stopped, leaving early\n");
+ udc->already_stopped = 1;
+ return 0;
+ }
+
+ if (mode != USB_MODE_CTRL_MODE_DEVICE) {
+ pr_debug("gadget not in device mode, leaving early\n");
+ return 0;
+ }
+
+ /* stop the controller */
+ usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
+ fsl_writel(usbcmd, &dr_regs->usbcmd);
+
+ udc->stopped = 1;
+
+ pr_info("USB Gadget suspended\n");
+
+ return 0;
+}
+
+static int fsl_udc_otg_resume(struct device *dev)
+{
+ pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
+ udc_controller->stopped, udc_controller->already_stopped);
+
+ /*
+ * If the controller was stopped at suspend time, then
+ * don't resume it now.
+ */
+ if (udc_controller->already_stopped) {
+ udc_controller->already_stopped = 0;
+ pr_debug("gadget was already stopped, leaving early\n");
+ return 0;
+ }
+
+ pr_info("USB Gadget resume\n");
+
+ return fsl_udc_resume(NULL);
+}
+
/*-------------------------------------------------------------------------
Register entry point for the peripheral controller driver
--------------------------------------------------------------------------*/
@@ -2458,6 +2739,9 @@ static struct platform_driver udc_driver = {
.driver = {
.name = (char *)driver_name,
.owner = THIS_MODULE,
+ /* udc suspend/resume called from OTG driver */
+ .suspend = fsl_udc_otg_suspend,
+ .resume = fsl_udc_otg_resume,
},
};
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index e88cce5c2c0..1d51be83fda 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -275,7 +275,9 @@ struct usb_sys_interface {
#define USB_MODE_CTRL_MODE_IDLE 0x00000000
#define USB_MODE_CTRL_MODE_DEVICE 0x00000002
#define USB_MODE_CTRL_MODE_HOST 0x00000003
+#define USB_MODE_CTRL_MODE_MASK 0x00000003
#define USB_MODE_CTRL_MODE_RSV 0x00000001
+#define USB_MODE_ES 0x00000004 /* Endian Select */
#define USB_MODE_SETUP_LOCK_OFF 0x00000008
#define USB_MODE_STREAM_DISABLE 0x00000010
/* Endpoint Flush Register */
@@ -461,6 +463,7 @@ struct fsl_ep {
struct fsl_udc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
+ struct fsl_usb2_platform_data *pdata;
struct completion *done; /* to make sure release() is done */
struct fsl_ep *eps;
unsigned int max_ep;
@@ -473,6 +476,8 @@ struct fsl_udc {
unsigned vbus_active:1;
unsigned stopped:1;
unsigned remote_wakeup:1;
+ unsigned already_stopped:1;
+ unsigned big_endian_desc:1;
struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
struct fsl_req *status_req; /* ep0 status request */
@@ -483,6 +488,7 @@ struct fsl_udc {
dma_addr_t ep_qh_dma; /* dma address of QH */
u32 max_pipes; /* Device max pipes */
+ u32 bus_reset; /* Device is bus resetting */
u32 resume_state; /* USB state to resume */
u32 usb_state; /* USB current state */
u32 ep0_state; /* Endpoint zero state */
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index e896f6359df..bcdac7c73e8 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -136,6 +136,12 @@
#define gadget_is_s3c_hsotg(g) 0
#endif
+#ifdef CONFIG_USB_S3C_HSUDC
+#define gadget_is_s3c_hsudc(g) (!strcmp("s3c-hsudc", (g)->name))
+#else
+#define gadget_is_s3c_hsudc(g) 0
+#endif
+
#ifdef CONFIG_USB_GADGET_EG20T
#define gadget_is_pch(g) (!strcmp("pch_udc", (g)->name))
#else
@@ -148,6 +154,12 @@
#define gadget_is_ci13xxx_msm(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_RENESAS_USBHS
+#define gadget_is_renesas_usbhs(g) (!strcmp("renesas_usbhs_udc", (g)->name))
+#else
+#define gadget_is_renesas_usbhs(g) 0
+#endif
+
/**
* usb_gadget_controller_number - support bcdDevice id convention
* @gadget: the controller being driven
@@ -207,6 +219,11 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
return 0x27;
else if (gadget_is_ci13xxx_msm(gadget))
return 0x28;
+ else if (gadget_is_renesas_usbhs(gadget))
+ return 0x29;
+ else if (gadget_is_s3c_hsudc(gadget))
+ return 0x30;
+
return -ENOENT;
}
diff --git a/drivers/usb/gadget/printer.c b/drivers/usb/gadget/printer.c
index c3f2bd42bd5..271ef94668e 100644
--- a/drivers/usb/gadget/printer.c
+++ b/drivers/usb/gadget/printer.c
@@ -1189,6 +1189,8 @@ printer_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
else if (gadget->a_alt_hnp_support)
DBG(dev, "HNP needs a different root port\n");
value = printer_set_config(dev, wValue);
+ if (!value)
+ value = set_interface(dev, PRINTER_INTERFACE);
break;
case USB_REQ_GET_CONFIGURATION:
if (ctrl->bRequestType != USB_DIR_IN)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 0912679de99..acb9cc418df 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -1,5 +1,8 @@
/* linux/drivers/usb/gadget/s3c-hsotg.c
*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
@@ -613,11 +616,10 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
} else {
maxsize = 64+64;
- if (hs_ep->dir_in) {
+ if (hs_ep->dir_in)
maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
- } else {
+ else
maxpkt = 2;
- }
}
/* we made the constant loading easier above by using +1 */
@@ -679,6 +681,14 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
__func__, readl(hsotg->regs + epctrl_reg), index,
hs_ep->dir_in ? "in" : "out");
+ /* If endpoint is stalled, we will restart request later */
+ ctrl = readl(hsotg->regs + epctrl_reg);
+
+ if (ctrl & S3C_DxEPCTL_Stall) {
+ dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
+ return;
+ }
+
length = ureq->length - ureq->actual;
if (0)
@@ -731,18 +741,6 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
/* write size / packets */
writel(epsize, hsotg->regs + epsize_reg);
- ctrl = readl(hsotg->regs + epctrl_reg);
-
- if (ctrl & S3C_DxEPCTL_Stall) {
- dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
-
- /* not sure what we can do here, if it is EP0 then we should
- * get this cleared once the endpoint has transmitted the
- * STALL packet, otherwise it needs to be cleared by the
- * host.
- */
- }
-
if (using_dma(hsotg)) {
unsigned int dma_reg;
@@ -1048,6 +1046,20 @@ static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
/**
+ * get_ep_head - return the first request on the endpoint
+ * @hs_ep: The controller endpoint to get
+ *
+ * Get the first request on the endpoint.
+ */
+static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
+{
+ if (list_empty(&hs_ep->queue))
+ return NULL;
+
+ return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
+}
+
+/**
* s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
* @hsotg: The device state
* @ctrl: USB control request
@@ -1055,8 +1067,12 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
struct usb_ctrlrequest *ctrl)
{
+ struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
+ struct s3c_hsotg_req *hs_req;
+ bool restart;
bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
struct s3c_hsotg_ep *ep;
+ int ret;
dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
__func__, set ? "SET" : "CLEAR");
@@ -1072,6 +1088,36 @@ static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
switch (le16_to_cpu(ctrl->wValue)) {
case USB_ENDPOINT_HALT:
s3c_hsotg_ep_sethalt(&ep->ep, set);
+
+ ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
+ if (ret) {
+ dev_err(hsotg->dev,
+ "%s: failed to send reply\n", __func__);
+ return ret;
+ }
+
+ if (!set) {
+ /*
+ * If we have request in progress,
+ * then complete it
+ */
+ if (ep->req) {
+ hs_req = ep->req;
+ ep->req = NULL;
+ list_del_init(&hs_req->queue);
+ hs_req->req.complete(&ep->ep,
+ &hs_req->req);
+ }
+
+ /* If we have pending request, then start it */
+ restart = !list_empty(&ep->queue);
+ if (restart) {
+ hs_req = get_ep_head(ep);
+ s3c_hsotg_start_req(hsotg, ep,
+ hs_req, false);
+ }
+ }
+
break;
default:
@@ -1148,14 +1194,6 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
}
- if (ret > 0) {
- if (!ep0->dir_in) {
- /* need to generate zlp in reply or take data */
- /* todo - deal with any data we might be sent? */
- ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
- }
- }
-
/* the request is either unhandlable, or is not formatted correctly
* so respond with a STALL for the status stage to indicate failure.
*/
@@ -1247,20 +1285,6 @@ static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
}
/**
- * get_ep_head - return the first request on the endpoint
- * @hs_ep: The controller endpoint to get
- *
- * Get the first request on the endpoint.
-*/
-static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
-{
- if (list_empty(&hs_ep->queue))
- return NULL;
-
- return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
-}
-
-/**
* s3c_hsotg_complete_request - complete a request given to us
* @hsotg: The device state.
* @hs_ep: The endpoint the request was on.
@@ -1683,6 +1707,37 @@ bad_mps:
dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
}
+/**
+ * s3c_hsotg_txfifo_flush - flush Tx FIFO
+ * @hsotg: The driver state
+ * @idx: The index for the endpoint (0..15)
+ */
+static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
+{
+ int timeout;
+ int val;
+
+ writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh,
+ hsotg->regs + S3C_GRSTCTL);
+
+ /* wait until the fifo is flushed */
+ timeout = 100;
+
+ while (1) {
+ val = readl(hsotg->regs + S3C_GRSTCTL);
+
+ if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0)
+ break;
+
+ if (--timeout == 0) {
+ dev_err(hsotg->dev,
+ "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
+ __func__, val);
+ }
+
+ udelay(1);
+ }
+}
/**
* s3c_hsotg_trytx - check to see if anything needs transmitting
@@ -1775,10 +1830,12 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
u32 ints;
- u32 clear = 0;
ints = readl(hsotg->regs + epint_reg);
+ /* Clear endpoint interrupts */
+ writel(ints, hsotg->regs + epint_reg);
+
dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
__func__, idx, dir_in ? "in" : "out", ints);
@@ -1801,19 +1858,28 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
s3c_hsotg_handle_outdone(hsotg, idx, false);
}
-
- clear |= S3C_DxEPINT_XferCompl;
}
if (ints & S3C_DxEPINT_EPDisbld) {
dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
- clear |= S3C_DxEPINT_EPDisbld;
+
+ if (dir_in) {
+ int epctl = readl(hsotg->regs + epctl_reg);
+
+ s3c_hsotg_txfifo_flush(hsotg, idx);
+
+ if ((epctl & S3C_DxEPCTL_Stall) &&
+ (epctl & S3C_DxEPCTL_EPType_Bulk)) {
+ int dctl = readl(hsotg->regs + S3C_DCTL);
+
+ dctl |= S3C_DCTL_CGNPInNAK;
+ writel(dctl, hsotg->regs + S3C_DCTL);
+ }
+ }
}
- if (ints & S3C_DxEPINT_AHBErr) {
+ if (ints & S3C_DxEPINT_AHBErr)
dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
- clear |= S3C_DxEPINT_AHBErr;
- }
if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
@@ -1829,14 +1895,10 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
else
s3c_hsotg_handle_outdone(hsotg, 0, true);
}
-
- clear |= S3C_DxEPINT_Setup;
}
- if (ints & S3C_DxEPINT_Back2BackSetup) {
+ if (ints & S3C_DxEPINT_Back2BackSetup)
dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
- clear |= S3C_DxEPINT_Back2BackSetup;
- }
if (dir_in) {
/* not sure if this is important, but we'll clear it anyway
@@ -1844,14 +1906,12 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
__func__, idx);
- clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
}
/* this probably means something bad is happening */
if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
__func__, idx);
- clear |= S3C_DIEPMSK_INTknEPMisMsk;
}
/* FIFO has space or is empty (see GAHBCFG) */
@@ -1860,11 +1920,8 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
__func__, idx);
s3c_hsotg_trytx(hsotg, hs_ep);
- clear |= S3C_DIEPMSK_TxFIFOEmpty;
}
}
-
- writel(clear, hsotg->regs + epint_reg);
}
/**
@@ -2056,7 +2113,6 @@ irq_retry:
dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
writel(otgint, hsotg->regs + S3C_GOTGINT);
- writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_DisconnInt) {
@@ -2072,8 +2128,9 @@ irq_retry:
}
if (gintsts & S3C_GINTSTS_EnumDone) {
- s3c_hsotg_irq_enumdone(hsotg);
writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_irq_enumdone(hsotg);
}
if (gintsts & S3C_GINTSTS_ConIDStsChng) {
@@ -2101,10 +2158,6 @@ irq_retry:
if (daint_in & 1)
s3c_hsotg_epint(hsotg, ep, 1);
}
-
- writel(daint, hsotg->regs + S3C_DAINT);
- writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
- hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_USBRst) {
@@ -2112,6 +2165,8 @@ irq_retry:
dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
readl(hsotg->regs + S3C_GNPTXSTS));
+ writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
+
kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
/* it seems after a reset we can end up with a situation
@@ -2123,8 +2178,6 @@ irq_retry:
s3c_hsotg_init_fifo(hsotg);
s3c_hsotg_enqueue_setup(hsotg);
-
- writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
}
/* check both FIFOs */
@@ -2138,8 +2191,6 @@ irq_retry:
s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
s3c_hsotg_irq_fifoempty(hsotg, false);
-
- writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_PTxFEmp) {
@@ -2149,8 +2200,6 @@ irq_retry:
s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
s3c_hsotg_irq_fifoempty(hsotg, true);
-
- writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_RxFLvl) {
@@ -2159,7 +2208,6 @@ irq_retry:
* set. */
s3c_hsotg_handle_rx(hsotg);
- writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_ModeMis) {
@@ -2193,19 +2241,17 @@ irq_retry:
if (gintsts & S3C_GINTSTS_GOUTNakEff) {
dev_info(hsotg->dev, "GOUTNakEff triggered\n");
- s3c_hsotg_dump(hsotg);
-
writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
- writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_dump(hsotg);
}
if (gintsts & S3C_GINTSTS_GINNakEff) {
dev_info(hsotg->dev, "GINNakEff triggered\n");
- s3c_hsotg_dump(hsotg);
-
writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
- writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_dump(hsotg);
}
/* if we've had fifo events, we should try and go around the
@@ -2403,11 +2449,6 @@ static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
- if (hs_req == hs_ep->req) {
- dev_dbg(hs->dev, "%s: already in progress\n", __func__);
- return -EINPROGRESS;
- }
-
spin_lock_irqsave(&hs_ep->lock, flags);
if (!on_list(hs_ep, hs_req)) {
@@ -2429,6 +2470,7 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
unsigned long irqflags;
u32 epreg;
u32 epctl;
+ u32 xfertype;
dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
@@ -2439,10 +2481,17 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
epreg = S3C_DIEPCTL(index);
epctl = readl(hs->regs + epreg);
- if (value)
- epctl |= S3C_DxEPCTL_Stall;
- else
+ if (value) {
+ epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK;
+ if (epctl & S3C_DxEPCTL_EPEna)
+ epctl |= S3C_DxEPCTL_EPDis;
+ } else {
epctl &= ~S3C_DxEPCTL_Stall;
+ xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
+ if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
+ xfertype == S3C_DxEPCTL_EPType_Intterupt)
+ epctl |= S3C_DxEPCTL_SetD0PID;
+ }
writel(epctl, hs->regs + epreg);
@@ -2451,8 +2500,13 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
if (value)
epctl |= S3C_DxEPCTL_Stall;
- else
+ else {
epctl &= ~S3C_DxEPCTL_Stall;
+ xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
+ if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
+ xfertype == S3C_DxEPCTL_EPType_Intterupt)
+ epctl |= S3C_DxEPCTL_SetD0PID;
+ }
writel(epctl, hs->regs + epreg);
@@ -2491,9 +2545,9 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
timeout = 1000;
do {
grstctl = readl(hsotg->regs + S3C_GRSTCTL);
- } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
+ } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
- if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
+ if (grstctl & S3C_GRSTCTL_CSftRst) {
dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
return -EINVAL;
}
@@ -2510,13 +2564,10 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
return -ETIMEDOUT;
}
- if (grstctl & S3C_GRSTCTL_CSftRst)
- continue;
-
if (!(grstctl & S3C_GRSTCTL_AHBIdle))
continue;
- break; /* reset done */
+ break; /* reset done */
}
dev_dbg(hsotg->dev, "reset successful\n");
@@ -2588,6 +2639,12 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
+ /* Clear any pending OTG interrupts */
+ writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
+
+ /* Clear any pending interrupts */
+ writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
+
writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
@@ -3261,7 +3318,7 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
hsotg->clk = clk_get(&pdev->dev, "otg");
if (IS_ERR(hsotg->clk)) {
dev_err(dev, "cannot get otg clock\n");
- ret = -EINVAL;
+ ret = PTR_ERR(hsotg->clk);
goto err_mem;
}
diff --git a/drivers/usb/gadget/s3c-hsudc.c b/drivers/usb/gadget/s3c-hsudc.c
new file mode 100644
index 00000000000..cfe3cf56d6b
--- /dev/null
+++ b/drivers/usb/gadget/s3c-hsudc.c
@@ -0,0 +1,1349 @@
+/* linux/drivers/usb/gadget/s3c-hsudc.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S3C24XX USB 2.0 High-speed USB controller gadget driver
+ *
+ * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
+ * Each endpoint can be configured as either in or out endpoint. Endpoints
+ * can be configured for Bulk or Interrupt transfer mode.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <mach/regs-s3c2443-clock.h>
+#include <plat/udc.h>
+
+#define S3C_HSUDC_REG(x) (x)
+
+/* Non-Indexed Registers */
+#define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
+#define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
+#define S3C_EIR_EP0 (1<<0)
+#define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
+#define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
+#define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
+#define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
+#define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
+#define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
+#define S3C_SSR_DTZIEN_EN (0xff8f)
+#define S3C_SSR_ERR (0xff80)
+#define S3C_SSR_VBUSON (1 << 8)
+#define S3C_SSR_HSP (1 << 4)
+#define S3C_SSR_SDE (1 << 3)
+#define S3C_SSR_RESUME (1 << 2)
+#define S3C_SSR_SUSPEND (1 << 1)
+#define S3C_SSR_RESET (1 << 0)
+#define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
+#define S3C_SCR_DTZIEN_EN (1 << 14)
+#define S3C_SCR_RRD_EN (1 << 5)
+#define S3C_SCR_SUS_EN (1 << 1)
+#define S3C_SCR_RST_EN (1 << 0)
+#define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
+#define S3C_EP0SR_EP0_LWO (1 << 6)
+#define S3C_EP0SR_STALL (1 << 4)
+#define S3C_EP0SR_TX_SUCCESS (1 << 1)
+#define S3C_EP0SR_RX_SUCCESS (1 << 0)
+#define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
+#define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
+
+/* Indexed Registers */
+#define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
+#define S3C_ESR_FLUSH (1 << 6)
+#define S3C_ESR_STALL (1 << 5)
+#define S3C_ESR_LWO (1 << 4)
+#define S3C_ESR_PSIF_ONE (1 << 2)
+#define S3C_ESR_PSIF_TWO (2 << 2)
+#define S3C_ESR_TX_SUCCESS (1 << 1)
+#define S3C_ESR_RX_SUCCESS (1 << 0)
+#define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
+#define S3C_ECR_DUEN (1 << 7)
+#define S3C_ECR_FLUSH (1 << 6)
+#define S3C_ECR_STALL (1 << 1)
+#define S3C_ECR_IEMS (1 << 0)
+#define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
+#define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
+#define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
+
+#define WAIT_FOR_SETUP (0)
+#define DATA_STATE_XMIT (1)
+#define DATA_STATE_RECV (2)
+
+/**
+ * struct s3c_hsudc_ep - Endpoint representation used by driver.
+ * @ep: USB gadget layer representation of device endpoint.
+ * @name: Endpoint name (as required by ep autoconfiguration).
+ * @dev: Reference to the device controller to which this EP belongs.
+ * @desc: Endpoint descriptor obtained from the gadget driver.
+ * @queue: Transfer request queue for the endpoint.
+ * @stopped: Maintains state of endpoint, set if EP is halted.
+ * @bEndpointAddress: EP address (including direction bit).
+ * @fifo: Base address of EP FIFO.
+ */
+struct s3c_hsudc_ep {
+ struct usb_ep ep;
+ char name[20];
+ struct s3c_hsudc *dev;
+ const struct usb_endpoint_descriptor *desc;
+ struct list_head queue;
+ u8 stopped;
+ u8 wedge;
+ u8 bEndpointAddress;
+ void __iomem *fifo;
+};
+
+/**
+ * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
+ * @req: Reference to USB gadget transfer request.
+ * @queue: Used for inserting this request to the endpoint request queue.
+ */
+struct s3c_hsudc_req {
+ struct usb_request req;
+ struct list_head queue;
+};
+
+/**
+ * struct s3c_hsudc - Driver's abstraction of the device controller.
+ * @gadget: Instance of usb_gadget which is referenced by gadget driver.
+ * @driver: Reference to currenty active gadget driver.
+ * @dev: The device reference used by probe function.
+ * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
+ * @regs: Remapped base address of controller's register space.
+ * @mem_rsrc: Device memory resource used for remapping device register space.
+ * irq: IRQ number used by the controller.
+ * uclk: Reference to the controller clock.
+ * ep0state: Current state of EP0.
+ * ep: List of endpoints supported by the controller.
+ */
+struct s3c_hsudc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct device *dev;
+ struct s3c24xx_hsudc_platdata *pd;
+ spinlock_t lock;
+ void __iomem *regs;
+ struct resource *mem_rsrc;
+ int irq;
+ struct clk *uclk;
+ int ep0state;
+ struct s3c_hsudc_ep ep[];
+};
+
+#define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
+#define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
+#define ep_index(_ep) ((_ep)->bEndpointAddress & \
+ USB_ENDPOINT_NUMBER_MASK)
+
+static struct s3c_hsudc *the_controller;
+static const char driver_name[] = "s3c-udc";
+static const char ep0name[] = "ep0-control";
+
+static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
+{
+ return container_of(req, struct s3c_hsudc_req, req);
+}
+
+static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
+{
+ return container_of(ep, struct s3c_hsudc_ep, ep);
+}
+
+static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
+{
+ return container_of(gadget, struct s3c_hsudc, gadget);
+}
+
+static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
+{
+ ep_addr &= USB_ENDPOINT_NUMBER_MASK;
+ writel(ep_addr, hsudc->regs + S3C_IR);
+}
+
+static inline void __orr32(void __iomem *ptr, u32 val)
+{
+ writel(readl(ptr) | val, ptr);
+}
+
+static void s3c_hsudc_init_phy(void)
+{
+ u32 cfg;
+
+ cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
+ writel(cfg, S3C2443_PWRCFG);
+
+ cfg = readl(S3C2443_URSTCON);
+ cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
+ writel(cfg, S3C2443_URSTCON);
+ mdelay(1);
+
+ cfg = readl(S3C2443_URSTCON);
+ cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
+ writel(cfg, S3C2443_URSTCON);
+
+ cfg = readl(S3C2443_PHYCTRL);
+ cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
+ cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
+ writel(cfg, S3C2443_PHYCTRL);
+
+ cfg = readl(S3C2443_PHYPWR);
+ cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
+ S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
+ S3C2443_PHYPWR_ANALOG_PD);
+ cfg |= S3C2443_PHYPWR_COMMON_ON;
+ writel(cfg, S3C2443_PHYPWR);
+
+ cfg = readl(S3C2443_UCLKCON);
+ cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
+ S3C2443_UCLKCON_TCLKEN);
+ writel(cfg, S3C2443_UCLKCON);
+}
+
+static void s3c_hsudc_uninit_phy(void)
+{
+ u32 cfg;
+
+ cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
+ writel(cfg, S3C2443_PWRCFG);
+
+ writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
+
+ cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
+ writel(cfg, S3C2443_UCLKCON);
+}
+
+/**
+ * s3c_hsudc_complete_request - Complete a transfer request.
+ * @hsep: Endpoint to which the request belongs.
+ * @hsreq: Transfer request to be completed.
+ * @status: Transfer completion status for the transfer request.
+ */
+static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
+ struct s3c_hsudc_req *hsreq, int status)
+{
+ unsigned int stopped = hsep->stopped;
+ struct s3c_hsudc *hsudc = hsep->dev;
+
+ list_del_init(&hsreq->queue);
+ hsreq->req.status = status;
+
+ if (!ep_index(hsep)) {
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ }
+
+ hsep->stopped = 1;
+ spin_unlock(&hsudc->lock);
+ if (hsreq->req.complete != NULL)
+ hsreq->req.complete(&hsep->ep, &hsreq->req);
+ spin_lock(&hsudc->lock);
+ hsep->stopped = stopped;
+}
+
+/**
+ * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
+ * @hsep: Endpoint for which queued requests have to be terminated.
+ * @status: Transfer completion status for the transfer request.
+ */
+static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
+{
+ struct s3c_hsudc_req *hsreq;
+
+ while (!list_empty(&hsep->queue)) {
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ s3c_hsudc_complete_request(hsep, hsreq, status);
+ }
+}
+
+/**
+ * s3c_hsudc_stop_activity - Stop activity on all endpoints.
+ * @hsudc: Device controller for which EP activity is to be stopped.
+ * @driver: Reference to the gadget driver which is currently active.
+ *
+ * All the endpoints are stopped and any pending transfer requests if any on
+ * the endpoint are terminated.
+ */
+static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc,
+ struct usb_gadget_driver *driver)
+{
+ struct s3c_hsudc_ep *hsep;
+ int epnum;
+
+ hsudc->gadget.speed = USB_SPEED_UNKNOWN;
+
+ for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
+ hsep = &hsudc->ep[epnum];
+ hsep->stopped = 1;
+ s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
+ }
+
+ spin_unlock(&hsudc->lock);
+ driver->disconnect(&hsudc->gadget);
+ spin_lock(&hsudc->lock);
+}
+
+/**
+ * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
+ * @hsudc: Device controller from which setup packet is to be read.
+ * @buf: The buffer into which the setup packet is read.
+ *
+ * The setup packet received in the EP0 fifo is read and stored into a
+ * given buffer address.
+ */
+
+static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
+{
+ int count;
+
+ count = readl(hsudc->regs + S3C_BRCR);
+ while (count--)
+ *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
+
+ writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
+}
+
+/**
+ * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
+ * @hsep: Endpoint to which the data is to be written.
+ * @hsreq: Transfer request from which the next chunk of data is written.
+ *
+ * Write the next chunk of data from a transfer request to the endpoint FIFO.
+ * If the transfer request completes, 1 is returned, otherwise 0 is returned.
+ */
+static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
+ struct s3c_hsudc_req *hsreq)
+{
+ u16 *buf;
+ u32 max = ep_maxpacket(hsep);
+ u32 count, length;
+ bool is_last;
+ void __iomem *fifo = hsep->fifo;
+
+ buf = hsreq->req.buf + hsreq->req.actual;
+ prefetch(buf);
+
+ length = hsreq->req.length - hsreq->req.actual;
+ length = min(length, max);
+ hsreq->req.actual += length;
+
+ writel(length, hsep->dev->regs + S3C_BWCR);
+ for (count = 0; count < length; count += 2)
+ writel(*buf++, fifo);
+
+ if (count != max) {
+ is_last = true;
+ } else {
+ if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
+ is_last = false;
+ else
+ is_last = true;
+ }
+
+ if (is_last) {
+ s3c_hsudc_complete_request(hsep, hsreq, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
+ * @hsep: Endpoint from which the data is to be read.
+ * @hsreq: Transfer request to which the next chunk of data read is written.
+ *
+ * Read the next chunk of data from the endpoint FIFO and a write it to the
+ * transfer request buffer. If the transfer request completes, 1 is returned,
+ * otherwise 0 is returned.
+ */
+static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
+ struct s3c_hsudc_req *hsreq)
+{
+ struct s3c_hsudc *hsudc = hsep->dev;
+ u32 csr, offset;
+ u16 *buf, word;
+ u32 buflen, rcnt, rlen;
+ void __iomem *fifo = hsep->fifo;
+ u32 is_short = 0;
+
+ offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
+ csr = readl(hsudc->regs + offset);
+ if (!(csr & S3C_ESR_RX_SUCCESS))
+ return -EINVAL;
+
+ buf = hsreq->req.buf + hsreq->req.actual;
+ prefetchw(buf);
+ buflen = hsreq->req.length - hsreq->req.actual;
+
+ rcnt = readl(hsudc->regs + S3C_BRCR);
+ rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
+
+ hsreq->req.actual += min(rlen, buflen);
+ is_short = (rlen < hsep->ep.maxpacket);
+
+ while (rcnt-- != 0) {
+ word = (u16)readl(fifo);
+ if (buflen) {
+ *buf++ = word;
+ buflen--;
+ } else {
+ hsreq->req.status = -EOVERFLOW;
+ }
+ }
+
+ writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
+
+ if (is_short || hsreq->req.actual == hsreq->req.length) {
+ s3c_hsudc_complete_request(hsep, hsreq, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
+ * @hsudc - Device controller for which the interrupt is to be handled.
+ * @ep_idx - Endpoint number on which an interrupt is pending.
+ *
+ * Handles interrupt for a in-endpoint. The interrupts that are handled are
+ * stall and data transmit complete interrupt.
+ */
+static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
+ struct s3c_hsudc_req *hsreq;
+ u32 csr;
+
+ csr = readl((u32)hsudc->regs + S3C_ESR);
+ if (csr & S3C_ESR_STALL) {
+ writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
+ return;
+ }
+
+ if (csr & S3C_ESR_TX_SUCCESS) {
+ writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
+ if (list_empty(&hsep->queue))
+ return;
+
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
+ (csr & S3C_ESR_PSIF_TWO))
+ s3c_hsudc_write_fifo(hsep, hsreq);
+ }
+}
+
+/**
+ * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
+ * @hsudc - Device controller for which the interrupt is to be handled.
+ * @ep_idx - Endpoint number on which an interrupt is pending.
+ *
+ * Handles interrupt for a out-endpoint. The interrupts that are handled are
+ * stall, flush and data ready interrupt.
+ */
+static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
+ struct s3c_hsudc_req *hsreq;
+ u32 csr;
+
+ csr = readl((u32)hsudc->regs + S3C_ESR);
+ if (csr & S3C_ESR_STALL) {
+ writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
+ return;
+ }
+
+ if (csr & S3C_ESR_FLUSH) {
+ __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
+ return;
+ }
+
+ if (csr & S3C_ESR_RX_SUCCESS) {
+ if (list_empty(&hsep->queue))
+ return;
+
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
+ (csr & S3C_ESR_PSIF_TWO))
+ s3c_hsudc_read_fifo(hsep, hsreq);
+ }
+}
+
+/** s3c_hsudc_set_halt - Set or clear a endpoint halt.
+ * @_ep: Endpoint on which halt has to be set or cleared.
+ * @value: 1 for setting halt on endpoint, 0 to clear halt.
+ *
+ * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
+ * If halt is cleared, for in-endpoints, if there are any pending
+ * transfer requests, transfers are started.
+ */
+static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+ struct s3c_hsudc *hsudc = hsep->dev;
+ struct s3c_hsudc_req *hsreq;
+ unsigned long irqflags;
+ u32 ecr;
+ u32 offset;
+
+ if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
+ return -EAGAIN;
+
+ spin_lock_irqsave(&hsudc->lock, irqflags);
+ set_index(hsudc, ep_index(hsep));
+ offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
+ ecr = readl(hsudc->regs + offset);
+
+ if (value) {
+ ecr |= S3C_ECR_STALL;
+ if (ep_index(hsep))
+ ecr |= S3C_ECR_FLUSH;
+ hsep->stopped = 1;
+ } else {
+ ecr &= ~S3C_ECR_STALL;
+ hsep->stopped = hsep->wedge = 0;
+ }
+ writel(ecr, hsudc->regs + offset);
+
+ if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ if (hsreq)
+ s3c_hsudc_write_fifo(hsep, hsreq);
+ }
+
+ spin_unlock_irqrestore(&hsudc->lock, irqflags);
+ return 0;
+}
+
+/** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
+ * @_ep: Endpoint on which wedge has to be set.
+ *
+ * Sets the halt feature with the clear requests ignored.
+ */
+static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+
+ if (!hsep)
+ return -EINVAL;
+
+ hsep->wedge = 1;
+ return usb_ep_set_halt(_ep);
+}
+
+/** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
+ * @_ep: Device controller on which the set/clear feature needs to be handled.
+ * @ctrl: Control request as received on the endpoint 0.
+ *
+ * Handle set feature or clear feature control requests on the control endpoint.
+ */
+static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct s3c_hsudc_ep *hsep;
+ bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
+ u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
+
+ if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
+ hsep = &hsudc->ep[ep_num];
+ switch (le16_to_cpu(ctrl->wValue)) {
+ case USB_ENDPOINT_HALT:
+ if (set || (!set && !hsep->wedge))
+ s3c_hsudc_set_halt(&hsep->ep, set);
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+/**
+ * s3c_hsudc_process_req_status - Handle get status control request.
+ * @hsudc: Device controller on which get status request has be handled.
+ * @ctrl: Control request as received on the endpoint 0.
+ *
+ * Handle get status control request received on control endpoint.
+ */
+static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
+ struct s3c_hsudc_req hsreq;
+ struct s3c_hsudc_ep *hsep;
+ __le16 reply;
+ u8 epnum;
+
+ switch (ctrl->bRequestType & USB_RECIP_MASK) {
+ case USB_RECIP_DEVICE:
+ reply = cpu_to_le16(0);
+ break;
+
+ case USB_RECIP_INTERFACE:
+ reply = cpu_to_le16(0);
+ break;
+
+ case USB_RECIP_ENDPOINT:
+ epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
+ hsep = &hsudc->ep[epnum];
+ reply = cpu_to_le16(hsep->stopped ? 1 : 0);
+ break;
+ }
+
+ INIT_LIST_HEAD(&hsreq.queue);
+ hsreq.req.length = 2;
+ hsreq.req.buf = &reply;
+ hsreq.req.actual = 0;
+ hsreq.req.complete = NULL;
+ s3c_hsudc_write_fifo(hsep0, &hsreq);
+}
+
+/**
+ * s3c_hsudc_process_setup - Process control request received on endpoint 0.
+ * @hsudc: Device controller on which control request has been received.
+ *
+ * Read the control request received on endpoint 0, decode it and handle
+ * the request.
+ */
+static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
+ struct usb_ctrlrequest ctrl = {0};
+ int ret;
+
+ s3c_hsudc_nuke_ep(hsep, -EPROTO);
+ s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
+
+ if (ctrl.bRequestType & USB_DIR_IN) {
+ hsep->bEndpointAddress |= USB_DIR_IN;
+ hsudc->ep0state = DATA_STATE_XMIT;
+ } else {
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ hsudc->ep0state = DATA_STATE_RECV;
+ }
+
+ switch (ctrl.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
+ break;
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ return;
+
+ case USB_REQ_GET_STATUS:
+ if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
+ break;
+ s3c_hsudc_process_req_status(hsudc, &ctrl);
+ return;
+
+ case USB_REQ_SET_FEATURE:
+ case USB_REQ_CLEAR_FEATURE:
+ if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
+ break;
+ s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+
+ if (hsudc->driver) {
+ spin_unlock(&hsudc->lock);
+ ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
+ spin_lock(&hsudc->lock);
+
+ if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ }
+
+ if (ret < 0) {
+ dev_err(hsudc->dev, "setup failed, returned %d\n",
+ ret);
+ s3c_hsudc_set_halt(&hsep->ep, 1);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ }
+ }
+}
+
+/** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
+ * @hsudc: Device controller on which endpoint 0 interrupt has occured.
+ *
+ * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
+ * when a stall handshake is sent to host or data is sent/received on
+ * endpoint 0.
+ */
+static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
+ struct s3c_hsudc_req *hsreq;
+ u32 csr = readl(hsudc->regs + S3C_EP0SR);
+ u32 ecr;
+
+ if (csr & S3C_EP0SR_STALL) {
+ ecr = readl(hsudc->regs + S3C_EP0CR);
+ ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
+ writel(ecr, hsudc->regs + S3C_EP0CR);
+
+ writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
+ hsep->stopped = 0;
+
+ s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ return;
+ }
+
+ if (csr & S3C_EP0SR_TX_SUCCESS) {
+ writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
+ if (ep_is_in(hsep)) {
+ if (list_empty(&hsep->queue))
+ return;
+
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ s3c_hsudc_write_fifo(hsep, hsreq);
+ }
+ }
+
+ if (csr & S3C_EP0SR_RX_SUCCESS) {
+ if (hsudc->ep0state == WAIT_FOR_SETUP)
+ s3c_hsudc_process_setup(hsudc);
+ else {
+ if (!ep_is_in(hsep)) {
+ if (list_empty(&hsep->queue))
+ return;
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ s3c_hsudc_read_fifo(hsep, hsreq);
+ }
+ }
+ }
+}
+
+/**
+ * s3c_hsudc_ep_enable - Enable a endpoint.
+ * @_ep: The endpoint to be enabled.
+ * @desc: Endpoint descriptor.
+ *
+ * Enables a endpoint when called from the gadget driver. Endpoint stall if
+ * any is cleared, transfer type is configured and endpoint interrupt is
+ * enabled.
+ */
+static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct s3c_hsudc_ep *hsep;
+ struct s3c_hsudc *hsudc;
+ unsigned long flags;
+ u32 ecr = 0;
+
+ hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
+ if (!_ep || !desc || hsep->desc || _ep->name == ep0name
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || hsep->bEndpointAddress != desc->bEndpointAddress
+ || ep_maxpacket(hsep) < le16_to_cpu(desc->wMaxPacketSize))
+ return -EINVAL;
+
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(hsep))
+ || !desc->wMaxPacketSize)
+ return -ERANGE;
+
+ hsudc = hsep->dev;
+ if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+
+ set_index(hsudc, hsep->bEndpointAddress);
+ ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
+ writel(ecr, hsudc->regs + S3C_ECR);
+
+ hsep->stopped = hsep->wedge = 0;
+ hsep->desc = desc;
+ hsep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+
+ s3c_hsudc_set_halt(_ep, 0);
+ __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+/**
+ * s3c_hsudc_ep_disable - Disable a endpoint.
+ * @_ep: The endpoint to be disabled.
+ * @desc: Endpoint descriptor.
+ *
+ * Disables a endpoint when called from the gadget driver.
+ */
+static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+ struct s3c_hsudc *hsudc = hsep->dev;
+ unsigned long flags;
+
+ if (!_ep || !hsep->desc)
+ return -EINVAL;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+
+ set_index(hsudc, hsep->bEndpointAddress);
+ __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
+
+ s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
+
+ hsep->desc = 0;
+ hsep->stopped = 1;
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+/**
+ * s3c_hsudc_alloc_request - Allocate a new request.
+ * @_ep: Endpoint for which request is allocated (not used).
+ * @gfp_flags: Flags used for the allocation.
+ *
+ * Allocates a single transfer request structure when called from gadget driver.
+ */
+static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
+ gfp_t gfp_flags)
+{
+ struct s3c_hsudc_req *hsreq;
+
+ hsreq = kzalloc(sizeof *hsreq, gfp_flags);
+ if (!hsreq)
+ return 0;
+
+ INIT_LIST_HEAD(&hsreq->queue);
+ return &hsreq->req;
+}
+
+/**
+ * s3c_hsudc_free_request - Deallocate a request.
+ * @ep: Endpoint for which request is deallocated (not used).
+ * @_req: Request to be deallocated.
+ *
+ * Allocates a single transfer request structure when called from gadget driver.
+ */
+static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+ struct s3c_hsudc_req *hsreq;
+
+ hsreq = container_of(_req, struct s3c_hsudc_req, req);
+ WARN_ON(!list_empty(&hsreq->queue));
+ kfree(hsreq);
+}
+
+/**
+ * s3c_hsudc_queue - Queue a transfer request for the endpoint.
+ * @_ep: Endpoint for which the request is queued.
+ * @_req: Request to be queued.
+ * @gfp_flags: Not used.
+ *
+ * Start or enqueue a request for a endpoint when called from gadget driver.
+ */
+static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
+ gfp_t gfp_flags)
+{
+ struct s3c_hsudc_req *hsreq;
+ struct s3c_hsudc_ep *hsep;
+ struct s3c_hsudc *hsudc;
+ unsigned long flags;
+ u32 offset;
+ u32 csr;
+
+ hsreq = container_of(_req, struct s3c_hsudc_req, req);
+ if ((!_req || !_req->complete || !_req->buf ||
+ !list_empty(&hsreq->queue)))
+ return -EINVAL;
+
+ hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
+ hsudc = hsep->dev;
+ if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+ set_index(hsudc, hsep->bEndpointAddress);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+
+ if (!ep_index(hsep) && _req->length == 0) {
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ s3c_hsudc_complete_request(hsep, hsreq, 0);
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+ }
+
+ if (list_empty(&hsep->queue) && !hsep->stopped) {
+ offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
+ if (ep_is_in(hsep)) {
+ csr = readl((u32)hsudc->regs + offset);
+ if (!(csr & S3C_ESR_TX_SUCCESS) &&
+ (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
+ hsreq = 0;
+ } else {
+ csr = readl((u32)hsudc->regs + offset);
+ if ((csr & S3C_ESR_RX_SUCCESS)
+ && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
+ hsreq = 0;
+ }
+ }
+
+ if (hsreq != 0)
+ list_add_tail(&hsreq->queue, &hsep->queue);
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+/**
+ * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
+ * @_ep: Endpoint from which the request is dequeued.
+ * @_req: Request to be dequeued.
+ *
+ * Dequeue a request from a endpoint when called from gadget driver.
+ */
+static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+ struct s3c_hsudc *hsudc = hsep->dev;
+ struct s3c_hsudc_req *hsreq;
+ unsigned long flags;
+
+ hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
+ if (!_ep || hsep->ep.name == ep0name)
+ return -EINVAL;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+
+ list_for_each_entry(hsreq, &hsep->queue, queue) {
+ if (&hsreq->req == _req)
+ break;
+ }
+ if (&hsreq->req != _req) {
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return -EINVAL;
+ }
+
+ set_index(hsudc, hsep->bEndpointAddress);
+ s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+static struct usb_ep_ops s3c_hsudc_ep_ops = {
+ .enable = s3c_hsudc_ep_enable,
+ .disable = s3c_hsudc_ep_disable,
+ .alloc_request = s3c_hsudc_alloc_request,
+ .free_request = s3c_hsudc_free_request,
+ .queue = s3c_hsudc_queue,
+ .dequeue = s3c_hsudc_dequeue,
+ .set_halt = s3c_hsudc_set_halt,
+ .set_wedge = s3c_hsudc_set_wedge,
+};
+
+/**
+ * s3c_hsudc_initep - Initialize a endpoint to default state.
+ * @hsudc - Reference to the device controller.
+ * @hsep - Endpoint to be initialized.
+ * @epnum - Address to be assigned to the endpoint.
+ *
+ * Initialize a endpoint with default configuration.
+ */
+static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
+ struct s3c_hsudc_ep *hsep, int epnum)
+{
+ char *dir;
+
+ if ((epnum % 2) == 0) {
+ dir = "out";
+ } else {
+ dir = "in";
+ hsep->bEndpointAddress = USB_DIR_IN;
+ }
+
+ hsep->bEndpointAddress |= epnum;
+ if (epnum)
+ snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
+ else
+ snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
+
+ INIT_LIST_HEAD(&hsep->queue);
+ INIT_LIST_HEAD(&hsep->ep.ep_list);
+ if (epnum)
+ list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
+
+ hsep->dev = hsudc;
+ hsep->ep.name = hsep->name;
+ hsep->ep.maxpacket = epnum ? 512 : 64;
+ hsep->ep.ops = &s3c_hsudc_ep_ops;
+ hsep->fifo = hsudc->regs + S3C_BR(epnum);
+ hsep->desc = 0;
+ hsep->stopped = 0;
+ hsep->wedge = 0;
+
+ set_index(hsudc, epnum);
+ writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
+}
+
+/**
+ * s3c_hsudc_setup_ep - Configure all endpoints to default state.
+ * @hsudc: Reference to device controller.
+ *
+ * Configures all endpoints to default state.
+ */
+static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
+{
+ int epnum;
+
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ INIT_LIST_HEAD(&hsudc->gadget.ep_list);
+ for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
+ s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
+}
+
+/**
+ * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
+ * @hsudc: Reference to device controller.
+ *
+ * Reconfigures the device controller registers to a default state.
+ */
+static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
+{
+ writel(0xAA, hsudc->regs + S3C_EDR);
+ writel(1, hsudc->regs + S3C_EIER);
+ writel(0, hsudc->regs + S3C_TR);
+ writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
+ S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
+ writel(0, hsudc->regs + S3C_EP0CR);
+
+ s3c_hsudc_setup_ep(hsudc);
+}
+
+/**
+ * s3c_hsudc_irq - Interrupt handler for device controller.
+ * @irq: Not used.
+ * @_dev: Reference to the device controller.
+ *
+ * Interrupt handler for the device controller. This handler handles controller
+ * interrupts and endpoint interrupts.
+ */
+static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
+{
+ struct s3c_hsudc *hsudc = _dev;
+ struct s3c_hsudc_ep *hsep;
+ u32 ep_intr;
+ u32 sys_status;
+ u32 ep_idx;
+
+ spin_lock(&hsudc->lock);
+
+ sys_status = readl(hsudc->regs + S3C_SSR);
+ ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
+
+ if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
+ spin_unlock(&hsudc->lock);
+ return IRQ_HANDLED;
+ }
+
+ if (sys_status) {
+ if (sys_status & S3C_SSR_VBUSON)
+ writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
+
+ if (sys_status & S3C_SSR_ERR)
+ writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
+
+ if (sys_status & S3C_SSR_SDE) {
+ writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
+ hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
+ USB_SPEED_HIGH : USB_SPEED_FULL;
+ }
+
+ if (sys_status & S3C_SSR_SUSPEND) {
+ writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
+ if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
+ && hsudc->driver && hsudc->driver->suspend)
+ hsudc->driver->suspend(&hsudc->gadget);
+ }
+
+ if (sys_status & S3C_SSR_RESUME) {
+ writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
+ if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
+ && hsudc->driver && hsudc->driver->resume)
+ hsudc->driver->resume(&hsudc->gadget);
+ }
+
+ if (sys_status & S3C_SSR_RESET) {
+ writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
+ for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
+ hsep = &hsudc->ep[ep_idx];
+ hsep->stopped = 1;
+ s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
+ }
+ s3c_hsudc_reconfig(hsudc);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ }
+ }
+
+ if (ep_intr & S3C_EIR_EP0) {
+ writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
+ set_index(hsudc, 0);
+ s3c_hsudc_handle_ep0_intr(hsudc);
+ }
+
+ ep_intr >>= 1;
+ ep_idx = 1;
+ while (ep_intr) {
+ if (ep_intr & 1) {
+ hsep = &hsudc->ep[ep_idx];
+ set_index(hsudc, ep_idx);
+ writel(1 << ep_idx, hsudc->regs + S3C_EIR);
+ if (ep_is_in(hsep))
+ s3c_hsudc_epin_intr(hsudc, ep_idx);
+ else
+ s3c_hsudc_epout_intr(hsudc, ep_idx);
+ }
+ ep_intr >>= 1;
+ ep_idx++;
+ }
+
+ spin_unlock(&hsudc->lock);
+ return IRQ_HANDLED;
+}
+
+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
+ int (*bind)(struct usb_gadget *))
+{
+ struct s3c_hsudc *hsudc = the_controller;
+ int ret;
+
+ if (!driver
+ || (driver->speed != USB_SPEED_FULL &&
+ driver->speed != USB_SPEED_HIGH)
+ || !bind
+ || !driver->unbind || !driver->disconnect || !driver->setup)
+ return -EINVAL;
+
+ if (!hsudc)
+ return -ENODEV;
+
+ if (hsudc->driver)
+ return -EBUSY;
+
+ hsudc->driver = driver;
+ hsudc->gadget.dev.driver = &driver->driver;
+ hsudc->gadget.speed = USB_SPEED_UNKNOWN;
+ ret = device_add(&hsudc->gadget.dev);
+ if (ret) {
+ dev_err(hsudc->dev, "failed to probe gadget device");
+ return ret;
+ }
+
+ ret = bind(&hsudc->gadget);
+ if (ret) {
+ dev_err(hsudc->dev, "%s: bind failed\n", hsudc->gadget.name);
+ device_del(&hsudc->gadget.dev);
+
+ hsudc->driver = NULL;
+ hsudc->gadget.dev.driver = NULL;
+ return ret;
+ }
+
+ enable_irq(hsudc->irq);
+ dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
+
+ s3c_hsudc_reconfig(hsudc);
+ s3c_hsudc_init_phy();
+ if (hsudc->pd->gpio_init)
+ hsudc->pd->gpio_init();
+
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_probe_driver);
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct s3c_hsudc *hsudc = the_controller;
+ unsigned long flags;
+
+ if (!hsudc)
+ return -ENODEV;
+
+ if (!driver || driver != hsudc->driver || !driver->unbind)
+ return -EINVAL;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+ hsudc->driver = 0;
+ s3c_hsudc_uninit_phy();
+ if (hsudc->pd->gpio_uninit)
+ hsudc->pd->gpio_uninit();
+ s3c_hsudc_stop_activity(hsudc, driver);
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+
+ driver->unbind(&hsudc->gadget);
+ device_del(&hsudc->gadget.dev);
+ disable_irq(hsudc->irq);
+
+ dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
+ driver->driver.name);
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
+{
+ return readl(hsudc->regs + S3C_FNR) & 0x3FF;
+}
+
+static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
+{
+ return s3c_hsudc_read_frameno(to_hsudc(gadget));
+}
+
+static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
+ .get_frame = s3c_hsudc_gadget_getframe,
+};
+
+static int s3c_hsudc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct s3c_hsudc *hsudc;
+ struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
+ int ret;
+
+ hsudc = kzalloc(sizeof(struct s3c_hsudc) +
+ sizeof(struct s3c_hsudc_ep) * pd->epnum,
+ GFP_KERNEL);
+ if (!hsudc) {
+ dev_err(dev, "cannot allocate memory\n");
+ return -ENOMEM;
+ }
+
+ the_controller = hsudc;
+ platform_set_drvdata(pdev, dev);
+ hsudc->dev = dev;
+ hsudc->pd = pdev->dev.platform_data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "unable to obtain driver resource data\n");
+ ret = -ENODEV;
+ goto err_res;
+ }
+
+ hsudc->mem_rsrc = request_mem_region(res->start, resource_size(res),
+ dev_name(&pdev->dev));
+ if (!hsudc->mem_rsrc) {
+ dev_err(dev, "failed to reserve register area\n");
+ ret = -ENODEV;
+ goto err_res;
+ }
+
+ hsudc->regs = ioremap(res->start, resource_size(res));
+ if (!hsudc->regs) {
+ dev_err(dev, "error mapping device register area\n");
+ ret = -EBUSY;
+ goto err_remap;
+ }
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "unable to obtain IRQ number\n");
+ goto err_irq;
+ }
+ hsudc->irq = ret;
+
+ ret = request_irq(hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc);
+ if (ret < 0) {
+ dev_err(dev, "irq request failed\n");
+ goto err_irq;
+ }
+
+ spin_lock_init(&hsudc->lock);
+
+ device_initialize(&hsudc->gadget.dev);
+ dev_set_name(&hsudc->gadget.dev, "gadget");
+
+ hsudc->gadget.is_dualspeed = 1;
+ hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
+ hsudc->gadget.name = dev_name(dev);
+ hsudc->gadget.dev.parent = dev;
+ hsudc->gadget.dev.dma_mask = dev->dma_mask;
+ hsudc->gadget.ep0 = &hsudc->ep[0].ep;
+
+ hsudc->gadget.is_otg = 0;
+ hsudc->gadget.is_a_peripheral = 0;
+
+ s3c_hsudc_setup_ep(hsudc);
+
+ hsudc->uclk = clk_get(&pdev->dev, "usb-device");
+ if (IS_ERR(hsudc->uclk)) {
+ dev_err(dev, "failed to find usb-device clock source\n");
+ return PTR_ERR(hsudc->uclk);
+ }
+ clk_enable(hsudc->uclk);
+
+ local_irq_disable();
+
+ disable_irq(hsudc->irq);
+ local_irq_enable();
+ return 0;
+
+err_irq:
+ iounmap(hsudc->regs);
+
+err_remap:
+ release_resource(hsudc->mem_rsrc);
+ kfree(hsudc->mem_rsrc);
+
+err_res:
+ kfree(hsudc);
+ return ret;
+}
+
+static struct platform_driver s3c_hsudc_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "s3c-hsudc",
+ },
+ .probe = s3c_hsudc_probe,
+};
+
+static int __init s3c_hsudc_modinit(void)
+{
+ return platform_driver_register(&s3c_hsudc_driver);
+}
+
+static void __exit s3c_hsudc_modexit(void)
+{
+ platform_driver_unregister(&s3c_hsudc_driver);
+}
+
+module_init(s3c_hsudc_modinit);
+module_exit(s3c_hsudc_modexit);
+
+MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
+MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index b015561fd60..1fa4f705b0b 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -708,13 +708,14 @@ static ssize_t fsg_show_file(struct device *dev, struct device_attribute *attr,
static ssize_t fsg_store_ro(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
- ssize_t rc = count;
+ ssize_t rc;
struct fsg_lun *curlun = fsg_lun_from_dev(dev);
struct rw_semaphore *filesem = dev_get_drvdata(dev);
- unsigned long ro;
+ unsigned ro;
- if (strict_strtoul(buf, 2, &ro))
- return -EINVAL;
+ rc = kstrtouint(buf, 2, &ro);
+ if (rc)
+ return rc;
/*
* Allow the write-enable status to change only while the
@@ -728,6 +729,7 @@ static ssize_t fsg_store_ro(struct device *dev, struct device_attribute *attr,
curlun->ro = ro;
curlun->initially_ro = ro;
LDBG(curlun, "read-only status set to %d\n", curlun->ro);
+ rc = count;
}
up_read(filesem);
return rc;
@@ -738,10 +740,12 @@ static ssize_t fsg_store_nofua(struct device *dev,
const char *buf, size_t count)
{
struct fsg_lun *curlun = fsg_lun_from_dev(dev);
- unsigned long nofua;
+ unsigned nofua;
+ int ret;
- if (strict_strtoul(buf, 2, &nofua))
- return -EINVAL;
+ ret = kstrtouint(buf, 2, &nofua);
+ if (ret)
+ return ret;
/* Sync data when switching from async mode to sync */
if (!nofua && curlun->nofua)
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-10-17 16:31:42 +0000